01 Mar, 2014
2 commits
-
Add new AEMIF driver for EMIF16 Texas Instruments controller.
The EMIF16 module is intended to provide a glue-less interface to
a variety of asynchronous memory devices like ASRA M, NOR and NAND
memory. A total of 256M bytes of any of these memories can be
accessed at any given time via 4 chip selects with 64M byte access
per chip select.Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR
are not supported.This controller is used on SoCs like Davinci, Keysone2
Acked-by: Santosh Shilimkar
Signed-off-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk
Signed-off-by: Greg Kroah-Hartman -
commit d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc ("driver/memory:Move
Freescale IFC driver to a common driver") introduces this build
regression into the mpc85xx_defconfig:drivers/built-in.o: In function `fsl_ifc_nand_remove':
drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev'
drivers/built-in.o: In function `fsl_ifc_nand_probe':
drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev'
drivers/built-in.o: In function `match_bank':
drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to `convert_ifc_address'
drivers/built-in.o: In function `fsl_ifc_nand_probe':
drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev'
drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev'
make: *** [vmlinux] Error 1This happens because there is nothing to descend us into the
drivers/memory directory in the mpc85xx_defconfig. It wasn't
selecting CONFIG_MEMORY. So we never built drivers/memory/fsl_ifc.o
and so we have nothing to link the above symbols against.Since the goal of the original commit was to relocate the driver to
an arch independent location, it only makes sense to relocate the
Kconfig setting there as well. But that alone won't fix the build
failure; for that we ensure whoever selects FSL_IFC also selects MEMORY.Cc: Prabhakar Kushwaha
Cc: Scott Wood
Cc: Arnd Bergmann
Cc: David Woodhouse
Cc: Greg Kroah-Hartman
Signed-off-by: Paul Gortmaker
Signed-off-by: Greg Kroah-Hartman
19 Feb, 2014
1 commit
-
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/memory
and fix the header file includes.Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall() to make sure this module
has been loaded before MTD partition parsing starts.Signed-off-by: Prabhakar Kushwaha
Acked-by: Arnd Bergmann
Signed-off-by: Greg Kroah-Hartman
07 Sep, 2013
1 commit
-
Pull ARM SoC platform changes from Olof Johansson:
"This branch contains mostly additions and changes to platform
enablement and SoC-level drivers. Since there's sometimes a
dependency on device-tree changes, there's also a fair amount of
those in this branch.Pieces worth mentioning are:
- Mbus driver for Marvell platforms, allowing kernel configuration
and resource allocation of on-chip peripherals.
- Enablement of the mbus infrastructure from Marvell PCI-e drivers.
- Preparation of MSI support for Marvell platforms.
- Addition of new PCI-e host controller driver for Tegra platforms
- Some churn caused by sharing of macro names between i.MX 6Q and 6DL
platforms in the device tree sources and header files.
- Various suspend/PM updates for Tegra, including LP1 support.
- Versatile Express support for MCPM, part of big little support.
- Allwinner platform support for A20 and A31 SoCs (dual and quad
Cortex-A7)
- OMAP2+ support for DRA7, a new Cortex-A15-based SoC.The code that touches other architectures are patches moving MSI
arch-specific functions over to weak symbols and removal of
ARCH_SUPPORTS_MSI, acked by PCI maintainers"* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)
tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE
PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource
ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list
ARM: dts: vf610-twr: enable i2c0 device
ARM: dts: i.MX51: Add one more I2C2 pinmux entry
ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
ARM: dts: i.MX27: Disable AUDMUX in the template
ARM: dts: wandboard: Add support for SDIO bcm4329
ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
ARM: dts: imx53-qsb: Make USBH1 functional
ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
ARM: dts: imx6qdl-sabresd: Add touchscreen support
ARM: imx: add ocram clock for imx53
ARM: dts: imx: ocram size is different between imx6q and imx6dl
ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
ARM: dts: i.MX27: Remove clock name from CPU node
...
16 Aug, 2013
1 commit
-
Remove unneeded error handling on the result of a call to
platform_get_resource when the value is passed to devm_ioremap_resource.A simplified version of the semantic patch that makes this change is as
follows: (http://coccinelle.lip6.fr/)//
@@
expression pdev,res,n,e,e1;
expression ret != 0;
identifier l;
@@- res = platform_get_resource(pdev, IORESOURCE_MEM, n);
... when != res
- if (res == NULL) { ... \(goto l;\|return ret;\) }
... when != res
+ res = platform_get_resource(pdev, IORESOURCE_MEM, n);
e = devm_ioremap_resource(e1, res);
//Signed-off-by: Julia Lawall
Signed-off-by: Stephen Warren
13 Aug, 2013
1 commit
-
This variable is not being used anywhere and it's only forgotten
garbage that should have been removed in the previous commit:commit 9b6e4c0a58e24c28bd757c9365824a37e80b751c
Author: Ezequiel Garcia
Date: Fri Jul 26 10:17:38 2013 -0300memory: mvebu-devbus: Remove address decoding window workaround
Signed-off-by: Ezequiel Garcia
Signed-off-by: Jason Cooper
06 Aug, 2013
1 commit
-
Now that mbus device tree binding has been introduced, remove the address
decoding window management from this driver.
A suitable 'ranges' entry should be added to the devbus-compatible node in
the device tree, as described by the mbus binding documentation.Acked-by: Greg Kroah-Hartman
Signed-off-by: Ezequiel Garcia
Tested-by: Andrew Lunn
Tested-by: Sebastian Hesselbarth
Signed-off-by: Jason Cooper
18 Jun, 2013
2 commits
-
In Tegra30 any memory controller interrupt would cause an infinite loop in the
IRQ handler. Additionally, a garbage pointer was used to read the MC
status registers, which causes wrong values to be printed if a MC error
occurred.Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Stephen Warren
Reviewed-by: Thierry Reding
Signed-off-by: Greg Kroah-Hartman -
In Tegra20 any memory controller interrupt would cause an
infinite loop in the IRQ handler.Signed-off-by: Tuomas Tynkkynen
Reviewed-by: Stephen Warren
Reviewed-by: Thierry Reding
Signed-off-by: Greg Kroah-Hartman
27 May, 2013
1 commit
-
We want the changes in here.
Signed-off-by: Greg Kroah-Hartman
22 May, 2013
1 commit
-
Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and
Discovery (mv78xx0) supports a Device Bus controller to access several
kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA).This commit adds a driver to handle this controller. So far only
Armada 370, Armada XP and Discovery SoCs are supported.The driver must be registered through a device tree node;
as explained in the binding document.For each child node in the device tree, this driver will:
* set timing parameters
* register a child device
* setup an address decoding window, using the mbus driverKeep in mind the address decoding window setup is only a temporary hack.
This code will be removed from this devbus driver as soon as a proper device
tree binding for the mbus driver is added.Signed-off-by: Ezequiel Garcia
Acked-by: Arnd Bergmann
Acked-by: Jason Cooper
Signed-off-by: Greg Kroah-Hartman
18 May, 2013
1 commit
-
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.Signed-off-by: Wolfram Sang
26 Mar, 2013
8 commits
-
of_get_property returns value in Big Endian format.
Before using this value it should be converted to little endian
using be32_to_cpup().
Custom configs of emif are read from dt using of_get_property,
but these are not converted to litte endian format.
Correcting the same here.Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman -
ERRATA DESCRIPTION :
The EMIF supports power-down state for low power. The EMIF
automatically puts the SDRAM into power-down after the memory is
not accessed for a defined number of cycles and the
EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
As the EMIF supports automatic output impedance calibration, a ZQ
calibration long command is issued every time it exits active
power-down and precharge power-down modes. The EMIF waits and
blocks any other command during this calibration.
The EMIF does not allow selective disabling of ZQ calibration upon
exit of power-down mode. Due to very short periods of power-down
cycles, ZQ calibration overhead creates bandwidth issues and
increases overall system power consumption. On the other hand,
issuing ZQ calibration long commands when exiting self-refresh is
still required.WORKAROUND :
Because there is no power consumption benefit of the power-down due
to the calibration and there is a performance risk, the guideline
is to not allow power-down state and, therefore, to not have set
the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.This is applicable only for EMIF4D IP used in OMAP4 Soc's.
Signed-off-by: Grygorii Strashko
Signed-off-by: Vitaly Chernooky
Signed-off-by: Oleksandr Dmytryshyn
Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman -
The issue was that only the first timings table was added to the
emif platform data at the emif driver registration. All other
timings tables was filled with zeros. Now all emif timings table
are added to the platform data.Signed-off-by: Oleksandr Dmytryshyn
Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman -
Some machine or kernel variants might have missed implementation
of power off handlers. We DONOT want to let the system be in
"out of spec" state in this condition. So, WARN and attempt
a machine restart in the hopes of clearing the out-of-spec
temperature condition.NOTE: This is not the safest option, but safer than leaving the
system in unstable conditions.Signed-off-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman -
As per JESD209-2E specification for LPDDR2,
http://www.jedec.org/standards-documents/results/jesd209-2E
Table 73, LPDDR2 memories come in two flavors - Standard and
Extended. The Standard types can operate from -25C to +85C
However, beyond that and upto +105C can only be supported by
Extended types.Unfortunately, it seems there is no info in MR0(device info) or
MR[1,2](device feature) for run time detection of this capability
as far as seen on the spec. Hence, we provide a custom_config
flag to be populated by platforms which have these "extended"
type memories.For the "Standard" memories, we need to consider MR4 notifications
of temperature triggers >85C as equivalent to thermal shutdown
events (equivalent to Spec specified thermal shutdown events for
"extended" parts).Reported-by: Richard Woodruff
Signed-off-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman -
In case the custom timings provide values which overflow
the maximum possible field value, warn and use maximum
permissible value.Signed-off-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman -
Program the power management shadow register on freq update
Else the concept of threshold frequencies dont really matter
as the system always uses the performance mode timing for LP
which is programmed in at init time.Signed-off-by: Nishanth Menon
Signed-off-by: Ambresh K
Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman -
The driver tries to round up the specified timeout cycles to
the next power of 2 value. This should be done defore updating
timeout variable.
Correcting this here.Reported-by: Nishanth Menon
Signed-off-by: Lokesh Vutla
Acked-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman
16 Mar, 2013
2 commits
-
This patch converts the drivers to use the
module_platform_driver_probe() macro which makes the code smaller and
a bit simpler.Signed-off-by: Fabio Porcedda
Cc: Benoit Cousson
Cc: Aneesh V
Signed-off-by: Greg Kroah-Hartman -
Make this depend on CONFIG_PM.
Signed-off-by: Hiroshi Doyu
Reviewed-by: Thierry Reding
Signed-off-by: Greg Kroah-Hartman
23 Jan, 2013
1 commit
-
Convert all uses of devm_request_and_ioremap() to the newly introduced
devm_ioremap_resource() which provides more consistent error handling.devm_ioremap_resource() provides its own error messages so all explicit
error messages can be removed from the failure code paths.Signed-off-by: Thierry Reding
Signed-off-by: Greg Kroah-Hartman
04 Jan, 2013
1 commit
-
CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
markings need to be removed.This change removes the use of __devinit, __devexit_p, and
__devinitconst, from these drivers.Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.Cc: Bill Pemberton
Cc: Hiroshi DOYU
Cc: Stephen Warren
Cc: Axel Lin
Signed-off-by: Greg Kroah-Hartman
27 Sep, 2012
2 commits
-
The code reading the register does not match the code writing to the register,
fix it.Also fix the coding style in mc_writel() for better readability.
Signed-off-by: Axel Lin
Acked-by: Stephen Warren
Tested-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman -
Add ifdef CONFIG_DEBUG_FS guard for emif_debugfs_[init|exit], and adds stub
functions for the case CONFIG_DEBUG_FS is not set.When CONFIG_DEBUG_FS is enabled, debugfs_create_dir and debugfs_create_file
return NULL on failure, fix it.Signed-off-by: Axel Lin
Acked-by : Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman
06 Sep, 2012
1 commit
-
Commit e6b42eb "memory: emif: add device tree support to emif driver"
added drivers/memory/of_memory.c, which references tables defined in
lib/jedec_ddr_data.c. of_memory.c is compiled when CONFIG_OF, whereas
jedec_ddr_data.c is compiled when CONFIG_DDR. This breaks the build
when CONFIG_OF is defined but not CONFIG_DDR:drivers/built-in.o: In function `of_get_ddr_timings':
drivers/memory/of_memory.c:138: undefined reference to `lpddr2_jedec_timings'
drivers/built-in.o: In function `of_get_min_tck':
drivers/memory/of_memory.c:62: undefined reference to `lpddr2_jedec_min_tck'
make: *** [vmlinux] Error 1To solve this, only compile of_memory.c when CONFIG_OF && CONFIG_DDR,
otherwise, stub out the functions.Signed-off-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman
05 Sep, 2012
1 commit
-
Device tree support for the EMIF driver. LPDDR2 generic timings
extraction from device is managed using couple of helper
functions which can be used by other memory controller
drivers.Reviewed-by: Benoit Cousson
Reviewed-by: Grant Likely
Tested-by: Lokesh Vutla
Signed-off-by: Aneesh V
Signed-off-by: Santosh Shilimkar
Cc: Greg Kroah-Hartman
Signed-off-by: Greg Kroah-Hartman
15 May, 2012
1 commit
-
Remove unnecessary empty functions.
Signed-off-by: Hiroshi DOYU
Signed-off-by: Greg Kroah-Hartman
14 May, 2012
1 commit
-
Introduce a new dev_*_ratelimited() instead of pr_*_ratelimited() for
better info to print.Signed-off-by: Hiroshi DOYU
Signed-off-by: Greg Kroah-Hartman
12 May, 2012
4 commits
-
For bare minimal system.
Signed-off-by: Hiroshi DOYU
Acked-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman -
For bare minimal system.
Signed-off-by: Hiroshi DOYU
Acked-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman -
Accessing interleaved MC register offsets/ranges are verified. BUG*()s
in accessors can be removed.Signed-off-by: Hiroshi DOYU
Signed-off-by: Greg Kroah-Hartman -
Accessing interleaved MC register offsets/ranges are verified. BUG*()s
in accessors can be removed.Signed-off-by: Hiroshi DOYU
Signed-off-by: Greg Kroah-Hartman
11 May, 2012
2 commits
-
Tegra Memory Controller(MC) driver for Tegra30
Added to support MC General interrupts, mainly for IOMMU(SMMU).Signed-off-by: Hiroshi DOYU
Acked-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman -
Tegra Memory Controller(MC) driver for Tegra20
Added to support MC General interrupts, mainly for IOMMU(GART).Signed-off-by: Hiroshi DOYU
Acked-by: Stephen Warren
Signed-off-by: Greg Kroah-Hartman
05 May, 2012
1 commit
-
Make TI_EMIF depends on ARCH_OMAP2PLUS to avoid build breaks on other
architectures. In future if other TI non OMAP socs start using it, the
dependency can be extended.Signed-off-by: Santosh Shilimkar
Reported-by: Paul Gortmaker
Cc: Greg Kroah-Hartman
Signed-off-by: Greg Kroah-Hartman
03 May, 2012
3 commits
-
Add debug entries for:
1. calculated registers per frequency
2. last polled value of MR4(temperature level
of LPDDR2 memory)Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Tested-by: Lokesh Vutla
Signed-off-by: Greg Kroah-Hartman -
Add settings that are not dependent on frequency
or any other transient parameters. This includes
- power managment control init
- impedence calibration control
- frequency independent phy configuration registers
- initialization of temperature pollingSigned-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Tested-by: Lokesh Vutla
Signed-off-by: Greg Kroah-Hartman -
Add an ISR for EMIF that:
1. reports details of access errors
2. takes action on thermal eventsAlso clear all interrupts on shut-down. Pending IRQs
may casue problems during warm-reset.Temperature handling:
EMIF can be configured to poll the temperature level
of an LPDDR2 device from the MR4 mode register in the
device. EMIF generates an interrupt whenever it identifies
a temperature level change between two consecutive pollings.Some of the timing parameters need to be de-rated at high
temperatures. The interrupt handler takes care of doing
this and also takes care of going back to nominal settings
when temperature falls back to nominal levels.Signed-off-by: Aneesh V
Reviewed-by: Santosh Shilimkar
Reviewed-by: Benoit Cousson
[santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar
Signed-off-by: Greg Kroah-Hartman