01 Oct, 2014
1 commit
-
In 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to
64-bit resources"), we added IORESOURCE_MEM_64 to the mask in
pci_assign_unassigned_root_bus_resources(), but not to the mask in
pci_assign_unassigned_bridge_resources().Add IORESOURCE_MEM_64 to the pci_assign_unassigned_bridge_resources() type
mask.Fixes: 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
CC: stable@vger.kernel.org # v3.16+
09 Jul, 2014
1 commit
-
Increase the maximum BAR size from 8GB to 128GB.
[bhelgaas: changelog]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
11 Jun, 2014
2 commits
-
Merge quoted strings that are broken across lines into a single entity.
The compiler merges them anyway, but checkpatch complains about it, and
merging them makes it easier to grep for strings.No functional change.
[bhelgaas: changelog, do the same for everything under drivers/pci]
Signed-off-by: Ryan Desfosses
Signed-off-by: Bjorn Helgaas -
Fix various whitespace errors.
No functional change.
[bhelgaas: fix other similar problems]
Signed-off-by: Ryan Desfosses
Signed-off-by: Bjorn Helgaas
29 May, 2014
1 commit
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* pci/hotplug:
PCI: cpqphp: Fix possible null pointer dereference
NVMe: Implement PCIe reset notification callback
PCI: Notify driver before and after device reset* pci/pci_is_bridge:
pcmcia: Use pci_is_bridge() to simplify code
PCI: pciehp: Use pci_is_bridge() to simplify code
PCI: acpiphp: Use pci_is_bridge() to simplify code
PCI: cpcihp: Use pci_is_bridge() to simplify code
PCI: shpchp: Use pci_is_bridge() to simplify code
PCI: rpaphp: Use pci_is_bridge() to simplify code
sparc/PCI: Use pci_is_bridge() to simplify code
powerpc/PCI: Use pci_is_bridge() to simplify code
ia64/PCI: Use pci_is_bridge() to simplify code
x86/PCI: Use pci_is_bridge() to simplify code
PCI: Use pci_is_bridge() to simplify code
PCI: Add new pci_is_bridge() interface
PCI: Rename pci_is_bridge() to pci_has_subordinate()* pci/virtualization:
PCI: Introduce new device binding path using pci_dev.driver_overrideConflicts:
drivers/pci/pci-sysfs.c
28 May, 2014
1 commit
-
Use pci_is_bridge() to simplify code. No functional change.
Requires: 326c1cdae741 PCI: Rename pci_is_bridge() to pci_has_subordinate()
Requires: 1c86438c9423 PCI: Add new pci_is_bridge() interface
Signed-off-by: Yijing Wang
Signed-off-by: Bjorn Helgaas
27 May, 2014
1 commit
-
* dma-api:
iommu/exynos: Remove unnecessary "&" from function pointers
DMA-API: Update dma_pool_create ()and dma_pool_alloc() descriptions
DMA-API: Fix duplicated word in DMA-API-HOWTO.txt
DMA-API: Capitalize "CPU" consistently
sh/PCI: Pass GAPSPCI_DMA_BASE CPU & bus address to dma_declare_coherent_memory()
DMA-API: Change dma_declare_coherent_memory() CPU address to phys_addr_t
DMA-API: Clarify physical/bus address distinction* pci/virtualization:
PCI: Mark RTL8110SC INTx masking as broken* pci/msi:
PCI/MSI: Remove pci_enable_msi_block()* pci/misc:
PCI: Remove pcibios_add_platform_entries()
s390/pci: use pdev->dev.groups for attribute creation
PCI: Move Open Firmware devspec attribute to PCI common code* pci/resource:
PCI: Add resource allocation comments
PCI: Simplify __pci_assign_resource() coding style
PCI: Change pbus_size_mem() return values to be more conventional
PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources
PCI: Support BAR sizes up to 8GB
resources: Clarify sanity check message
PCI: Don't add disabled subtractive decode bus resources
PCI: Don't print anything while decoding is disabled
PCI: Don't set BAR to zero if dma_addr_t is too small
PCI: Don't convert BAR address to resource if dma_addr_t is too small
PCI: Reject BAR above 4GB if dma_addr_t is too small
PCI: Fail safely if we can't handle BARs larger than 4GB
x86/gart: Tidy messages and add bridge device info
x86/gart: Replace printk() with pr_info()
x86/PCI: Move pcibios_assign_resources() annotation to definition
x86/PCI: Mark ATI SBx00 HPET BAR as IORESOURCE_PCI_FIXED
x86/PCI: Don't try to move IORESOURCE_PCI_FIXED resources
x86/PCI: Fix Broadcom CNB20LE unintended sign extension
24 May, 2014
4 commits
-
Add comments in the code to match the allocation strategy of 7c671426dfc3
("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources").No functional change.
Signed-off-by: Bjorn Helgaas
-
pbus_size_mem() previously returned 0 for failure and 1 for success.
Change it to return -ENOSPC for failure and 0 for success.No functional change.
Signed-off-by: Bjorn Helgaas
-
This patch changes the way we handle 64-bit prefetchable bridge windows to
make it more likely that we can assign space to all devices.Previously we put all prefetchable resources in the prefetchable bridge
window. If any of those resources was 32-bit only, we restricted the
window to be below 4GB.After this patch, we only put 64-bit prefetchable resources in a 64-bit
prefetchable window. We put all 32-bit prefetchable resources in the
non-prefetchable window, even if there are no 64-bit prefetchable
resources.With the previous approach, if there was a 32-bit prefetchable resource
behind a bridge, we forced the bridge's prefetchable window below 4GB,
which meant that even if there was plenty of space above 4GB available, we
couldn't use it, and assignment of large 64-bit resources could fail, as
in the bugzilla below.The new strategy is:
1) If the prefetchable window is 64 bits wide, we put only 64-bit
prefetchable resources in it. Any 32-bit prefetchable resources go in
the non-prefetchable window.2) If the prefetchable window is 32 bits wide, we put both 32- and 64-bit
prefetchable resources in it.3) If there is no prefetchable window, all MMIO resources go in the
non-prefetchable window.This reduces performance for 32-bit prefetchable resources below a bridge
with a 64-bit prefetchable window. We previously assigned prefetchable
space, but now we'll assign non-prefetchable space. This is the case even
if there are no 64-bit prefetchable resources, or if they would all fit
below 4GB. In those cases, the old strategy would work and would have
better performance.[bhelgaas: write changelog, add bugzilla link, fold in mem64_mask removal]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=74151
Tested-by: Guo Chao
Tested-by: Wei Yang
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
This is needed for some of the Xeon Phi type systems.
[bhelgaas: added Nikhil, use ARRAY_SIZE() to connect with decl, folded in
Kevin's "order < 0" fix to ARRAY_SIZE() usage]
Signed-off-by: Nikhil P Rao
Signed-off-by: Alan Cox
Signed-off-by: Kevin Hilman
Signed-off-by: Bjorn Helgaas
30 Apr, 2014
1 commit
-
Some PCI functions used to be marked __devinit. When CONFIG_HOTPLUG was
not set, these functions were discarded after boot. A few callers of these
__devinit functions were marked __ref to indicate that they could safely
call the __devinit functions even though the callers were not __devinit.But CONFIG_HOTPLUG and __devinit are now gone, and the need for the __ref
annotations is also gone, so remove them. Relevant historical commits:54b956b90360 Remove __dev* markings from init.h
a8e4b9c101ae PCI: add generic pci_hp_add_bridge()
0ab2b57f8db8 PCI: fix section mismatch warning in pci_scan_child_bus
451124a7cc6c PCI: fix 4x section mismatch warningsSigned-off-by: Bjorn Helgaas
11 Jan, 2014
1 commit
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* pci/resource:
PCI: Allocate 64-bit BARs above 4G when possible
PCI: Enforce bus address limits in resource allocation
PCI: Split out bridge window override of minimum allocation address
agp/ati: Use PCI_COMMAND instead of hard-coded 4
agp/intel: Use CPU physical address, not bus address, for ioremap()
agp/intel: Use pci_bus_address() to get GTTADR bus address
agp/intel: Use pci_bus_address() to get MMADR bus address
agp/intel: Support 64-bit GMADR
agp/intel: Rename gtt_bus_addr to gtt_phys_addr
drm/i915: Rename gtt_bus_addr to gtt_phys_addr
agp: Use pci_resource_start() to get CPU physical address for BAR
agp: Support 64-bit APBASE
PCI: Add pci_bus_address() to get bus address of a BAR
PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
PCI: Change pci_bus_region addresses to dma_addr_t
22 Dec, 2013
1 commit
-
These interfaces:
pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region)took a pci_dev, but they really depend only on the pci_bus. And we want to
use them in resource allocation paths where we have the bus but not a
device, so this patch converts them to take the pci_bus instead of the
pci_dev:pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource)
pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region)In fact, with standard PCI-PCI bridges, they only depend on the host
bridge, because that's the only place address translation occurs, but
we aren't going that far yet.[bhelgaas: changelog]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
13 Dec, 2013
2 commits
-
pci_setup_bridge_io() accessed PCI_IO_BASE and PCI_IO_LIMIT using dword
(32-bit) reads and writes, which also access the Secondary Status register.
Since the Secondary Status register is in the upper 16 bits of the dword,
and we preserved those upper 16 bits, this had the effect of clearing any
of the write-1-to-clear bits that happened to be set in the Secondary
Status register.That's not what we want, so use word (16-bit) accesses to update only
PCI_IO_BASE and PCI_IO_LIMIT.Signed-off-by: Bjorn Helgaas
-
pci_bridge_check_ranges() determines whether the bridge supports an I/O
aperture and a prefetchable memory aperture.Previously, if the I/O aperture was unsupported, disabled, or configured at
[io 0x0000-0x0fff], we wrote 0xf0 to PCI_IO_BASE and PCI_IO_LIMIT, which,
if the bridge supports it, enables the I/O aperture at [io 0xf000-0xffff].
The enabled aperture may conflict with other devices in the system.Similarly, we wrote 0xfff0 to PCI_PREF_MEMORY_BASE and
PCI_PREF_MEMORY_LIMIT, which enables the prefetchable memory aperture at
[mem 0xfff00000-0xffffffff], and that may also conflict with other devices.All we need to know is whether the base and limit registers are writable,
so we can use values that leave the apertures disabled, e.g., PCI_IO_BASE =
0xf0, PCI_IO_LIMIT = 0xe0, PCI_PREF_MEMORY_BASE = 0xfff0,
PCI_PREF_MEMORY_LIMIT = 0xffe0.Writing non-zero values to both the base and limit registers means we
detect whether either or both are writable, as we did before.Reported-by: Jason Gunthorpe
Based-on-patch-by: Jason Gunthorpe
Signed-off-by: Bjorn Helgaas
15 Nov, 2013
1 commit
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Fix whitespace, capitalization, and spelling errors. No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.Signed-off-by: Marta Rybczynska (pci_reset_bridge_secondary_bus())
Signed-off-by: Bjorn Helgaas
Acked-by: Rafael J. Wysocki
26 Sep, 2013
2 commits
-
When calculating window_alignment(), type information like IORESOURCE_MEM
and IORESOURCE_PREFETCH may not be enough. For example, on powernv, we
need to know whether the window is 64-bit or not.This patch passes the full resource type (res->flags) for window alignment.
[bhelgaas: changelog]
Signed-off-by: Wei Yang
Signed-off-by: Bjorn Helgaas
Acked-by: Gavin Shan -
In __pci_bus_size_bridges() we check whether a bus is a root bus by testing
bus->self. As indicated by commit 79af72d7 ("PCI: pci_is_root_bus
helper"), bus->self == NULL is not a proper way to check for a root bus.
One issue is that "virtual" buses added for SR-IOV (via virtfn_add_bus())
have bus->self == NULL but are not root buses.This patch changes it to pci_is_root_bus() to check whether it is a root
bus.[bhelgaas: changelog]
Signed-off-by: Wei Yang
Signed-off-by: Bjorn Helgaas
04 Sep, 2013
1 commit
-
Pull PCI changes from Bjorn Helgaas:
PCI device hotplug:
- Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
- Assign resources on per-host bridge basis (Yinghai Lu)MPS (Max Payload Size):
- Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
- Add warnings about unsafe MPS settings (Yijing Wang)
- Simplify interface and messages (Bjorn Helgaas)SR-IOV:
- Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
- Update NumVFs register when disabling SR-IOV (Yijing Wang)Virtualization:
- Add bus and slot reset support (Alex Williamson)
- Fix ACS (Access Control Services) issues (Alex Williamson)Miscellaneous:
- Simplify PCIe Capability accessors (Bjorn Helgaas)
- Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
- Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
- Delay enabling bridges until they're needed (Yinghai Lu)
- Split Designware support into Synopsys and Exynos parts (Jingoo Han)
- Convert class code to use dev_groups (Greg Kroah-Hartman)
- Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
- Fix bridge I/O window alignment (Bjorn Helgaas)
- Add pci_wait_for_pending_transaction() (Casey Leedom)
- Use devm_ioremap_resource() in Marvell driver (Tushar Behera)* tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits)
PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
PCI: exynos: Add I/O access wrappers
PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()
PCI: Remove pcie_cap_has_devctl()
PCI: Support PCIe Capability Slot registers only for ports with slots
PCI: Remove PCIe Capability version checks
PCI: Allow PCIe Capability link-related register access for switches
PCI: Add offsets of PCIe capability registers
PCI: Tidy bitmasks and spacing of PCIe capability definitions
PCI: Remove obsolete comment reference to pci_pcie_cap2()
PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment
PCI: Rename PCIe capability definitions to follow convention
PCI: Warn if unsafe MPS settings detected
PCI: Fix MPS peer-to-peer DMA comment syntax
PCI: Disable decoding for BAR sizing only when it was actually enabled
PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n
PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality
PCI: Don't restrict MPS for slots below Root Ports
PCI: Simplify MPS test for Downstream Port
PCI: Remove unnecessary check for pcie_get_mps() failure
...
27 Aug, 2013
1 commit
-
* pci/yinghai-assign-unassigned-v6:
PCI: Assign resources for hot-added host bridge more aggressively
PCI: Move resource reallocation code to non-__init
PCI: Delay enabling bridges until they're needed
PCI: Assign resources on a per-bus basis
PCI: Enable unassigned resource reallocation on per-bus basis
PCI: Turn on reallocation for unassigned resources with host bridge offset
PCI: Look for unassigned resources on per-bus basis
PCI: Drop temporary variable in pci_assign_unassigned_resources()
06 Aug, 2013
1 commit
-
An upstream bridge's I/O window must be at least as aligned as any
downstream device or bridge requires. In particular, if the upstream
bridge supports 1K alignment but a downstream bridge requires 4K alignment,
the upstream window must also be 4K aligned.Therefore, do not reduce the required alignment ("min_align") based on
the upstream bridge's capabilities.Reported-by: Wei Yang
Suggested-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
03 Aug, 2013
3 commits
-
This patch changes the type of "size" to resource_size_t and makes the
corresponding dev_printk() change.[bhelgaas: changelog]
Signed-off-by: Wei Yang
Signed-off-by: Bjorn Helgaas -
This patch fills in the missing description for two parameters of
pbus_size_mem().Signed-off-by: Wei Yang
Signed-off-by: Bjorn Helgaas -
Normally, on one PCI bus there would be more devices than bridges. When
calculating the depth of a PCI bus, it would be more time efficient to
enumerating through the child buses instead of the child devices.Also by doing so, the code seems more self explaining. Previously, it went
through the devices and checked whether a bridge introduced a child bus or
not, which needs more background knowledge to understand it.This patch calculates the depth by enumerating the bus hierarchy.
Signed-off-by: Wei Yang
Signed-off-by: Bjorn Helgaas
26 Jul, 2013
9 commits
-
Ben Herrenschmidt reported the following problem:
- The bus has space for all desired MMIO resources, including optional
space for SR-IOV devices
- We attempt to allocate I/O port space, but it fails because the bus
has no I/O space
- Because of the I/O allocation failure, we retry MMIO allocation,
requesting only the required space, without the optional SR-IOV spaceThis means we don't allocate the optional SR-IOV space, even though we
could.This is related to 0c5be0cb0e ("PCI: Retry on IORESOURCE_IO type
allocations").This patch changes how we handle allocation failures. We will now retry
allocation of only the resource type that failed. If MMIO allocation
fails, we'll retry only MMIO allocation. If I/O port allocation fails,
we'll retry only I/O port allocation.[bhelgaas: changelog]
Reference: https://lkml.kernel.org/r/1367712653.11982.19.camel@pasglop
Reported-by: Benjamin Herrenschmidt
Tested-by: Gavin Shan
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
CC: stable@vger.kernel.org # v3.10+ -
When hot-adding an ACPI host bridge, use
pci_assign_unassigned_root_bus_resources() instead of
pci_assign_unassigned_bus_resources().The former is more aggressive and will release and reassign existing
resources if necessary. This is safe at hot-add time because no drivers
are bound to devices below the new host bridge yet.[bhelgaas: changelog, split __init changes out for reviewability]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
Resource reallocation is currently done only at boot-time, but will
soon be done when host bridge is hot-added. This patch removes the
__init annotations so the code will still be present after boot.[bhelgaas: split __init changes out]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
We currently enable PCI bridges after scanning a bus and assigning
resources. This is often done in arch code.This patch changes this so we don't enable a bridge until necessary, i.e.,
until we enable a PCI device behind the bridge. We do this in the generic
pci_enable_device() path, so this also removes the arch-specific code to
enable bridges.[bhelgaas: changelog]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
Previously, we did resource assignment globally. This patch splits up
pci_assign_unassigned_resources() so assignment is done for each root bus
in turn. We check each root bus individually to see whether it needs any
reassignment, and if it does, we assign resources for just that bus.[bhelgaas: changelog]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
pci_realloc_detect() turns on automatic resource allocation when it finds
unassigned SR-IOV resources. Previously it did this on a global basis, so
we enabled reallocation if any PCI device anywhere had an unassigned SR-IOV
resource.This patch changes pci_realloc_detect() so it looks at a single bus, so we
can do this when a host bridge is hot-added.[bhelgaas: changelog]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
Previously we did not turn on automatic PCI resource reallocation for
unassigned IOV resources behind a host bridge with address offset. This
patch fixes that bug.The intent was that "!r->start" would check for a BAR containing zero. But
that check is incorrect for host bridges that apply an offset, because in
that case the resource address is not the same as the bus address.This patch fixes that by converting the resource address back to a bus
address before checking for zero.[bhelgaas: changelog]
Suggested-by: Benjamin Herrenschmidt
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
When CONFIG_PCI_REALLOC_ENABLE_AUTO=y, pci_realloc_detect() looks at PCI
devices to see if any have SR-IOV resources that need to be assigned. If
it finds any, it turns on automatic resource reallocation.This patch changes pci_realloc_detect() so it uses pci_walk_bus() on
each root bus instead of using for_each_pci_dev(). This is a step
toward doing reallocation on a per-bus basis, so we can do it for
a hot-added host bridge.[bhelgaas: changelog, rename callback to iov_resources_unassigned(), use
boolean for "unassigned"]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
Drop the "bus" temporary variable. No functional change, but simplifies
later patch slightly.[bhelgaas: changelog, make same change in
pci_assign_unassigned_bridge_resources() to keep it parallel with
pci_assign_unassigned_resources()]
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
23 Jun, 2013
1 commit
-
On x86 platforms, the kernel respects PCI resource assignments from
the BIOS and only reassigns resources for unassigned BARs at boot
time. However, with the ACPI-based hotplug (acpiphp), it ignores the
BIOS' PCI resource assignments completely and reassigns all resources
by itself. This causes differences in PCI resource allocation
between boot time and runtime hotplug to occur, which is generally
undesirable and sometimes actively breaks things.Namely, if there are enough resources, reassigning all PCI resources
during runtime hotplug should work, but it may fail if the resources
are constrained. This may happen, for instance, when some PCI
devices with huge MMIO BARs are involved in the runtime hotplug
operations, because the current PCI MMIO alignment algorithm may
waste huge chunks of MMIO address space in those cases.On the Alexander's Sony VAIO VPCZ23A4R the BIOS allocates limited
MMIO resources for the dock station which contains a device
(graphics adapter) with a 256MB MMIO BAR. An attempt to reassign
that during runtime hotplug causes the dock station MMIO window to be
exhausted and acpiphp fails to allocate resources for the majority
of devices on the dock station as a result.To prevent that from happening, modify acpiphp to follow the boot
time resources allocation behavior so that the BIOS' resource
assignments are respected during runtime hotplug too.[rjw: Changelog]
References: https://bugzilla.kernel.org/show_bug.cgi?id=56531
Reported-and-tested-by: Alexander E. Patrakov
Tested-by: Illya Klymov
Signed-off-by: Jiang Liu
Acked-by: Yinghai Lu
Cc: 3.9+
Signed-off-by: Rafael J. Wysocki
18 Apr, 2013
1 commit
-
These places capture return values to avoid "must_check" warnings,
but we didn't *do* anything with the return values, which causes
"set but not used" warnings. We might as well do something instead
of just trying to evade the "must_check" warnings.Signed-off-by: Bjorn Helgaas
13 Apr, 2013
1 commit
-
This fixes "no previous prototype" warnings found via "make W=1".
Signed-off-by: Bjorn Helgaas
26 Jan, 2013
1 commit
-
We can stop trying according to try_number now and do not need to use
root_bus checking as stop sign.In extreme case we could need to reallocate resource for device just
under root bus. For PCI root bus hot-add, we need to retry to assign
resources to PCI devices just under pci root bus.Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas
Acked-by: Rafael J. Wysocki
04 Nov, 2012
2 commits
-
So could use assign_unassigned_bus_res pci root bus add
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas -
We have pci_assign_unassigned_bus_resources() in as global function now.
Move pci_rescan_bus() back to probe.c where it should be.
Signed-off-by: Yinghai Lu
Signed-off-by: Bjorn Helgaas