15 Dec, 2009

3 commits


26 Nov, 2009

1 commit

  • Limit the number of per cpu TSC sync messages by only printing
    to the console if an error occurs, otherwise print as a DEBUG
    message.

    The info message "Skipping synchronization ..." is only printed
    after the last cpu has booted.

    Signed-off-by: Mike Travis
    Cc: Heiko Carstens
    Cc: Roland Dreier
    Cc: Randy Dunlap
    Cc: Tejun Heo
    Cc: Andi Kleen
    Cc: Greg Kroah-Hartman
    Cc: Yinghai Lu
    Cc: David Rientjes
    Cc: Steven Rostedt
    Cc: Rusty Russell
    Cc: Hidetoshi Seto
    Cc: Jack Steiner
    Cc: Frederic Weisbecker
    LKML-Reference:
    Signed-off-by: Ingo Molnar

    Mike Travis
     

24 Sep, 2009

1 commit

  • On modern systems, the kernel prints the message

    Skipping synchronization checks as TSC is reliable.

    once for every non-boot CPU.

    This gets kind of ridiculous on huge systems; for example, on a
    64-thread system I was lucky enough to get:

    $ dmesg | grep 'TSC is reliable' | wc
    63 567 4221

    There's no point to doing this for every CPU, since the code is
    just checking the boot CPU anyway, so change this to a
    printk_once() to make the message appears only once.

    Signed-off-by: Roland Dreier
    LKML-Reference:
    Signed-off-by: Ingo Molnar

    Roland Dreier
     

07 May, 2009

1 commit


23 Dec, 2008

1 commit

  • …86/debug', 'x86/defconfig', 'x86/detect-hyper', 'x86/doc', 'x86/dumpstack', 'x86/early-printk', 'x86/fpu', 'x86/idle', 'x86/io', 'x86/memory-corruption-check', 'x86/microcode', 'x86/mm', 'x86/mtrr', 'x86/nmi-watchdog', 'x86/pat2', 'x86/pci-ioapic-boot-irq-quirks', 'x86/ptrace', 'x86/quirks', 'x86/reboot', 'x86/setup-memory', 'x86/signal', 'x86/sparse-fixes', 'x86/time', 'x86/uv' and 'x86/xen' into x86/core

    Ingo Molnar
     

18 Nov, 2008

1 commit

  • Impact: fix incorrectly marked unstable TSC clock

    Patch (commit 0d12cdd "sched: improve sched_clock() performance") has
    a regression on one of the test systems here.

    With the patch, I see:

    checking TSC synchronization [CPU#0 -> CPU#1]:
    Measured 28 cycles TSC warp between CPUs, turning off TSC clock.
    Marking TSC unstable due to check_tsc_sync_source failed

    Whereas, without the patch syncs pass fine on all CPUs:

    checking TSC synchronization [CPU#0 -> CPU#1]: passed.

    Due to this, TSC is marked unstable, when it is not actually unstable.
    This is because syncs in check_tsc_wrap() goes away due to this commit.

    As per the discussion on this thread, correct way to fix this is to add
    explicit syncs as below?

    Signed-off-by: Venkatesh Pallipadi
    Signed-off-by: Ingo Molnar

    Venki Pallipadi
     

02 Nov, 2008

1 commit

  • Impact: Changes timebase calibration on Vmware.

    Use the synthetic TSC_RELIABLE bit to workaround virtualization anomalies.

    Virtual TSCs can be kept nearly in sync, but because the virtual TSC
    offset is set by software, it's not perfect. So, the TSC
    synchronization test can fail. Even then the TSC can be used as a
    clocksource since the VMware platform exports a reliable TSC to the
    guest for timekeeping purposes. Use this bit to check if we need to
    skip the TSC sync checks.

    Along with this also set the CONSTANT_TSC bit when on VMware, since we
    still want to use TSC as clocksource on VM running over hardware which
    has unsynchronized TSC's (opteron's), since the hypervisor will take
    care of providing consistent TSC to the guest.

    Signed-off-by: Alok N Kataria
    Signed-off-by: Dan Hecht
    Signed-off-by: H. Peter Anvin

    Alok Kataria
     

21 Aug, 2008

1 commit

  • Use WARN() instead of a printk+WARN_ON() pair; this way the message
    becomes part of the warning section for better reporting/collection.
    This also allowed the folding of some if()'s into the WARN()

    Signed-off-by: Arjan van de Ven
    Cc: akpm@linux-foundation.org
    Signed-off-by: Ingo Molnar

    Arjan van de Ven
     

30 Jan, 2008

4 commits

  • add warning to check_tsc_warp() - if get_cycles() does not progress.

    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Ingo Molnar
     
  • 100 million max # of loops is a bit too much - reduce it to 10 million.

    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Ingo Molnar
     
  • rdtsc is now speculation-safe, so no need for the sync variants of
    the APIs.

    [ mingo@elte.hu: removed the nsec_barrier() complication. ]

    Signed-off-by: Andi Kleen
    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Andi Kleen
     
  • s2ram recently became useful here, except for the kernel's annoying
    habit of disabling my P4's perfectly good TSC.

    [ 107.894470] CPU 1 is now offline
    [ 107.894474] SMP alternatives: switching to UP code
    [ 107.895832] CPU0 attaching sched-domain:
    [ 107.895836] domain 0: span 1
    [ 107.895838] groups: 1
    [ 107.896097] CPU1 is down
    [ 3.726156] Intel machine check architecture supported.
    [ 3.726165] Intel machine check reporting enabled on CPU#0.
    [ 3.726167] CPU0: Intel P4/Xeon Extended MCE MSRs (12) available
    [ 3.726170] CPU0: Thermal monitoring enabled
    [ 3.726175] Back to C!
    [ 3.726708] Force enabled HPET at resume
    [ 3.726775] Enabling non-boot CPUs ...
    [ 3.727049] CPU0 attaching NULL sched-domain.
    [ 3.727165] SMP alternatives: switching to SMP code
    [ 3.727858] Booting processor 1/1 eip 3000
    [ 3.727862] CPU 1 irqstacks, hard=b042f000 soft=b042d000
    [ 3.738173] Initializing CPU#1
    [ 3.798912] Calibrating delay using timer specific routine.. 5986.12 BogoMIPS (lpj=2993061)
    [ 3.798920] CPU: After generic identify, caps: bfebfbff 00000000 00000000 00000000 00004400 00000000 00000000 00000000
    [ 3.798931] CPU: Trace cache: 12K uops, L1 D cache: 8K
    [ 3.798934] CPU: L2 cache: 512K
    [ 3.798936] CPU: Physical Processor ID: 0
    [ 3.798938] CPU: After all inits, caps: bfebfbff 00000000 00000000 0000b080 00004400 00000000 00000000 00000000
    [ 3.798946] Intel machine check architecture supported.
    [ 3.798952] Intel machine check reporting enabled on CPU#1.
    [ 3.798955] CPU1: Intel P4/Xeon Extended MCE MSRs (12) available
    [ 3.798959] CPU1: Thermal monitoring enabled
    [ 3.799161] CPU1: Intel(R) Pentium(R) 4 CPU 3.00GHz stepping 09
    [ 3.799187] checking TSC synchronization [CPU#0 -> CPU#1]:
    [ 3.819181] Measured 63588552840 cycles TSC warp between CPUs, turning off TSC clock.
    [ 3.819184] Marking TSC unstable due to: check_tsc_sync_source failed.

    If check_tsc_warp() is called after initial boot, and the TSC has in the
    meantime been set (BIOS, user, silicon, elves) to a value lower than the
    last stored/stale value, we blame the TSC. Reset to pristine condition
    after every test.

    Signed-off-by: Mike Galbraith
    Signed-off-by: Ingo Molnar
    Signed-off-by: Thomas Gleixner

    Mike Galbraith
     

14 Oct, 2007

1 commit

  • Since the x86 merge, lots of files that referenced their own filenames
    are no longer correct. Rather than keep them up to date, just delete
    them, as they add no real value.

    Additionally:
    - fix up comment formatting in scx200_32.c
    - Remove a credit from myself in setup_64.c from a time when we had no SCM
    - remove longwinded history from tsc_32.c which can be figured out from
    git.

    Signed-off-by: Dave Jones
    Signed-off-by: Linus Torvalds

    Dave Jones
     

11 Oct, 2007

2 commits