05 Dec, 2015
4 commits
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Add support to the keystone remoteproc driver for managing the
DSP present in the Keystone 2 Galileo (K2G) SoC. The K2G SoC has
a Power Management Micro Controller (PMMC) that manages the
individual device's power, clock and reset functionalities.The keystone remoteproc driver already uses standard frameworks
for reset and clock control, so it doesn't require any significant
modifications other than a new compatible suitable for K2G DSP.The binding document is also updated to reflect the modified
property values used by the K2G DSP node as compared to the
values used by existing Keystone 2 DSPs.NOTE:
The enhancement to use common pm_runtime framework for all Keystone
2 SoCs is left for a future time. The redundata clock API usage for
K2G does not impact any functionality, but is still required for
other K2 SoCs.Signed-off-by: Suman Anna
Signed-off-by: Andrew F. Davis -
The Keystone remoteproc driver has already been enhanced to
support using the reset framework API for managing the DSP
device resets. All the existing DSP DT nodes have also been
switched to use the 'resets' property instead of the deprecated
'ti,syscon-psc' property.All the Keystone 2 family of SoCs are expected to be using reset
drivers going forward, so drop the support for the direct syscon
PSC based reset handling from the driver completely. The DT
binding has also been updated accordingly.While at this, also add a build dependency for the driver
against the RESET_CONTROLLER Kconfig, and switch to using the
devm_reset_control_get() API instead of the optional variant.Signed-off-by: Andrew F. Davis
[s-anna@ti.com: mandatory reset dependencies, binding updates]
Signed-off-by: Suman Anna -
The Keystone family of SoCs has the reset registers as part of the
Power and Sleep Controller (PSC) module. The keystone remoteproc
driver currently manages these DSP resets by itself through the
regmap/syscon API.Enhance the keystone remoteproc driver to start using the reset
framework API for managing resets. This is being done to streamline
the driver usage for supporting the DSP on Keystone 2 Galileo (K2G)
SoC. This also switches the driver to use a more standard framework
for resets.The support is added as an incremental change, so the regmap/syscon
framework is used as a fallback to support the transition of the
Keystone 2 DSP DTS nodes from using 'ti,psc-syscon' to the 'resets'
property.Signed-off-by: Andrew F. Davis
[s-anna@ti.com: add error checking, checkpatch fixes, binding updates]
Signed-off-by: Suman Anna -
…nel/platform-linux-feature-tree into rproc-linux-4.1.y
Resync with the latest platform base code. The merge pulls in various
required patches, fixes and new features including the following:
- A new SYSCON reset driver that will be used by Keystone 2
remoteproc driver for K2HK/L/E SoCs
- Device nodes for Device State Controller, IRQ Controller for
receiving interrupts from remoteprocs, and a DSP GPIO Controller
for sending interrupts to DSPs on Keystone 2 Galileo SoC
- Fixes in the TI SCI protocol to work with latest updates on the
PMMC firmware for isolating reset control from clock control ops
for K2G reset driver functionality
- A new TI SCI reset driver that will be used by Keystone 2
remoteproc driver for K2G SoCOther updates include
- Clock updates to various Keystone 2 Galileo DTS nodes
- LDO/SMPS fixes on AM57xx IDK boards
- Various config fragments improvements to enable reset
framework and drivers* 'platform-ti-linux-4.1.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (53 commits)
ARM: dts: k2g: Add DSP GPIO controller node
ARM: dts: k2g: Add keystone IRQ controller node
ARM: dts: k2g: Add device state controller node
ti_config_fragments/baseport: Enable TI SCI reset driver
ARM: dts: k2g: Add TI SCI reset-controller node
reset: Add the TI SCI reset driver
Documentation: dt: reset: Add TI SCI reset binding
dt-bindings: reset: Add k2g reset definitions
ti_config_fragments/baseport: enable reset-syscon driver
ARM: Keystone: Enable ARCH_HAS_RESET_CONTROLLER
ARM: dts: keystone: Add PSC reset node
reset: add a SYSCON based reset driver
Documentation: dt: reset: Add syscon reset binding
ARM: OMAP2+: omap_hwmod: Always restore saved hardreset context
hwmon: (tmp102) Force wait for conversion time for the first valid data
ti_config_fragments/baseport: Build thermal into kernel
firmware: ti_sci: Add device_resets calls to the device ops
firmware: ti_sci: Drop resets field from ti_sci_set_device_state calls
ARM: dts: k2g: Fix Message Manager interrupt polarity
baseport.cfg: Enable SYSTEM V IPC
...Signed-off-by: Suman Anna <s-anna@ti.com>
04 Dec, 2015
2 commits
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Add TI SCI reset controller binding. This describes the DT binding
details for a reset controller node providing reset management services
to hardware blocks (reset consumers) using the Texas Instrument's System
Control Interface (TI SCI) protocol to communicate to a system controller
block present on the SoC.Signed-off-by: Andrew F. Davis
[s-anna@ti.com: revise the binding format]
Signed-off-by: Suman Anna
Acked-by: Nishanth Menon -
Add syscon reset controller binding. This will hook to the reset
framework and use syscon/regmap to set reset bits. This allows
reset control of individual SoC subsytems and devices with
memory-mapped reset registers in a common register memory
space.Signed-off-by: Andrew F. Davis
[s-anna@ti.com: revise the binding format]
Signed-off-by: Suman Anna
13 Nov, 2015
1 commit
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Pull in the updated mailbox feature branch into the remoteproc
tree for adding mailboxes to the PRU-ICSS PRU cores on AM572x
and AM571x IDKs.The merge also brings in the up-to-date platform tree with
support for OPP_HIGH support on IVA and DSP DPLLs.* 'mailbox-linux-4.1.y' of git://git.ti.com/rpmsg/mailbox:
ARM: dts: am57xx-idk-common: Enable the system mailboxes 3 and 4
ARM: dts: DRA72x: Add sub-mailbox nodes for all PRUSS1 & PRUSS2
ARM: dts: k2g: Remove voltage-ranges property from MMC nodes
HACK: ARM: dts: am571x-idk: Configure DSP & IVA clocks for OPP_HIGH
HACK: ARM: dts: am572x-idk: Configure DSP & IVA clocks for OPP_HIGH
HACK: ARM: dts: am57xx-beagle-x15: Configure DSP & IVA clocks for OPP_HIGH
HACK: ARM: dts: dra72-evm: Configure DSP & IVA clocks for OPP_HIGH
HACK: ARM: dts: dra7-evm: Configure DSP and IVA clocks for OPP_HIGH
ti_config_fragments/baseport: Enable CONFIG_REGULATOR
ARM: dts: k2g: Enable edma
ARM: common: edma: Switch to platform_driver_register
ARM: dts: k2g: add clock support
clk: keystone: add sci-clk driver support
dt-binding: clock: add k2g clock definitions
Documentation: dt: Add TI SCI clock
ARM: dts: am437x-idk-evm: Add opp disable exception for OPP50
ARM: OMAP2+: opp: Add opp exception checking
Documentation: dt: omap: opp: Add opp exception binding docs
ARM: OMAP2+: opp: Fix comment block for opp_def_list_enable_opp
dmaengine: edma: fix residue race for cyclicSigned-off-by: Suman Anna
12 Nov, 2015
2 commits
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Add a clock implementation, TI SCI clock, that will hook to the common
clock framework, and allow each clock to be controlled via TI SCI protocol.Signed-off-by: Tero Kristo
Tested-by: Dave Gerlach -
Add documentation for new ti,opp-enable-exception and
ti,opp-disable-exception to allow board specific changes to OPP tables.Signed-off-by: Dave Gerlach
Reviewed-by: Nishanth Menon
10 Nov, 2015
3 commits
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Add the device tree binding document for the userspace memory mapping
driver on Keystone SoCs.The binding status is unstable, as this might be redone completely
to accomplish this in a saner fashion.Signed-off-by: Suman Anna
-
Add the device tree bindings document for the Texas Instrument's
Keystone 2 DSP remoteproc devices.Signed-off-by: Sam Nelson
Signed-off-by: Suman Anna -
…nel/platform-linux-feature-tree into rproc-linux-4.1.y
Resync with the latest platform base code. The merge pulls in various
required patches, fixes and new features including the following:
- Keystone 2 PSC node required by Keystone 2 remoteproc driver
- Keystone 2 Galileo SoC support
- Initial support for AM572x and AM571x IDKs
- Various config fragments improvements and fixes* 'platform-ti-linux-4.1.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (57 commits)
ti_config_fragments/baseport: enable REGULATOR_FIXED_VOLTAGE
memory: ti_emif_pm: Use CONFIG_PM_SLEEP to avoid build warning
soc: ti: wkup_m3_ipc: Clean up pm_ops to prevent build warnings
firmware: ti_sci: Add support for Clock control
ARM: dts: keystone: Add PSC node
dmaengine: edma: special case slot limit workaround
ti_config_fragments/baseport: Enable TI SCI PM domains
ARM: dts: k2g: Add power-domains and handles to all available device nodes
soc: ti: Add ti_sci_pm_domains driver
Documentation: dt: Add TI SCI PM Domains
firmware: ti_sci: Add support for Device control
firmware: ti_sci: Switch over flags to bitfields
ARM: dts: k2g: Update PMMC debug region
HACK: firmware: ti_sci: Move mailbox ticker after the tick
ARM: dts: AM571x-IDK Initial Support
Documentation: devicetree: bindings: arm: omap: omap.txt
ARM: DTS: AM57xx-idk-common.dtsi and AM572x-idk.dts
PM / Domains: Return -EPROBE_DEFER if we fail to init or turn-on domain
firmware: Fix build error when TI_SCI_PROTOCOL=m
HACK: ARM: DRA7: hwmod_data: Prevent wait_target_disable error for usb_otg_ss
...Signed-off-by: Suman Anna <s-anna@ti.com>
06 Nov, 2015
1 commit
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Add a generic power domain implementation, TI SCI PM Domains, that will
hook into the genpd framework and allow each PD, which will be created
one per device, to be managed over the TI SCI protocol.Signed-off-by: Dave Gerlach
05 Nov, 2015
1 commit
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Added board definition for the AM571x-idk board.
Signed-off-by: Schuyler Patton
Reviewed-by: Lokesh Vutla
30 Oct, 2015
2 commits
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Texas Instrument's System Control Interface (TI-SCI) Message Protocol
is used in Texas Instrument's System on Chip (SoC) such as those
in newer SoCs in the keystone processor family starting with K2G.
This message protocol is used to communicate between various compute
entities (such as processors like ARM, DSP etc.) with a central system
controller entity.TI-SCI message protocol provides support for management of various
hardware entitites within the SoC.The message protocol can be found here: TBD.
Signed-off-by: Nishanth Menon
-
Message Manager is a hardware block used to communicate with various
processor systems within certain Texas Instrument's Keystone
generation SoCs.This hardware engine is used to transfer messages from various compute
entities(or processors) within the SoC. It is designed to be self
contained without needing software initialization for operation.Signed-off-by: Nishanth Menon
27 Oct, 2015
1 commit
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K2G SoC family is the newest version of the Keystone family of processors.
Add new bindings for K2G and the K2G evm. Also document these new bindings.
Signed-off-by: Nishanth Menon
Signed-off-by: Franklin S Cooper Jr
Tested-by: Lokesh Vutla
24 Oct, 2015
1 commit
-
…nel/platform-linux-feature-tree into rproc-linux-4.1.y
Resync with the latest platform base code. The merge pulls in various
fixes and new features including the following:
- Support for AM572x IDK
- Support for larger RAMs on DRA7 platforms (LPAE support)
- SoC-specific compatibles support for Keystone SoCs* 'platform-ti-linux-4.1.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (62 commits)
mtd: nand: omap: print resource_size_t as %pa
drivers: net: davinci_cpdma: Fix build warning with LPAE enabled
ti_config_fragments: Enable LPAE for dra7_only.cfg
ARM: dts: DRA7: change address-cells and size-cells
ARM: OMAP2+: Fix oops with LPAE and more than 2GB of memory
ARM: OMAP2+: pm33xx: Wrap static vars used for suspend in CONFIG_SUSPEND
rtc: ds1307: Fix alarm programming for mcp794xx
drivers: power: build when voltage domain is selected as well
ARM: dts: AM572x-IDK Initial Support
Documentation: devicetree: bindings: regulator: palmas-pmic.txt
Documentation: devicetree: bindings: arm: omap: omap.txt
ARM: omap: wakeupgen: Fix build error with !CONFIG_CPU_PM
irqchip: omap-intc: add support for spurious irq handling
genirq: Export handle_bad_irq
dmaengine: edma: Optimize memcpy operation
dmaengine: edma: Remove alignment constraint for memcpy
ARM: cmpxchg: avoid warnings from macro-ized cmpxchg() implementations
ARM: dts: omap5-uevm: Add Uart wakeup interrupt
ARM: dts: omap5-uevm.dts: fix i2c5 pinctrl offsets
PM / Runtime: Update last_busy in rpm_resume
...Signed-off-by: Suman Anna <s-anna@ti.com>
20 Oct, 2015
2 commits
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Adding support for the tps659038 pmic so it doesn't generate a warning
when running the patch check script to
Documentation/devicetree/bindings/regulator/palmas-pmic.txtAdding a note that the tps659037 device is a OTP spin of the
tps659038 pmic and device compatible.Signed-off-by: Schuyler Patton
-
Added board definition for the AM572x-idk board.
Signed-off-by: Schuyler Patton
09 Oct, 2015
1 commit
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commit 8841cbf666d63e6b108ba741aa07e06ac7171de1 upstream.
Keystone2 devices are used on more platforms than just Texas
Instruments reference evaluation platforms called EVMs. Providing a
generic compatible "ti,keystone" is not sufficient to differentiate
various SoC definitions possible on various platforms for the
following reasons:
a) Userspace applications have no way of knowing which SoC they are
functioning, providing the compatible matches provide a mechanism for
them to enable SoC specific functionality. Such userspace applications
are typically automated test framework or SoC custom hardware
acceleration entitlement from a common file system.
b) Provides an accurate hardware description. This allows
SoC specific logic to be run time handled based on
of_machine_is_compatible("ti,k2hk") or as needed for the dependent
processor instead of needing to use board dependent compatibles that
are needed now.Hence, provide compatible matches for each SoC in the Keystone family.
Acked-By: Murali Karicheri
Signed-off-by: Nishanth Menon
Signed-off-by: Santosh Shilimkar
28 Aug, 2015
1 commit
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This patch adds the bindings for the Programmable Real-Time Unit and
Industrial Communication Subsystem (PRU-ICSS) present on various TI
SoCs (that are adapted for DT boot). The binding uses standard DT
properties without introducing any specific properties.Signed-off-by: Suman Anna
12 Aug, 2015
1 commit
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Merge in the updated iommu feature branch into the remoteproc tree.
This merge pulls in the OMAP IOMMU driver support for both the DRA74x
and DRA72x SoC families, and on the DRA7 EVM, DRA72 EVM and AM57xx
Beagle X15 boards.* 'iommu-linux-4.1.y' of git://git.ti.com/rpmsg/iommu:
ARM: OMAP2+: Regroup IOMMU pdata quirks for DRA7
ARM: dts: beagle-x15: Enable relevant IPU and DSP MMU nodes
ARM: dts: dra72-evm: Enable relevant IPU and DSP MMU nodes
ARM: dts: dra7-evm: Enable relevant IPU and DSP MMU nodes
iommu/omap: add support to program multiple iommus
iommu/omap: change the attach detection logic
ARM: OMAP2+: devices: Use sentinel terminated iommu archdata for ISP
ARM: OMAP2+: Extend iommu pdata-quirks to DRA74x DSP2
ARM: OMAP2+: Extend iommu pdata-quirks to DRA7 IPUs & DSP1
ARM: DRA7: hwmod data: Add MMU data for DSP2
ARM: DRA7: hwmod data: Add MMU data for IPUs & DSP1
ARM: dts: DRA74x: Add IOMMU nodes for DSP2
ARM: dts: DRA7: Add common IOMMU nodes
iommu/omap: Add support for configuring dsp iommus on DRA7xx
Documentation: dt: Update OMAP iommu bindings for DRA7 DSPs
ARM: dts: DRA74x: Add dsp2_system syscon node
ARM: dts: DRA7: Add dsp1_system syscon nodeSigned-off-by: Suman Anna
11 Aug, 2015
1 commit
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Add the device tree bindings document for OMAP4+ remoteproc
devices.Signed-off-by: Suman Anna
08 Aug, 2015
2 commits
-
The DSP processor sub-systems on DRA7xx have two MMU instances
each, one for the processor core and the other for an internal
EDMA block. These MMUs need an additional shared register to be
programmed in the DSP_SYSTEM sub-module to be enabled properly.The OMAP IOMMU bindings is updated to account for this additional
syscon property required for these DSP IOMMU instances on DRA7xx
SoCs. A new compatible "ti,dra7-dsp-iommu" is also defined to
distinguish these devices specifically from other DRA7 IOMMU
devices.An example of the DRA7 DSP IOMMU nodes is also added to the
document for clarity.Signed-off-by: Suman Anna
[s-anna@ti.com: cherry-pick linux-omap patchwork id '6838681'] -
…nel/platform-linux-feature-tree into iommu-linux-4.1.y
Pull in the platform base tree for the required DPLL clock rate
settings on the DPLL_IVA (OMAP4/OMAP5 SoCs) and DPLL_DSP & DPLL_IVA
(DRA7 SoCs) DPLLs. These configure the frequencies of the functional
clocks required by the IOMMUs and their correponding processors
at OPP_NOM. These were previously running at bypass frequencies.The pull also brings in base PM functionality as well as ARM Errata
fixes and others.* 'platform-ti-linux-4.1.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (280 commits)
ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates
ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates
ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL
ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates
ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates
ARM: OMAP5 / DRA7: Introduce workaround for 801819
ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA
ARM: OMAP: Check for clocks which do not have parents
ARM: dts: am335x: Update vdd_mpu max voltage
ARM: dts: am437x-gp-evm: Add pinctrl for debugss pins
leds: leds-gpio: Enhance pinctrl support
OMAP: AM437X: Add rtc_only with ddr in self-refresh support
rtc: OMAP: Add support for rtc-only mode
ARM: AM33XX: Add rtc only support
ARM: dts: am437x-sk-evm: disable DDR regulator in rtc-only/poweroff mode
regulator: tps65218: do not disable DCDC3 during poweroff on broken PMICs
mfd: tps65218: add version check to the PMIC probe
ARM: dts: am437x-gp-evm: disable DDR regulator in rtc-only/poweroff mode
regulator: tps65218: force set power-up/down strobe to 3 for dcdc3
ARM: dts: AM437X-GP-EVM: AM437X-SK-EVM: Make dcdc3 dcdc5 and dcdc6 enable during suspend
...Signed-off-by: Suman Anna <s-anna@ti.com>
27 Jul, 2015
2 commits
-
EPOS evms are fitted with a separate family of am43xx SoCs and are named
am438x series. Adding a separate soc_is function to identify that
particular series of SoCs. This can be done to avoid unnecessarily
registering hwmods like rtc when not needed on EPOS evms.
The last specific number of the part is unknown yet so keeping it generic
am438'x'.Signed-off-by: Keerthy
-
Based on the board property switch the source from internal
to external clock. Switching to external source is needed for
rtcwake to work in low power modes.Signed-off-by: Keerthy
25 Jul, 2015
1 commit
-
SoCs such as DRA7 family from Texas Instruments also include a highly
configurable hardware block called the IOdelay block. This block
allows very specific custom fine tuning for electrical characteristics
of IO pins.In addition to the regular pin muxing modes supported by the
pinctrl-single, additional configuration for this block for specific
pins may also be mandatory in certain cases.It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors, which during mux
or IODelay reconfiguration, has a potential for a significant glitch
which may cause functional impairment to certain hardware. It is hence
recommended to do as little of muxing as absolutely necessary without
IO isolation (which can only be done in initial stages of bootloader).Even with the above limitation, certain functionality such as MMC may
mandate the need of IODelay reconfiguration depending on speed of
transfer. Hence, introduce a new binding to facilitate programming the
same.Signed-off-by: Nishanth Menon
23 Jul, 2015
1 commit
-
OMAP platforms have multiple voltage domains, but each with consistent
behavior of controlling the VDD (supply) and also possibly
VBB(ABB/Bias voltage).These need to be sequenced in a specific order for functionality.
Further optimization such as AVS(Adaptive Voltage Scaling) can be
introduced on this basic framework. This patch already provides for
reading optimized voltages from efuse (Class0) for SoCs such as OMAP5,
DRA74x and DRA72x.This now allows reuse by voltage domain devices which may share the same
voltage domain by allowing the regulator framework to maintain per
consumer usage information.Signed-off-by: Nishanth Menon
Signed-off-by: Dave Gerlach
21 Jul, 2015
1 commit
-
The OMAP IOMMU bindings is updated to reflect the required #iommu-cells
property.Signed-off-by: Suman Anna
[s-anna@ti.com: cherry-pick linux-omap patchwork id '6831121']
15 Jul, 2015
1 commit
-
Allow loading of a binary containing i2c scaling sequences to be
provided to the wkup_m3 firmware in order to properly scale voltage
rails on the PMIC during low power modes like DeepSleep0. Proper binary
format is determined by the FW in use.Code expects firmware to have 0x0C57 present as the first two bytes
followed by one byte defining offset to sleep sequence followed by one
byte defining offset to wake sequence and then lastly both sequences.
Each sequence is a series of I2C transfers in the form:u8 length | u8 chip address | u8 byte0/reg address | u8 byte1 | u8 byteN
..The length indicates the number of bytes to transfer, including the
register address. The length of each transfer is limited by the I2C
buffer size of 32 bytes.Based on previous work by Russ Dill.
Signed-off-by: Dave Gerlach
09 Jul, 2015
8 commits
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AM43xx support isolation of the IOs so that control is taken
from the peripheral they are connected to and overridden by values
present in the CTRL_CONF_* registers for the pad in the control module.The actual toggling happens from the wkup_m3, so use a DT property from
thea wkup_m3_ipc node to allow the PM code to communicate the necessity
for placing the IOs into isolation to the firmware.Signed-off-by: Dave Gerlach
-
Some boards (currently AM335x EVM-SK) provides s/w control via
GPIO to toggle VTT regulator to reduce power consumption in low
power state.The VTT regulator should be disabled after enabling self-refresh on
suspend, and should be enabled before disabling self-refresh on resume.
This is to allow proper self-refresh entry/exit commands to be
transmitted to the memory.Add support for toggling VTT regulator using DT properties.
Actual toggling happens in CM3 Firmware. The enable option & the GPIO
pin used is collected in A8 Core and then sent to CM3 using IPC
registers.Note:
Here it is assumed that VTT Toggle will be done using a pin on GPIO-0
Instance. The reason is GPIO-0 is in wakeup domain.Signed-off-by: Dave Gerlach
-
Introduce a dt property, ti,no-idle, that prevents an IP to idle at any
point. This is to handle Errata i877, which tells that GMAC clocks
cannot be disabled.Acked-by: Roger Quadros
Tested-by: Mugunthan V N
Signed-off-by: Lokesh Vutla
Signed-off-by: Sekhar Nori
Signed-off-by: Dave Gerlach -
Add the device tree bindings document for the TI Wakeup M3 IPC
device on AM33xx and AM43xx SoCs. These devices are used by the
TI wkup_m3_ipc driver, and contain the registers upon which the
IPC protocol to communicate with the Wakeup M3 processor is
implemented.Signed-off-by: Dave Gerlach
Signed-off-by: Suman Anna -
Add the device tree bindings document for ti,emif-am3352 and
ti,emif-am4372 which are used by the ti-emif-sram driver to
provide low-level PM functionality.Signed-off-by: Dave Gerlach
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Add node for TI AM4372 EMIF.
Signed-off-by: Dave Gerlach
-
Allow option for mapping SRAM as executable. This is useful for
platforms using the sram driver that need to run PM code from sram
like several ARM platforms.Signed-off-by: Russ Dill
Signed-off-by: Dave Gerlach -
The mailbox framework controls the transmission queue and requires
either its controller implementations or clients to run the state
machine for the Tx queue. The OMAP mailbox controller uses a Tx-ready
interrupt as the equivalent of a Tx-done interrupt to run this Tx
queue state-machine.The WkupM3 processor on AM33xx and AM43xx SoCs is used to offload
certain PM tasks, like doing the necessary operations for Device
PM suspend/resume or for entering lower c-states during cpuidle.The CPUIdle on AM33xx requires the messages to be sent without
having to trigger the Tx-ready interrupts, as the interrupt
would immediately terminate the CPUIdle operation. Support for
this has been added by introducing a DT quirk, "ti,mbox-send-noirq"
and using it to modify the normal OMAP mailbox controller behavior
on the sub-mailboxes used to communicate with the WkupM3 remote
processor. This also requires the wkup_m3_ipc driver to adjust
its mailbox usage logic to run the Tx state machine.NOTE:
- AM43xx does not communicate with WkupM3 for CPU Idle, so is
not affected by this behavior. But, it uses the same IPC driver
for PM suspend/resume functionality, so requires the quirk as
well, because of changes to the common wkup_m3_ipc driver.Signed-off-by: Dave Gerlach
[s-anna@ti.com: revise logic and update comments/patch description]
Signed-off-by: Suman Anna
