22 Sep, 2014
1 commit
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Move the Netlogic XLP device-trees to arch/mips/boot/dts/ and update the
Makefiles accordingly. A built-in device-tree is optional, so select
BUILTIN_DTB when it is requested.Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: James Hogan
Cc: Paul Burton
Cc: David Daney
Cc: John Crispin
Cc: Jayachandran C
Cc: Qais Yousef
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7560/
Signed-off-by: Ralf Baechle
10 Jun, 2014
1 commit
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Pull MIPS updates from Ralf Baechle:
- three fixes for 3.15 that didn't make it in time
- limited Octeon 3 support.
- paravirtualization support
- improvment to platform support for Netlogix SOCs.
- add support for powering down the Malta eval board in software
- add many instructions to the in-kernel microassembler.
- add support for the BPF JIT.
- minor cleanups of the BCM47xx code.
- large cleanup of math emu code resulting in significant code size
reduction, better readability of the code and more accurate
emulation.
- improvments to the MIPS CPS code.
- support C3 power status for the R4k count/compare clock device.
- improvments to the GIO support for older SGI workstations.
- increase number of supported CPUs to 256; this can be reached on
certain embedded multithreaded ccNUMA configurations.
- various small cleanups, updates and fixes* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (173 commits)
MIPS: IP22/IP28: Improve GIO support
MIPS: Octeon: Add twsi interrupt initialization for OCTEON 3XXX, 5XXX, 63XX
DEC: Document the R4k MB ASIC mini interrupt controller
DEC: Add self as the maintainer
MIPS: Add microMIPS MSA support.
MIPS: Replace calls to obsolete strict_strto call with kstrto* equivalents.
MIPS: Replace obsolete strict_strto call with kstrto
MIPS: BFP: Simplify code slightly.
MIPS: Call find_vma with the mmap_sem held
MIPS: Fix 'write_msa_##' inline macro.
MIPS: Fix MSA toolchain support detection.
mips: Update the email address of Geert Uytterhoeven
MIPS: Add minimal defconfig for mips_paravirt
MIPS: Enable build for new system 'paravirt'
MIPS: paravirt: Add pci controller for virtio
MIPS: Add code for new system 'paravirt'
MIPS: Add functions for hypervisor call
MIPS: OCTEON: Add OCTEON3 to __get_cpu_type
MIPS: Add function get_ebase_cpunum
MIPS: Add minimal support for OCTEON3 to c-r4k.c
...
30 May, 2014
13 commits
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The XLP9XX SoC has an on-chip SATA controller with two ports. Add
ahci-init-xlp2.c to initialize the controller, setup the glue logic
registers, fixup PCI quirks and setup interrupt ack logic.Signed-off-by: Ganesan Ramalingam
Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6913/
Signed-off-by: Ralf Baechle -
XLP3XX includes an on-chip SATA controller with 4 ports. The
controller needs glue logic initialization and PCI fixup before
it can be used with the standard AHCI driver.Signed-off-by: Ganesan Ramalingam
Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6872/
Signed-off-by: Ralf Baechle -
Add support for the XLP5XX processor which is an 8 core variant of the
XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX.Signed-off-by: Yonghong Song
Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6871/
Signed-off-by: Ralf Baechle -
Calculate XLP 9XX and 2XX core frequency from the per-core PLL. This
should give the correct value for all board configurations.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6870/
Signed-off-by: Ralf Baechle -
Update PIC frequency calculation for XLP9XX and 2XX processors using
the correct PLL registers. This should work for all possible board
configurations.Signed-off-by: Ganesan Ramalingam
Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6876/
Signed-off-by: Ralf Baechle -
Add the compatible property to the PIC entry. Also fix up the nodename
to use the correct address.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6869/
Signed-off-by: Ralf Baechle -
Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor
type.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6868/
Signed-off-by: Ralf Baechle -
Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND
and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add
device IDs for a few blocks.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6911/
Signed-off-by: Ralf Baechle -
The ELPA bit needs to be set in the PAGEGRAIN register to enable
access to >64GB physical address. Update reset.S to do this from
every hardware thread.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6866/
Signed-off-by: Ralf Baechle -
Update thread wakeup function to use scratch registers for saving SP and
RA. Move the register restore code needed for thread 0 to the calling
function. This reduces the size of code copied to the reset vector.Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6910/
Signed-off-by: Ralf Baechle -
Use standard function to print cpumask. Also fixup a typo in the same
file.Signed-off-by: Jayachandran C
Cc: g@linux-mips.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6909/
Signed-off-by: Ralf Baechle -
Warn and return if invalid IRQ is passed to nlm_set_pic_extra_ack.
Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6862/
Signed-off-by: Ralf Baechle -
This is needed for nlm_node_present(0) to work on uniprocessor compile.
Signed-off-by: Jayachandran C
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6861/
Signed-off-by: Ralf Baechle
27 May, 2014
1 commit
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Nothing was using the method and there isn't any need for this hook. This
leaves smp_cpus_done() empty for the moment.As suggested by Paul Bolle .
Signed-off-by: Ralf Baechle
30 Apr, 2014
2 commits
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Unify the various architectures __dtb_start and __dtb_end definitions
moving them into of_fdt.h.Signed-off-by: Rob Herring
Acked-by: Vineet Gupta
Acked-by: James Hogan
Tested-by: Michal Simek
Cc: Ralf Baechle
Cc: Jonas Bonn
Cc: Chris Zankel
Cc: Max Filippov
Cc: linux-metag@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux@lists.openrisc.net
Cc: linux-xtensa@linux-xtensa.org
Tested-by: Grant Likely
Tested-by: Stephen Chivers -
The existing code is buggy because built-in DTBs are in init memory.
It is also broken because the reserved bootmem was then freed after
unflattening, but the unflattened tree points to data in the flat tree.
Fix this by using the unflatten_and_copy_device_tree function.This removes all accesses to FDT header data by the arch code.
Signed-off-by: Rob Herring
Cc: Ralf Baechle
Cc: linux-mips@linux-mips.org
Tested-by: Grant Likely
31 Jan, 2014
1 commit
-
Pull MIPS updates from Ralf Baechle:
"The most notable new addition inside this pull request is the support
for MIPS's latest and greatest core called "inter/proAptiv". The
patch series describes this core as follows."The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit."The platform specific patches touch all 3 Broadcom families. It adds
support for the new Broadcom/Netlogix XLP9xx Soc, building a common
BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count
and full gpio button/led descriptions for BCM47xx.The rest of the series are cleanups and bug fixes that are MIPS
generic and consist largely of changes that Imgtec/MIPS had published
in their linux-mti-3.10.git stable tree. Random other cleanups and
patches preparing code to be merged in 3.15"* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
mips: select ARCH_MIGHT_HAVE_PC_SERIO
mips: delete non-required instances of include
MIPS: KVM: remove shadow_tlb code
MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI
mips/ide: flush dcache also if icache does not snoop dcache
MIPS: BCM47XX: fix position of cpu_wait disabling
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_
MIPS: introduce MIPS_L1_CACHE_SHIFT_
MIPS: ZBOOT: gather string functions into string.c
arch/mips/pci: don't check resource with devm_ioremap_resource
arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
bcma: gpio: don't cast u32 to unsigned long
ssb: gpio: add own IRQ domain
MIPS: BCM47XX: fix sparse warnings in board.c
MIPS: BCM47XX: add board detection for Linksys WRT54GS V1
MIPS: BCM47XX: fix detection for some boards
MIPS: BCM47XX: Enable buttons support on SSB
MIPS: BCM47XX: Convert WNDR4500 to new syntax
MIPS: BCM47XX: Use "timer" trigger for status LEDs
...
25 Jan, 2014
18 commits
-
None of these files are actually using any __init type directives
and hence don't need to include . Most are just a
left over from __devinit and __cpuinit removal, or simply due to
code getting copied from one driver to the next.Signed-off-by: Paul Gortmaker
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6320/ -
Move wakeup to after early console. This will allow us to display error
messages when cores are not woken up. Also reduce the wait time for core
to come up.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6303/ -
The early serial code is not needed because we already have early
printk support provided by common/earlycons.cThis change also fixes the following build error that occurs when
CONFIG_SERIAL_8250 is not configured for Netlogic XLR boards:arch/mips/built-in.o: In function `nlm_early_serial_setup':
setup.c:(.init.text+0x274): undefined reference to `early_serial_setup'
make: *** [vmlinux] Error 1Reported-by: Markos Chandras
Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6083/ -
Add a default device tree fie for XLP9XX boards, and add code to use
this device tree if no DTB is passed to the kernel.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6287/ -
Support for adding legacy IRQ domain for XLP9XX. The node id of the
PIC has to be calulated differently for XLP9XX.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6286/ -
XLP9XX has a USB 3.0 controller on-chip with 2 xHCI ports. The USB
block is similar to the one on XLP2XX, so update usb-init-xlp2.c
to handle XLP9XX as well.Signed-off-by: Ganesan Ramalingam
Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6285/ -
Add PCI support for Netlogic XLP9XX. The PCI registers and
SoC bus numbers have changed in XLP9XX.Also skip a few (bus,dev,fn) combinations which have issues when
read.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6284/ -
XLP9XX has 20 cores per node, opposed to 8 on earlier XLP8XX.
Update code that calculates node id from cpu id to handle this.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6283/ -
Update bridge code. Add code to the XLP9XX registers for DRAM
size, limit and node when running on XLPXXSigned-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6282/ -
Update IO offset of the early console UART.
Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6281/ -
Add the SYS block registers for XLP9XX, most of them have changed.
The wakeup sequence has been updated to set the coherent mode from
the main thread rather than the woken up thread.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6280/ -
Functions for the XLP9XX interrupt table entry format and other PIC
register changes.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6279/ -
Most IO block offsets have changed in XLP9XX. Update iomap.h to add the
new addresses of different SoC blocks like PIC, SYS, UART etc. that are
needed by the base code.On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus
corresponding to the node. Update iomap code to reflect this.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6277/ -
Adds processor ID of XLP 9XX to asm/cpu.h. Update netlogic/xlp-hal/xlp.h
to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6274/ -
Use the FUSE register to get the list of active cores in the CPU
instead of using the CPU reset register, this is the recommended
method.Also add code to mask the coremask with the default number of cores
for each processor series.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6275/ -
On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6276/ -
No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistentSigned-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6273/ -
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.The MSI-X chip definition uses the standard functions to enable
and disable interrupts.Signed-off-by: Jayachandran C
Signed-off-by: John Crispin
Patchwork: http://patchwork.linux-mips.org/patch/6270/
26 Nov, 2013
1 commit
-
Now that we have a CONFIG_PANIC_TIMEOUT=x setting, remove the
mips settings. The default is 0, which means don't reboot on
panic.Signed-off-by: Ralf Baechle
Acked-by: Shinya Kuribayashi
Signed-off-by: Jason Baron
Cc: benh@kernel.crashing.org
Cc: paulus@samba.org
Cc: mpe@ellerman.id.au
Cc: felipe.contreras@gmail.com
Cc: linux-mips@linux-mips.org
Cc: Linus Torvalds
Cc: Andrew Morton
Cc: Peter Zijlstra
Cc: Thomas Gleixner
Link: http://lkml.kernel.org/r/d19dc75fca343ec5d9ada75a1400f57330021976.1385418410.git.jbaron@akamai.com
Signed-off-by: Ingo Molnar
12 Nov, 2013
1 commit
-
Pull devicetree updates from Rob Herring:
"DeviceTree updates for 3.13. This is a bit larger pull request than
usual for this cycle with lots of clean-up.- Cross arch clean-up and consolidation of early DT scanning code.
- Clean-up and removal of arch prom.h headers. Makes arch specific
prom.h optional on all but Sparc.
- Addition of interrupts-extended property for devices connected to
multiple interrupt controllers.
- Refactoring of DT interrupt parsing code in preparation for
deferred probe of interrupts.
- ARM cpu and cpu topology bindings documentation.
- Various DT vendor binding documentation updates"* tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (82 commits)
powerpc: add missing explicit OF includes for ppc
dt/irq: add empty of_irq_count for !OF_IRQ
dt: disable self-tests for !OF_IRQ
of: irq: Fix interrupt-map entry matching
MIPS: Netlogic: replace early_init_devtree() call
of: Add Panasonic Corporation vendor prefix
of: Add Chunghwa Picture Tubes Ltd. vendor prefix
of: Add AU Optronics Corporation vendor prefix
of/irq: Fix potential buffer overflow
of/irq: Fix bug in interrupt parsing refactor.
of: set dma_mask to point to coherent_dma_mask
of: add vendor prefix for PHYTEC Messtechnik GmbH
DT: sort vendor-prefixes.txt
of: Add vendor prefix for Cadence
of: Add empty for_each_available_child_of_node() macro definition
arm/versatile: Fix versatile irq specifications.
of/irq: create interrupts-extended property
microblaze/pci: Drop PowerPC-ism from irq parsing
of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.
of/irq: Use irq_of_parse_and_map()
...
07 Nov, 2013
1 commit
-
The early_init_devtree() API was removed in linux-next for 3.13 with
commit "mips: use early_init_dt_scan". This causes Netlogic XLP compile
to fail:arch/mips/netlogic/xlp/setup.c:101: undefined reference to `early_init_devtree'
Add xlp_early_init_devtree() which uses the __dt_setup_arch() to
handle early device tree related initialization to fix this.Signed-off-by: Jayachandran C
Signed-off-by: Rob Herring