23 May, 2014

4 commits

• 48b6bce35   pinctrl: berlin: add the BG2CD pinctrl driver ... Browse Code »

  Add the pin-controller driver for the Berlin BG2Q SoC, with definition
  of its groups and functions. Pin control registers are part of chip/
  system control registers, which will be represented by a single node.
  Until a proper driver for the chip/system control is available,
  register the corresponding regmap in pinctrl driver probe.

  Signed-off-by: Antoine Tenart
  Acked-by: Sebastian Hesselbarth
  Signed-off-by: Linus Walleij

  Antoine Tenart

  2014-05-23 06:06:38 +0800  
• b016d1bd0   pinctrl: berlin: add the BG2 pinctrl driver ... Browse Code »

  Add the pin-controller driver for the Berlin BG2 SoC, with definition
  of its groups and functions. Pin control registers are part of chip/
  system control registers, which will be represented by a single node.
  Until a proper driver for the chip/system control is available,
  register the corresponding regmap in pinctrl driver probe.

  Signed-off-by: Antoine Tenart
  Acked-by: Sebastian Hesselbarth
  Signed-off-by: Linus Walleij

  Antoine Tenart

  2014-05-23 06:06:04 +0800  
• 626eea870   pinctrl: berlin: add the BG2Q pinctrl driver ... Browse Code »

  Add the pin-controller driver for the Berlin BG2Q SoC, with definition
  of its groups and functions. Pin control registers are part of chip/
  system control registers, which will be represented by a single node.
  Until a proper driver for the chip/system control is available,
  register the corresponding regmap in pinctrl driver probe.

  Signed-off-by: Antoine Tenart
  Acked-by: Sebastian Hesselbarth
  Signed-off-by: Linus Walleij

  Antoine Tenart

  2014-05-23 06:05:30 +0800  
• 3de68d331   pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs ... Browse Code »

  13

  The Marvell Berlin boards have a group based pinmuxing mechanism. This
  adds the core driver support. We actually do not need any information
  about the pins here and only have the definition of the groups.

  Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
  BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
  to mode 0:

  Group Modes Offset Base Offset LSB Bit Width
  GSM12 3 sm_base 0x40 0x10 0x2

  Ball Group Mode 0 Mode 1 Mode 2
  BK4 GSM12 UART0_RX IrDA0_RX GPIO9
  BH6 GSM12 UART0_TX IrDA0_TX GPIO10

  So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
  to set (sm_base + 0x40 + 0x10) &= ff3fffff.

  As pin control registers are part of either chip control or system
  control registers, that deal with a bunch of other functions we rely
  on a regmap instead of exclusively remapping any resources.

  Signed-off-by: Antoine Tenart
  Acked-by: Sebastian Hesselbarth
  Signed-off-by: Linus Walleij

  Antoine Tenart

  2014-05-23 06:05:00 +0800