15 Jul, 2008

1 commit


10 Jul, 2008

5 commits


21 Apr, 2008

3 commits


23 Feb, 2008

1 commit


18 Feb, 2008

1 commit

  • This patch fixes the following build error caused by commit
    3631c650c495d61b1dabf32eb26b46873636e918:

    ...
    LD .tmp_vmlinux1
    crypto/built-in.o: In function `skcipher_null_crypt':
    crypto_null.c:(.text+0x3d14): undefined reference to `blkcipher_walk_virt'
    crypto_null.c:(.text+0x3d14): relocation truncated to fit: R_MIPS_26 against `blkcipher_walk_virt'
    crypto/built-in.o: In function `$L32':
    crypto_null.c:(.text+0x3d54): undefined reference to `blkcipher_walk_done'
    crypto_null.c:(.text+0x3d54): relocation truncated to fit: R_MIPS_26 against `blkcipher_walk_done'
    crypto/built-in.o:(.data+0x2e8): undefined reference to `crypto_blkcipher_type'
    make[1]: *** [.tmp_vmlinux1] Error 1

    Signed-off-by: Adrian Bunk
    Signed-off-by: Herbert Xu

    Adrian Bunk
     

15 Feb, 2008

1 commit


11 Jan, 2008

17 commits

  • Signed-off-by: Tan Swee Heng
    Signed-off-by: Herbert Xu

    Tan Swee Heng
     
  • ERROR: "crypto_aead_setauthsize" [crypto/tcrypt.ko] undefined!
    ERROR: "crypto_alloc_aead" [crypto/tcrypt.ko] undefined!

    Signed-off-by: Sebastian Siewior
    Signed-off-by: Herbert Xu

    Sebastian Siewior
     
  • This is the x86-64 version of the Salsa20 stream cipher algorithm. The
    original assembly code came from
    . It has been
    reformatted for clarity.

    Signed-off-by: Tan Swee Heng
    Signed-off-by: Herbert Xu

    Tan Swee Heng
     
  • This patch contains the salsa20-i586 implementation. The original
    assembly code came from
    . I have reformatted
    it (added indents) so that it matches the other algorithms in
    arch/x86/crypto.

    Signed-off-by: Tan Swee Heng
    Signed-off-by: Herbert Xu

    Tan Swee Heng
     
  • Now that seqiv supports AEAD algorithms it needs to select the AEAD option.

    Thanks to Erez Zadok for pointing out the problem.

    Signed-off-by: Herbert Xu

    Herbert Xu
     
  • This patch adds Counter with CBC-MAC (CCM) support.
    RFC 3610 and NIST Special Publication 800-38C were referenced.

    Signed-off-by: Joy Latten
    Signed-off-by: Herbert Xu

    Joy Latten
     
  • This generator generates an IV based on a sequence number by xoring it
    with a salt. This algorithm is mainly useful for CTR and similar modes.

    This patch also sets it as the default IV generator for ctr.

    Signed-off-by: Herbert Xu

    Herbert Xu
     
  • With the impending addition of the givcipher type, both blkcipher and
    ablkcipher algorithms will use it to create givcipher objects. As such
    it no longer makes sense to split the system between ablkcipher and
    blkcipher. In particular, both ablkcipher.c and blkcipher.c would need
    to use the givcipher type which has to reside in ablkcipher.c since it
    shares much code with it.

    This patch merges the two Kconfig options as well as the modules into one.

    Signed-off-by: Herbert Xu

    Herbert Xu
     
  • i get here:

    ----
    LD vmlinux
    SYSMAP System.map
    SYSMAP .tmp_System.map
    Building modules, stage 2.
    MODPOST 226 modules
    ERROR: "crypto_hash_type" [crypto/authenc.ko] undefined!
    make[1]: *** [__modpost] Error 1
    make: *** [modules] Error 2
    ---

    which fails because crypto_hash_type is declared in crypto/hash.c. You might wanna
    fix it like so:

    Signed-off-by: Borislav Petkov
    Signed-off-by: Herbert Xu

    Borislav Petkov
     
  • Add LZO compression algorithm support

    Signed-off-by: Zoltan Sogor
    Signed-off-by: Herbert Xu

    Zoltan Sogor
     
  • Add GCM/GMAC support to cryptoapi.

    GCM (Galois/Counter Mode) is an AEAD mode of operations for any block cipher
    with a block size of 16. The typical example is AES-GCM.

    Signed-off-by: Mikko Herranen
    Reviewed-by: Mika Kukkonen
    Signed-off-by: Herbert Xu

    Mikko Herranen
     
  • This patch implements the Salsa20 stream cipher using the blkcipher interface.

    The core cipher code comes from Daniel Bernstein's submission to eSTREAM:
    http://www.ecrypt.eu.org/stream/svn/viewcvs.cgi/ecrypt/trunk/submissions/salsa20/full/ref/

    The test vectors comes from:
    http://www.ecrypt.eu.org/stream/svn/viewcvs.cgi/ecrypt/trunk/submissions/salsa20/full/

    It has been tested successfully with "modprobe tcrypt mode=34" on an
    UML instance.

    Signed-off-by: Tan Swee Heng
    Signed-off-by: Herbert Xu

    Tan Swee Heng
     
  • Resubmitting this patch which extends sha256_generic.c to support SHA-224 as
    described in FIPS 180-2 and RFC 3874. HMAC-SHA-224 as described in RFC4231
    is then supported through the hmac interface.

    Patch includes test vectors for SHA-224 and HMAC-SHA-224.

    SHA-224 chould be chosen as a hash algorithm when 112 bits of security
    strength is required.

    Patch generated against the 2.6.24-rc1 kernel and tested against
    2.6.24-rc1-git14 which includes fix for scatter gather implementation for HMAC.

    Signed-off-by: Jonathan Lynch
    Signed-off-by: Herbert Xu

    Jonathan Lynch
     
  • The setkey() function can be shared with the generic algorithm.

    Signed-off-by: Sebastian Siewior
    Signed-off-by: Herbert Xu

    Sebastian Siewior
     
  • NO other block mode is M by default.

    Signed-off-by: Sebastian Siewior
    Signed-off-by: Herbert Xu

    Sebastian Siewior
     
  • The setkey() function can be shared with the generic algorithm.

    Signed-off-by: Sebastian Siewior
    Signed-off-by: Herbert Xu

    Sebastian Siewior
     
  • This patch implements CTR mode for IPsec.
    It is based off of RFC 3686.

    Please note:
    1. CTR turns a block cipher into a stream cipher.
    Encryption is done in blocks, however the last block
    may be a partial block.

    A "counter block" is encrypted, creating a keystream
    that is xor'ed with the plaintext. The counter portion
    of the counter block is incremented after each block
    of plaintext is encrypted.
    Decryption is performed in same manner.

    2. The CTR counterblock is composed of,
    nonce + IV + counter

    The size of the counterblock is equivalent to the
    blocksize of the cipher.
    sizeof(nonce) + sizeof(IV) + sizeof(counter) = blocksize

    The CTR template requires the name of the cipher
    algorithm, the sizeof the nonce, and the sizeof the iv.
    ctr(cipher,sizeof_nonce,sizeof_iv)

    So for example,
    ctr(aes,4,8)
    specifies the counterblock will be composed of 4 bytes
    from a nonce, 8 bytes from the iv, and 4 bytes for counter
    since aes has a blocksize of 16 bytes.

    3. The counter portion of the counter block is stored
    in big endian for conformance to rfc 3686.

    Signed-off-by: Joy Latten
    Signed-off-by: Herbert Xu

    Joy Latten
     

11 Oct, 2007

5 commits

  • XTS currently considered to be the successor of the LRW mode by the IEEE1619
    workgroup. LRW was discarded, because it was not secure if the encyption key
    itself is encrypted with LRW.

    XTS does not have this problem. The implementation is pretty straightforward,
    a new function was added to gf128mul to handle GF(128) elements in ble format.
    Four testvectors from the specification
    http://grouper.ieee.org/groups/1619/email/pdf00086.pdf
    were added, and they verify on my system.

    Signed-off-by: Rik Snel
    Signed-off-by: Herbert Xu

    Rik Snel
     
  • This patch adds the authenc algorithm which constructs an AEAD algorithm
    from an asynchronous block cipher and a hash. The construction is done
    by concatenating the encrypted result from the cipher with the output
    from the hash, as is used by the IPsec ESP protocol.

    The authenc algorithm exists as a template with four parameters:

    authenc(auth, authsize, enc, enckeylen).

    The authentication algorithm, the authentication size (i.e., truncating
    the output of the authentication algorithm), the encryption algorithm,
    and the encryption key length. Both the size field and the key length
    field are in bytes. For example, AES-128 with SHA1-HMAC would be
    represented by

    authenc(hmac(sha1), 12, cbc(aes), 16)

    The key for the authenc algorithm is the concatenation of the keys for
    the authentication algorithm with the encryption algorithm. For the
    above example, if a key of length 36 bytes is given, then hmac(sha1)
    would receive the first 20 bytes while the last 16 would be given to
    cbc(aes).

    Signed-off-by: Herbert Xu

    Herbert Xu
     
  • This patch adds crypto_aead which is the interface for AEAD
    (Authenticated Encryption with Associated Data) algorithms.

    AEAD algorithms perform authentication and encryption in one
    step. Traditionally users (such as IPsec) would use two
    different crypto algorithms to perform these. With AEAD
    this comes down to one algorithm and one operation.

    Of course if traditional algorithms were used we'd still
    be doing two operations underneath. However, real AEAD
    algorithms may allow the underlying operations to be
    optimised as well.

    Signed-off-by: Herbert Xu

    Herbert Xu
     
  • This patch adds support for the SEED cipher (RFC4269).

    This patch have been used in few VPN appliance vendors in Korea for
    several years. And it was verified by KISA, who developed the
    algorithm itself.

    As its importance in Korean banking industry, it would be great
    if linux incorporates the support.

    Signed-off-by: Hye-Shik Chang
    Signed-off-by: Herbert Xu

    Hye-Shik Chang
     
  • Other options requiring specific block cipher algorithms already have
    the appropriate select's.

    Signed-off-by: Adrian Bunk
    Signed-off-by: Herbert Xu

    Adrian Bunk
     

15 Jul, 2007

1 commit


13 Jul, 2007

2 commits

  • The async_tx api provides methods for describing a chain of asynchronous
    bulk memory transfers/transforms with support for inter-transactional
    dependencies. It is implemented as a dmaengine client that smooths over
    the details of different hardware offload engine implementations. Code
    that is written to the api can optimize for asynchronous operation and the
    api will fit the chain of operations to the available offload resources.

    I imagine that any piece of ADMA hardware would register with the
    'async_*' subsystem, and a call to async_X would be routed as
    appropriate, or be run in-line. - Neil Brown

    async_tx exploits the capabilities of struct dma_async_tx_descriptor to
    provide an api of the following general format:

    struct dma_async_tx_descriptor *
    async_(..., struct dma_async_tx_descriptor *depend_tx,
    dma_async_tx_callback cb_fn, void *cb_param)
    {
    struct dma_chan *chan = async_tx_find_channel(depend_tx, );
    struct dma_device *device = chan ? chan->device : NULL;
    int int_en = cb_fn ? 1 : 0;
    struct dma_async_tx_descriptor *tx = device ?
    device->device_prep_dma_(chan, len, int_en) : NULL;

    if (tx) { /* run asynchronously */
    ...
    tx->tx_set_dest(addr, tx, index);
    ...
    tx->tx_set_src(addr, tx, index);
    ...
    async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
    } else { /* run synchronously */
    ...

    ...
    async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
    }

    return tx;
    }

    async_tx_find_channel() returns a capable channel from its pool. The
    channel pool is organized as a per-cpu array of channel pointers. The
    async_tx_rebalance() routine is tasked with managing these arrays. In the
    uniprocessor case async_tx_rebalance() tries to spread responsibility
    evenly over channels of similar capabilities. For example if there are two
    copy+xor channels, one will handle copy operations and the other will
    handle xor. In the SMP case async_tx_rebalance() attempts to spread the
    operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
    channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
    dependency is specified async_tx_find_channel defaults to keeping the
    operation on the same channel. A xor->copy->xor chain will stay on one
    channel if it supports both operation types, otherwise the transaction will
    transition between a copy and a xor resource.

    Currently the raid5 implementation in the MD raid456 driver has been
    converted to the async_tx api. A driver for the offload engines on the
    Intel Xscale series of I/O processors, iop-adma, is provided in a later
    commit. With the iop-adma driver and async_tx, raid456 is able to offload
    copy, xor, and xor-zero-sum operations to hardware engines.

    On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
    improvement) and sequential reads to a degraded array (40 - 55%
    improvement). For the other cases performance was roughly equal, +/- a few
    percentage points. On a x86-smp platform the performance of the async_tx
    implementation (in synchronous mode) was also +/- a few percentage points
    of the original implementation. According to 'top' on iop342 CPU
    utilization drops from ~50% to ~15% during a 'resync' while the speed
    according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.

    The tiobench command line used for testing was: tiobench --size 2048
    --block 4096 --block 131072 --dir /mnt/raid --numruns 5
    * iop342 had 1GB of memory available

    Details:
    * if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
    async_tx_find_channel a static inline routine that always returns NULL
    * when a callback is specified for a given transaction an interrupt will
    fire at operation completion time and the callback will occur in a
    tasklet. if the the channel does not support interrupts then a live
    polling wait will be performed
    * the api is written as a dmaengine client that requests all available
    channels
    * In support of dependencies the api implicitly schedules channel-switch
    interrupts. The interrupt triggers the cleanup tasklet which causes
    pending operations to be scheduled on the next channel
    * Xor engines treat an xor destination address differently than a software
    xor routine. To the software routine the destination address is an implied
    source, whereas engines treat it as a write-only destination. This patch
    modifies the xor_blocks routine to take a an explicit destination address
    to mirror the hardware.

    Changelog:
    * fixed a leftover debug print
    * don't allow callbacks in async_interrupt_cond
    * fixed xor_block changes
    * fixed usage of ASYNC_TX_XOR_DROP_DEST
    * drop dma mapping methods, suggested by Chris Leech
    * printk warning fixups from Andrew Morton
    * don't use inline in C files, Adrian Bunk
    * select the API when MD is enabled
    * BUG_ON xor source counts
    Signed-off-by: Dan Williams
    Acked-By: NeilBrown

    Dan Williams
     
  • The async_tx api tries to use a dma engine for an operation, but will fall
    back to an optimized software routine otherwise. Xor support is
    implemented using the raid5 xor routines. For organizational purposes this
    routine is moved to a common area.

    The following fixes are also made:
    * rename xor_block => xor_blocks, suggested by Adrian Bunk
    * ensure that xor.o initializes before md.o in the built-in case
    * checkpatch.pl fixes
    * mark calibrate_xor_blocks __init, Adrian Bunk

    Cc: Adrian Bunk
    Cc: NeilBrown
    Cc: Herbert Xu
    Signed-off-by: Dan Williams

    Dan Williams
     

11 Jul, 2007

1 commit


09 May, 2007

1 commit


02 May, 2007

1 commit