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Commit 4f60dab113230943fb1bc7969053d9a1b6578339

Authored by Yaniv Rosner
Committed by David S. Miller
1 parent b5bbf0080e
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

bnx2x: Add support for BCM84823 

Add support for new phy type BCM84823 (Dual copper-port phy)

Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

Showing 2 changed files with 42 additions and 3 deletions Side-by-side Diff

drivers/net/bnx2x_hsi.h
Diff comments   View file @ 4f60dab
... ... @@ -264,6 +264,7 @@
264 264 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
265 265 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
266 266 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
  267 +#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
267 268 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
268 269 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
269 270  
drivers/net/bnx2x_link.c
Diff comments   View file @ 4f60dab
... ... @@ -2200,6 +2200,8 @@
2200 2200 MDIO_PMA_REG_CTRL,
2201 2201 1<<15);
2202 2202 break;
  2203 + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
  2204 + break;
2203 2205 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2204 2206 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2205 2207 break;
... ... @@ -4373,6 +4375,7 @@
4373 4375 break;
4374 4376 }
4375 4377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
  4378 + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
4376 4379 /* This phy uses the NIG latch mechanism since link
4377 4380 indication arrives through its LED4 and not via
4378 4381 its LASI signal, so we get steady signal
... ... @@ -4380,6 +4383,12 @@
4380 4383 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4381 4384 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4382 4385  
  4386 + bnx2x_cl45_write(bp, params->port,
  4387 + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
  4388 + ext_phy_addr,
  4389 + MDIO_PMA_DEVAD,
  4390 + MDIO_PMA_REG_CTRL, 0x0000);
  4391 +
4383 4392 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4384 4393 if (params->req_line_speed == SPEED_AUTO_NEG) {
4385 4394  
... ... @@ -5230,6 +5239,7 @@
5230 5239 }
5231 5240 break;
5232 5241 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
  5242 + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5233 5243 /* Check 10G-BaseT link status */
5234 5244 /* Check PMD signal ok */
5235 5245 bnx2x_cl45_read(bp, params->port, ext_phy_type,
... ... @@ -5445,8 +5455,10 @@
5445 5455 (NIG_STATUS_XGXS0_LINK10G |
5446 5456 NIG_STATUS_XGXS0_LINK_STATUS |
5447 5457 NIG_STATUS_SERDES0_LINK_STATUS));
5448   - if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5449   - == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
  5458 + if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config)
  5459 + == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) ||
  5460 + (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
  5461 + == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823)) {
5450 5462 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5451 5463 }
5452 5464 if (vars->phy_link_up) {
... ... @@ -5559,6 +5571,7 @@
5559 5571 status = bnx2x_format_ver(spirom_ver, version, len);
5560 5572 break;
5561 5573 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
  5574 + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
5562 5575 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5563 5576 (spirom_ver & 0x7F);
5564 5577 status = bnx2x_format_ver(spirom_ver, version, len);
... ... @@ -6250,6 +6263,22 @@
6250 6263 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6251 6264 break;
6252 6265 }
  6266 + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
  6267 + {
  6268 + u8 ext_phy_addr =
  6269 + XGXS_EXT_PHY_ADDR(params->ext_phy_config);
  6270 + bnx2x_cl45_write(bp, port,
  6271 + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
  6272 + ext_phy_addr,
  6273 + MDIO_AN_DEVAD,
  6274 + MDIO_AN_REG_CTRL, 0x0000);
  6275 + bnx2x_cl45_write(bp, port,
  6276 + PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
  6277 + ext_phy_addr,
  6278 + MDIO_PMA_DEVAD,
  6279 + MDIO_PMA_REG_CTRL, 1);
  6280 + break;
  6281 + }
6253 6282 default:
6254 6283 /* HW reset */
6255 6284 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
... ... @@ -6661,6 +6690,13 @@
6661 6690 return 0;
6662 6691 }
6663 6692  
  6693 +
  6694 +static u8 bnx2x_84823_common_init_phy(struct bnx2x *bp, u32 shmem_base)
  6695 +{
  6696 + /* HW reset */
  6697 + bnx2x_ext_phy_hw_reset(bp, 1);
  6698 + return 0;
  6699 +}
6664 6700 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6665 6701 {
6666 6702 u8 rc = 0;
... ... @@ -6690,7 +6726,9 @@
6690 6726 /* GPIO1 affects both ports, so there's need to pull
6691 6727 it for single port alone */
6692 6728 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6693   -
  6729 + break;
  6730 + case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
  6731 + rc = bnx2x_84823_common_init_phy(bp, shmem_base);
6694 6732 break;
6695 6733 default:
6696 6734 DP(NETIF_MSG_LINK,