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Commit 54407f190c8d542572a9547ba5460d811810b6e4

Authored by Sergei Shtylyov
Committed by Simon Horman
1 parent 7173e59e6b
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

phy-rcar-usb: add R8A7778 support 

The driver currently only supports R8A7779 SoC. Compared to it, R8A7778 USB-PHY
has extra register range containing two high-speed signal quality characteristic
control registers which should be set up  during USB-PHY  startup depending on
whether a ferrite bead is in use or not.  So, we now handle an optional second
memory range in the driver's probe method, add the 'ferrite_bead' field to the
driver's platform data, and add an extra (optional) step to the USB-PHY startup
routine which sets up the extended registers.

Also mark in the driver's Kconfig section  that R8A7778 is now supported and
generally clarify that section, uppercasing the word "phy" and also changing
the module name that got lost in the big driver rename, while at it...

The patch has been tested on the Marzen and BOCK-W boards.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Showing 3 changed files with 39 additions and 12 deletions Inline Diff

drivers/usb/phy/Kconfig
Diff comments   View file @ 54407f1
1 # 1 #
2 # Physical Layer USB driver configuration 2 # Physical Layer USB driver configuration
3 # 3 #
4 menuconfig USB_PHY 4 menuconfig USB_PHY
5 bool "USB Physical Layer drivers" 5 bool "USB Physical Layer drivers"
6 help 6 help
7 USB controllers (those which are host, device or DRD) need a 7 USB controllers (those which are host, device or DRD) need a
8 device to handle the physical layer signalling, commonly called 8 device to handle the physical layer signalling, commonly called
9 a PHY. 9 a PHY.
10 10
11 The following drivers add support for such PHY devices. 11 The following drivers add support for such PHY devices.
12 12
13 if USB_PHY 13 if USB_PHY
14 14
15 # 15 #
16 # USB Transceiver Drivers 16 # USB Transceiver Drivers
17 # 17 #
18 config AB8500_USB 18 config AB8500_USB
19 tristate "AB8500 USB Transceiver Driver" 19 tristate "AB8500 USB Transceiver Driver"
20 depends on AB8500_CORE 20 depends on AB8500_CORE
21 help 21 help
22 Enable this to support the USB OTG transceiver in AB8500 chip. 22 Enable this to support the USB OTG transceiver in AB8500 chip.
23 This transceiver supports high and full speed devices plus, 23 This transceiver supports high and full speed devices plus,
24 in host mode, low speed. 24 in host mode, low speed.
25 25
26 config FSL_USB2_OTG 26 config FSL_USB2_OTG
27 bool "Freescale USB OTG Transceiver Driver" 27 bool "Freescale USB OTG Transceiver Driver"
28 depends on USB_EHCI_FSL && USB_FSL_USB2 && USB_SUSPEND 28 depends on USB_EHCI_FSL && USB_FSL_USB2 && USB_SUSPEND
29 select USB_OTG 29 select USB_OTG
30 help 30 help
31 Enable this to support Freescale USB OTG transceiver. 31 Enable this to support Freescale USB OTG transceiver.
32 32
33 config ISP1301_OMAP 33 config ISP1301_OMAP
34 tristate "Philips ISP1301 with OMAP OTG" 34 tristate "Philips ISP1301 with OMAP OTG"
35 depends on I2C && ARCH_OMAP_OTG 35 depends on I2C && ARCH_OMAP_OTG
36 help 36 help
37 If you say yes here you get support for the Philips ISP1301 37 If you say yes here you get support for the Philips ISP1301
38 USB-On-The-Go transceiver working with the OMAP OTG controller. 38 USB-On-The-Go transceiver working with the OMAP OTG controller.
39 The ISP1301 is a full speed USB transceiver which is used in 39 The ISP1301 is a full speed USB transceiver which is used in
40 products including H2, H3, and H4 development boards for Texas 40 products including H2, H3, and H4 development boards for Texas
41 Instruments OMAP processors. 41 Instruments OMAP processors.
42 42
43 This driver can also be built as a module. If so, the module 43 This driver can also be built as a module. If so, the module
44 will be called isp1301_omap. 44 will be called isp1301_omap.
45 45
46 config MV_U3D_PHY 46 config MV_U3D_PHY
47 bool "Marvell USB 3.0 PHY controller Driver" 47 bool "Marvell USB 3.0 PHY controller Driver"
48 depends on CPU_MMP3 48 depends on CPU_MMP3
49 help 49 help
50 Enable this to support Marvell USB 3.0 phy controller for Marvell 50 Enable this to support Marvell USB 3.0 phy controller for Marvell
51 SoC. 51 SoC.
52 52
53 config NOP_USB_XCEIV 53 config NOP_USB_XCEIV
54 tristate "NOP USB Transceiver Driver" 54 tristate "NOP USB Transceiver Driver"
55 help 55 help
56 This driver is to be used by all the usb transceiver which are either 56 This driver is to be used by all the usb transceiver which are either
57 built-in with usb ip or which are autonomous and doesn't require any 57 built-in with usb ip or which are autonomous and doesn't require any
58 phy programming such as ISP1x04 etc. 58 phy programming such as ISP1x04 etc.
59 59
60 config OMAP_CONTROL_USB 60 config OMAP_CONTROL_USB
61 tristate "OMAP CONTROL USB Driver" 61 tristate "OMAP CONTROL USB Driver"
62 help 62 help
63 Enable this to add support for the USB part present in the control 63 Enable this to add support for the USB part present in the control
64 module. This driver has API to power on the USB2 PHY and to write to 64 module. This driver has API to power on the USB2 PHY and to write to
65 the mailbox. The mailbox is present only in omap4 and the register to 65 the mailbox. The mailbox is present only in omap4 and the register to
66 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an 66 power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
67 additional register to power on USB3 PHY. 67 additional register to power on USB3 PHY.
68 68
69 config OMAP_USB2 69 config OMAP_USB2
70 tristate "OMAP USB2 PHY Driver" 70 tristate "OMAP USB2 PHY Driver"
71 depends on ARCH_OMAP2PLUS 71 depends on ARCH_OMAP2PLUS
72 select OMAP_CONTROL_USB 72 select OMAP_CONTROL_USB
73 help 73 help
74 Enable this to support the transceiver that is part of SOC. This 74 Enable this to support the transceiver that is part of SOC. This
75 driver takes care of all the PHY functionality apart from comparator. 75 driver takes care of all the PHY functionality apart from comparator.
76 The USB OTG controller communicates with the comparator using this 76 The USB OTG controller communicates with the comparator using this
77 driver. 77 driver.
78 78
79 config OMAP_USB3 79 config OMAP_USB3
80 tristate "OMAP USB3 PHY Driver" 80 tristate "OMAP USB3 PHY Driver"
81 select OMAP_CONTROL_USB 81 select OMAP_CONTROL_USB
82 help 82 help
83 Enable this to support the USB3 PHY that is part of SOC. This 83 Enable this to support the USB3 PHY that is part of SOC. This
84 driver takes care of all the PHY functionality apart from comparator. 84 driver takes care of all the PHY functionality apart from comparator.
85 This driver interacts with the "OMAP Control USB Driver" to power 85 This driver interacts with the "OMAP Control USB Driver" to power
86 on/off the PHY. 86 on/off the PHY.
87 87
88 config SAMSUNG_USBPHY 88 config SAMSUNG_USBPHY
89 tristate "Samsung USB PHY Driver" 89 tristate "Samsung USB PHY Driver"
90 help 90 help
91 Enable this to support Samsung USB phy helper driver for Samsung SoCs. 91 Enable this to support Samsung USB phy helper driver for Samsung SoCs.
92 This driver provides common interface to interact, for Samsung USB 2.0 PHY 92 This driver provides common interface to interact, for Samsung USB 2.0 PHY
93 driver and later for Samsung USB 3.0 PHY driver. 93 driver and later for Samsung USB 3.0 PHY driver.
94 94
95 config SAMSUNG_USB2PHY 95 config SAMSUNG_USB2PHY
96 tristate "Samsung USB 2.0 PHY controller Driver" 96 tristate "Samsung USB 2.0 PHY controller Driver"
97 select SAMSUNG_USBPHY 97 select SAMSUNG_USBPHY
98 help 98 help
99 Enable this to support Samsung USB 2.0 (High Speed) PHY controller 99 Enable this to support Samsung USB 2.0 (High Speed) PHY controller
100 driver for Samsung SoCs. 100 driver for Samsung SoCs.
101 101
102 config SAMSUNG_USB3PHY 102 config SAMSUNG_USB3PHY
103 tristate "Samsung USB 3.0 PHY controller Driver" 103 tristate "Samsung USB 3.0 PHY controller Driver"
104 select SAMSUNG_USBPHY 104 select SAMSUNG_USBPHY
105 help 105 help
106 Enable this to support Samsung USB 3.0 (Super Speed) phy controller 106 Enable this to support Samsung USB 3.0 (Super Speed) phy controller
107 for samsung SoCs. 107 for samsung SoCs.
108 108
109 config TWL4030_USB 109 config TWL4030_USB
110 tristate "TWL4030 USB Transceiver Driver" 110 tristate "TWL4030 USB Transceiver Driver"
111 depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS 111 depends on TWL4030_CORE && REGULATOR_TWL4030 && USB_MUSB_OMAP2PLUS
112 help 112 help
113 Enable this to support the USB OTG transceiver on TWL4030 113 Enable this to support the USB OTG transceiver on TWL4030
114 family chips (including the TWL5030 and TPS659x0 devices). 114 family chips (including the TWL5030 and TPS659x0 devices).
115 This transceiver supports high and full speed devices plus, 115 This transceiver supports high and full speed devices plus,
116 in host mode, low speed. 116 in host mode, low speed.
117 117
118 config TWL6030_USB 118 config TWL6030_USB
119 tristate "TWL6030 USB Transceiver Driver" 119 tristate "TWL6030 USB Transceiver Driver"
120 depends on TWL4030_CORE && OMAP_USB2 && USB_MUSB_OMAP2PLUS 120 depends on TWL4030_CORE && OMAP_USB2 && USB_MUSB_OMAP2PLUS
121 help 121 help
122 Enable this to support the USB OTG transceiver on TWL6030 122 Enable this to support the USB OTG transceiver on TWL6030
123 family chips. This TWL6030 transceiver has the VBUS and ID GND 123 family chips. This TWL6030 transceiver has the VBUS and ID GND
124 and OTG SRP events capabilities. For all other transceiver functionality 124 and OTG SRP events capabilities. For all other transceiver functionality
125 UTMI PHY is embedded in OMAP4430. The internal PHY configurations APIs 125 UTMI PHY is embedded in OMAP4430. The internal PHY configurations APIs
126 are hooked to this driver through platform_data structure. 126 are hooked to this driver through platform_data structure.
127 The definition of internal PHY APIs are in the mach-omap2 layer. 127 The definition of internal PHY APIs are in the mach-omap2 layer.
128 128
129 config USB_GPIO_VBUS 129 config USB_GPIO_VBUS
130 tristate "GPIO based peripheral-only VBUS sensing 'transceiver'" 130 tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
131 depends on GPIOLIB 131 depends on GPIOLIB
132 help 132 help
133 Provides simple GPIO VBUS sensing for controllers with an 133 Provides simple GPIO VBUS sensing for controllers with an
134 internal transceiver via the usb_phy interface, and 134 internal transceiver via the usb_phy interface, and
135 optionally control of a D+ pullup GPIO as well as a VBUS 135 optionally control of a D+ pullup GPIO as well as a VBUS
136 current limit regulator. 136 current limit regulator.
137 137
138 config USB_ISP1301 138 config USB_ISP1301
139 tristate "NXP ISP1301 USB transceiver support" 139 tristate "NXP ISP1301 USB transceiver support"
140 depends on USB || USB_GADGET 140 depends on USB || USB_GADGET
141 depends on I2C 141 depends on I2C
142 select USB_OTG_UTILS 142 select USB_OTG_UTILS
143 help 143 help
144 Say Y here to add support for the NXP ISP1301 USB transceiver driver. 144 Say Y here to add support for the NXP ISP1301 USB transceiver driver.
145 This chip is typically used as USB transceiver for USB host, gadget 145 This chip is typically used as USB transceiver for USB host, gadget
146 and OTG drivers (to be selected separately). 146 and OTG drivers (to be selected separately).
147 147
148 To compile this driver as a module, choose M here: the 148 To compile this driver as a module, choose M here: the
149 module will be called isp1301. 149 module will be called isp1301.
150 150
151 config USB_MSM_OTG 151 config USB_MSM_OTG
152 tristate "OTG support for Qualcomm on-chip USB controller" 152 tristate "OTG support for Qualcomm on-chip USB controller"
153 depends on (USB || USB_GADGET) && ARCH_MSM 153 depends on (USB || USB_GADGET) && ARCH_MSM
154 help 154 help
155 Enable this to support the USB OTG transceiver on MSM chips. It 155 Enable this to support the USB OTG transceiver on MSM chips. It
156 handles PHY initialization, clock management, and workarounds 156 handles PHY initialization, clock management, and workarounds
157 required after resetting the hardware and power management. 157 required after resetting the hardware and power management.
158 This driver is required even for peripheral only or host only 158 This driver is required even for peripheral only or host only
159 mode configurations. 159 mode configurations.
160 This driver is not supported on boards like trout which 160 This driver is not supported on boards like trout which
161 has an external PHY. 161 has an external PHY.
162 162
163 config USB_MV_OTG 163 config USB_MV_OTG
164 tristate "Marvell USB OTG support" 164 tristate "Marvell USB OTG support"
165 depends on USB_EHCI_MV && USB_MV_UDC && USB_SUSPEND 165 depends on USB_EHCI_MV && USB_MV_UDC && USB_SUSPEND
166 select USB_OTG 166 select USB_OTG
167 help 167 help
168 Say Y here if you want to build Marvell USB OTG transciever 168 Say Y here if you want to build Marvell USB OTG transciever
169 driver in kernel (including PXA and MMP series). This driver 169 driver in kernel (including PXA and MMP series). This driver
170 implements role switch between EHCI host driver and gadget driver. 170 implements role switch between EHCI host driver and gadget driver.
171 171
172 To compile this driver as a module, choose M here. 172 To compile this driver as a module, choose M here.
173 173
174 config USB_MXS_PHY 174 config USB_MXS_PHY
175 tristate "Freescale MXS USB PHY support" 175 tristate "Freescale MXS USB PHY support"
176 depends on ARCH_MXC || ARCH_MXS 176 depends on ARCH_MXC || ARCH_MXS
177 select STMP_DEVICE 177 select STMP_DEVICE
178 help 178 help
179 Enable this to support the Freescale MXS USB PHY. 179 Enable this to support the Freescale MXS USB PHY.
180 180
181 MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x. 181 MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
182 182
183 config USB_RCAR_PHY 183 config USB_RCAR_PHY
184 tristate "Renesas R-Car USB phy support" 184 tristate "Renesas R-Car USB PHY support"
185 depends on USB || USB_GADGET 185 depends on USB || USB_GADGET
186 help 186 help
187 Say Y here to add support for the Renesas R-Car USB phy driver. 187 Say Y here to add support for the Renesas R-Car USB common PHY driver.
188 This chip is typically used as USB phy for USB host, gadget. 188 This chip is typically used as USB PHY for USB host, gadget.
189 This driver supports: R8A7779 189 This driver supports R8A7778 and R8A7779.
190 190
191 To compile this driver as a module, choose M here: the 191 To compile this driver as a module, choose M here: the
192 module will be called rcar-phy. 192 module will be called phy-rcar-usb.
193 193
194 config USB_ULPI 194 config USB_ULPI
195 bool "Generic ULPI Transceiver Driver" 195 bool "Generic ULPI Transceiver Driver"
196 depends on ARM 196 depends on ARM
197 help 197 help
198 Enable this to support ULPI connected USB OTG transceivers which 198 Enable this to support ULPI connected USB OTG transceivers which
199 are likely found on embedded boards. 199 are likely found on embedded boards.
200 200
201 config USB_ULPI_VIEWPORT 201 config USB_ULPI_VIEWPORT
202 bool 202 bool
203 depends on USB_ULPI 203 depends on USB_ULPI
204 help 204 help
205 Provides read/write operations to the ULPI phy register set for 205 Provides read/write operations to the ULPI phy register set for
206 controllers with a viewport register (e.g. Chipidea/ARC controllers). 206 controllers with a viewport register (e.g. Chipidea/ARC controllers).
207 207
208 endif # USB_PHY 208 endif # USB_PHY
209 209
drivers/usb/phy/phy-rcar-usb.c
Diff comments   View file @ 54407f1
1 /* 1 /*
2 * Renesas R-Car USB phy driver 2 * Renesas R-Car USB phy driver
3 * 3 *
4 * Copyright (C) 2012-2013 Renesas Solutions Corp. 4 * Copyright (C) 2012-2013 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13 #include <linux/delay.h> 13 #include <linux/delay.h>
14 #include <linux/io.h> 14 #include <linux/io.h>
15 #include <linux/usb/otg.h> 15 #include <linux/usb/otg.h>
16 #include <linux/platform_device.h> 16 #include <linux/platform_device.h>
17 #include <linux/spinlock.h> 17 #include <linux/spinlock.h>
18 #include <linux/module.h> 18 #include <linux/module.h>
19 #include <linux/platform_data/usb-rcar-phy.h> 19 #include <linux/platform_data/usb-rcar-phy.h>
20 20
21 /* REGS block */ 21 /* REGS block */
22 #define USBPCTRL0 0x00 22 #define USBPCTRL0 0x00
23 #define USBPCTRL1 0x04 23 #define USBPCTRL1 0x04
24 #define USBST 0x08 24 #define USBST 0x08
25 #define USBEH0 0x0C 25 #define USBEH0 0x0C
26 #define USBOH0 0x1C 26 #define USBOH0 0x1C
27 #define USBCTL0 0x58 27 #define USBCTL0 0x58
28 28
29 /* High-speed signal quality characteristic control registers (R8A7778 only) */
30 #define HSQCTL1 0x24
31 #define HSQCTL2 0x28
32
29 /* USBPCTRL0 */ 33 /* USBPCTRL0 */
30 #define OVC2 (1 << 10) /* Switches the OVC input pin for port 2: */ 34 #define OVC2 (1 << 10) /* (R8A7779 only) */
35 /* Switches the OVC input pin for port 2: */
31 /* 1: USB_OVC2, 0: OVC2 */ 36 /* 1: USB_OVC2, 0: OVC2 */
32 #define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */ 37 #define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */
33 /* 1: USB_OVC1, 0: OVC1/VBUS1 */ 38 /* 1: USB_OVC1, 0: OVC1/VBUS1 */
34 /* Function mode: set to 0 */ 39 /* Function mode: set to 0 */
35 #define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */ 40 #define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */
36 /* 1: USB_OVC0 pin, 0: OVC0 */ 41 /* 1: USB_OVC0 pin, 0: OVC0 */
37 #define OVC2_ACT (1 << 6) /* Host mode: OVC2 polarity: */ 42 #define OVC2_ACT (1 << 6) /* (R8A7779 only) */
43 /* Host mode: OVC2 polarity: */
38 /* 1: active-high, 0: active-low */ 44 /* 1: active-high, 0: active-low */
39 #define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */ 45 #define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */
40 /* 1: high, 0: low */ 46 /* 1: high, 0: low */
41 #define OVC0_ACT (1 << 3) /* Host mode: OVC0 polarity: */ 47 #define OVC0_ACT (1 << 3) /* Host mode: OVC0 polarity: */
42 /* 1: active-high, 0: active-low */ 48 /* 1: active-high, 0: active-low */
43 #define OVC1_ACT (1 << 1) /* Host mode: OVC1 polarity: */ 49 #define OVC1_ACT (1 << 1) /* Host mode: OVC1 polarity: */
44 /* 1: active-high, 0: active-low */ 50 /* 1: active-high, 0: active-low */
45 /* Function mode: be sure to set to 1 */ 51 /* Function mode: be sure to set to 1 */
46 #define PORT1 (1 << 0) /* Selects port 1 mode: */ 52 #define PORT1 (1 << 0) /* Selects port 1 mode: */
47 /* 1: function, 0: host */ 53 /* 1: function, 0: host */
48 /* USBPCTRL1 */ 54 /* USBPCTRL1 */
49 #define PHY_RST (1 << 2) 55 #define PHY_RST (1 << 2)
50 #define PLL_ENB (1 << 1) 56 #define PLL_ENB (1 << 1)
51 #define PHY_ENB (1 << 0) 57 #define PHY_ENB (1 << 0)
52 58
53 /* USBST */ 59 /* USBST */
54 #define ST_ACT (1 << 31) 60 #define ST_ACT (1 << 31)
55 #define ST_PLL (1 << 30) 61 #define ST_PLL (1 << 30)
56 62
57 struct rcar_usb_phy_priv { 63 struct rcar_usb_phy_priv {
58 struct usb_phy phy; 64 struct usb_phy phy;
59 spinlock_t lock; 65 spinlock_t lock;
60 66
61 void __iomem *reg0; 67 void __iomem *reg0;
68 void __iomem *reg1;
62 int counter; 69 int counter;
63 }; 70 };
64 71
65 #define usb_phy_to_priv(p) container_of(p, struct rcar_usb_phy_priv, phy) 72 #define usb_phy_to_priv(p) container_of(p, struct rcar_usb_phy_priv, phy)
66 73
67 74
68 /* 75 /*
69 * USB initial/install operation. 76 * USB initial/install operation.
70 * 77 *
71 * This function setup USB phy. 78 * This function setup USB phy.
72 * The used value and setting order came from 79 * The used value and setting order came from
73 * [USB :: Initial setting] on datasheet. 80 * [USB :: Initial setting] on datasheet.
74 */ 81 */
75 static int rcar_usb_phy_init(struct usb_phy *phy) 82 static int rcar_usb_phy_init(struct usb_phy *phy)
76 { 83 {
77 struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy); 84 struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy);
78 struct device *dev = phy->dev; 85 struct device *dev = phy->dev;
79 struct rcar_phy_platform_data *pdata = dev->platform_data; 86 struct rcar_phy_platform_data *pdata = dev->platform_data;
80 void __iomem *reg0 = priv->reg0; 87 void __iomem *reg0 = priv->reg0;
88 void __iomem *reg1 = priv->reg1;
81 static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT }; 89 static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT };
82 int i; 90 int i;
83 u32 val; 91 u32 val;
84 unsigned long flags; 92 unsigned long flags;
85 93
86 spin_lock_irqsave(&priv->lock, flags); 94 spin_lock_irqsave(&priv->lock, flags);
87 if (priv->counter++ == 0) { 95 if (priv->counter++ == 0) {
88 96
89 /* 97 /*
90 * USB phy start-up 98 * USB phy start-up
91 */ 99 */
92 100
93 /* (1) USB-PHY standby release */ 101 /* (1) USB-PHY standby release */
94 iowrite32(PHY_ENB, (reg0 + USBPCTRL1)); 102 iowrite32(PHY_ENB, (reg0 + USBPCTRL1));
95 103
96 /* (2) start USB-PHY internal PLL */ 104 /* (2) start USB-PHY internal PLL */
97 iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1)); 105 iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1));
98 106
99 /* (3) USB module status check */ 107 /* (3) set USB-PHY in accord with the conditions of usage */
108 if (reg1) {
109 u32 hsqctl1 = pdata->ferrite_bead ? 0x41 : 0;
110 u32 hsqctl2 = pdata->ferrite_bead ? 0x0d : 7;
111
112 iowrite32(hsqctl1, reg1 + HSQCTL1);
113 iowrite32(hsqctl2, reg1 + HSQCTL2);
114 }
115
116 /* (4) USB module status check */
100 for (i = 0; i < 1024; i++) { 117 for (i = 0; i < 1024; i++) {
101 udelay(10); 118 udelay(10);
102 val = ioread32(reg0 + USBST); 119 val = ioread32(reg0 + USBST);
103 if (val == (ST_ACT | ST_PLL)) 120 if (val == (ST_ACT | ST_PLL))
104 break; 121 break;
105 } 122 }
106 123
107 if (val != (ST_ACT | ST_PLL)) { 124 if (val != (ST_ACT | ST_PLL)) {
108 dev_err(dev, "USB phy not ready\n"); 125 dev_err(dev, "USB phy not ready\n");
109 goto phy_init_end; 126 goto phy_init_end;
110 } 127 }
111 128
112 /* (4) USB-PHY reset clear */ 129 /* (5) USB-PHY reset clear */
113 iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1)); 130 iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1));
114 131
115 /* Board specific port settings */ 132 /* Board specific port settings */
116 val = 0; 133 val = 0;
117 if (pdata->port1_func) 134 if (pdata->port1_func)
118 val |= PORT1; 135 val |= PORT1;
119 if (pdata->penc1) 136 if (pdata->penc1)
120 val |= PENC; 137 val |= PENC;
121 for (i = 0; i < 3; i++) { 138 for (i = 0; i < 3; i++) {
122 /* OVCn bits follow each other in the right order */ 139 /* OVCn bits follow each other in the right order */
123 if (pdata->ovc_pin[i].select_3_3v) 140 if (pdata->ovc_pin[i].select_3_3v)
124 val |= OVC0 << i; 141 val |= OVC0 << i;
125 /* OVCn_ACT bits are spaced by irregular intervals */ 142 /* OVCn_ACT bits are spaced by irregular intervals */
126 if (pdata->ovc_pin[i].active_high) 143 if (pdata->ovc_pin[i].active_high)
127 val |= ovcn_act[i]; 144 val |= ovcn_act[i];
128 } 145 }
129 iowrite32(val, (reg0 + USBPCTRL0)); 146 iowrite32(val, (reg0 + USBPCTRL0));
130 147
131 /* 148 /*
132 * Bus alignment settings 149 * Bus alignment settings
133 */ 150 */
134 151
135 /* (1) EHCI bus alignment (little endian) */ 152 /* (1) EHCI bus alignment (little endian) */
136 iowrite32(0x00000000, (reg0 + USBEH0)); 153 iowrite32(0x00000000, (reg0 + USBEH0));
137 154
138 /* (1) OHCI bus alignment (little endian) */ 155 /* (1) OHCI bus alignment (little endian) */
139 iowrite32(0x00000000, (reg0 + USBOH0)); 156 iowrite32(0x00000000, (reg0 + USBOH0));
140 } 157 }
141 158
142 phy_init_end: 159 phy_init_end:
143 spin_unlock_irqrestore(&priv->lock, flags); 160 spin_unlock_irqrestore(&priv->lock, flags);
144 161
145 return 0; 162 return 0;
146 } 163 }
147 164
148 static void rcar_usb_phy_shutdown(struct usb_phy *phy) 165 static void rcar_usb_phy_shutdown(struct usb_phy *phy)
149 { 166 {
150 struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy); 167 struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy);
151 void __iomem *reg0 = priv->reg0; 168 void __iomem *reg0 = priv->reg0;
152 unsigned long flags; 169 unsigned long flags;
153 170
154 spin_lock_irqsave(&priv->lock, flags); 171 spin_lock_irqsave(&priv->lock, flags);
155 172
156 if (priv->counter-- == 1) /* last user */ 173 if (priv->counter-- == 1) /* last user */
157 iowrite32(0x00000000, (reg0 + USBPCTRL1)); 174 iowrite32(0x00000000, (reg0 + USBPCTRL1));
158 175
159 spin_unlock_irqrestore(&priv->lock, flags); 176 spin_unlock_irqrestore(&priv->lock, flags);
160 } 177 }
161 178
162 static int rcar_usb_phy_probe(struct platform_device *pdev) 179 static int rcar_usb_phy_probe(struct platform_device *pdev)
163 { 180 {
164 struct rcar_usb_phy_priv *priv; 181 struct rcar_usb_phy_priv *priv;
165 struct resource *res0; 182 struct resource *res0, *res1;
166 struct device *dev = &pdev->dev; 183 struct device *dev = &pdev->dev;
167 void __iomem *reg0; 184 void __iomem *reg0, *reg1 = NULL;
168 int ret; 185 int ret;
169 186
170 if (!pdev->dev.platform_data) { 187 if (!pdev->dev.platform_data) {
171 dev_err(dev, "No platform data\n"); 188 dev_err(dev, "No platform data\n");
172 return -EINVAL; 189 return -EINVAL;
173 } 190 }
174 191
175 res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); 192 res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176 if (!res0) { 193 if (!res0) {
177 dev_err(dev, "Not enough platform resources\n"); 194 dev_err(dev, "Not enough platform resources\n");
178 return -EINVAL; 195 return -EINVAL;
179 } 196 }
180 197
181 reg0 = devm_ioremap_resource(dev, res0); 198 reg0 = devm_ioremap_resource(dev, res0);
182 if (IS_ERR(reg0)) 199 if (IS_ERR(reg0))
183 return PTR_ERR(reg0); 200 return PTR_ERR(reg0);
184 201
202 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
203 if (res1) {
204 reg1 = devm_ioremap_resource(dev, res1);
205 if (IS_ERR(reg1))
206 return PTR_ERR(reg1);
207 }
208
185 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 209 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
186 if (!priv) { 210 if (!priv) {
187 dev_err(dev, "priv data allocation error\n"); 211 dev_err(dev, "priv data allocation error\n");
188 return -ENOMEM; 212 return -ENOMEM;
189 } 213 }
190 214
191 priv->reg0 = reg0; 215 priv->reg0 = reg0;
216 priv->reg1 = reg1;
192 priv->counter = 0; 217 priv->counter = 0;
193 priv->phy.dev = dev; 218 priv->phy.dev = dev;
194 priv->phy.label = dev_name(dev); 219 priv->phy.label = dev_name(dev);
195 priv->phy.init = rcar_usb_phy_init; 220 priv->phy.init = rcar_usb_phy_init;
196 priv->phy.shutdown = rcar_usb_phy_shutdown; 221 priv->phy.shutdown = rcar_usb_phy_shutdown;
197 spin_lock_init(&priv->lock); 222 spin_lock_init(&priv->lock);
198 223
199 ret = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2); 224 ret = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
200 if (ret < 0) { 225 if (ret < 0) {
201 dev_err(dev, "usb phy addition error\n"); 226 dev_err(dev, "usb phy addition error\n");
202 return ret; 227 return ret;
203 } 228 }
204 229
205 platform_set_drvdata(pdev, priv); 230 platform_set_drvdata(pdev, priv);
206 231
207 return ret; 232 return ret;
208 } 233 }
209 234
210 static int rcar_usb_phy_remove(struct platform_device *pdev) 235 static int rcar_usb_phy_remove(struct platform_device *pdev)
211 { 236 {
212 struct rcar_usb_phy_priv *priv = platform_get_drvdata(pdev); 237 struct rcar_usb_phy_priv *priv = platform_get_drvdata(pdev);
213 238
214 usb_remove_phy(&priv->phy); 239 usb_remove_phy(&priv->phy);
215 240
216 return 0; 241 return 0;
217 } 242 }
218 243
219 static struct platform_driver rcar_usb_phy_driver = { 244 static struct platform_driver rcar_usb_phy_driver = {
220 .driver = { 245 .driver = {
221 .name = "rcar_usb_phy", 246 .name = "rcar_usb_phy",
222 }, 247 },
223 .probe = rcar_usb_phy_probe, 248 .probe = rcar_usb_phy_probe,
224 .remove = rcar_usb_phy_remove, 249 .remove = rcar_usb_phy_remove,
225 }; 250 };
226 251
227 module_platform_driver(rcar_usb_phy_driver); 252 module_platform_driver(rcar_usb_phy_driver);
228 253
229 MODULE_LICENSE("GPL v2"); 254 MODULE_LICENSE("GPL v2");
230 MODULE_DESCRIPTION("Renesas R-Car USB phy"); 255 MODULE_DESCRIPTION("Renesas R-Car USB phy");
231 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); 256 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
232 257
include/linux/platform_data/usb-rcar-phy.h
Diff comments   View file @ 54407f1
1 /* 1 /*
2 * Copyright (C) 2013 Renesas Solutions Corp. 2 * Copyright (C) 2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Cogent Embedded, Inc. 3 * Copyright (C) 2013 Cogent Embedded, Inc.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9 9
10 #ifndef __USB_RCAR_PHY_H 10 #ifndef __USB_RCAR_PHY_H
11 #define __USB_RCAR_PHY_H 11 #define __USB_RCAR_PHY_H
12 12
13 #include <linux/types.h> 13 #include <linux/types.h>
14 14
15 struct rcar_phy_platform_data { 15 struct rcar_phy_platform_data {
16 bool ferrite_bead:1; /* (R8A7778 only) */
17
16 bool port1_func:1; /* true: port 1 used by function, false: host */ 18 bool port1_func:1; /* true: port 1 used by function, false: host */
17 unsigned penc1:1; /* Output of the PENC1 pin in function mode */ 19 unsigned penc1:1; /* Output of the PENC1 pin in function mode */
18 struct { /* Overcurrent pin control for ports 0..2 */ 20 struct { /* Overcurrent pin control for ports 0..2 */
19 bool select_3_3v:1; /* true: USB_OVCn pin, false: OVCn pin */ 21 bool select_3_3v:1; /* true: USB_OVCn pin, false: OVCn pin */
20 /* Set to false on port 1 in function mode */ 22 /* Set to false on port 1 in function mode */
21 bool active_high:1; /* true: active high, false: active low */ 23 bool active_high:1; /* true: active high, false: active low */
22 /* Set to true on port 1 in function mode */ 24 /* Set to true on port 1 in function mode */
23 } ovc_pin[3]; 25 } ovc_pin[3]; /* (R8A7778 only has 2 ports) */
24 }; 26 };
25 27
26 #endif /* __USB_RCAR_PHY_H */ 28 #endif /* __USB_RCAR_PHY_H */
27 29