phy-rcar-usb: add R8A7778 support

The driver currently only supports R8A7779 SoC. Compared to it, R8A7778 USB-PHY has extra register range containing two high-speed signal quality characteristic control registers which should be set up during USB-PHY startup depending on whether a ferrite bead is in use or not. So, we now handle an optional second memory range in the driver's probe method, add the 'ferrite_bead' field to the driver's platform data, and add an extra (optional) step to the USB-PHY startup routine which sets up the extended registers. Also mark in the driver's Kconfig section that R8A7778 is now supported and generally clarify that section, uppercasing the word "phy" and also changing the module name that got lost in the big driver rename, while at it... The patch has been tested on the Marzen and BOCK-W boards. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

phy-rcar-usb: add R8A7778 support
The driver currently only supports R8A7779 SoC. Compared to it, R8A7778 USB-PHY has extra register range containing two high-speed signal quality characteristic control registers which should be set up during USB-PHY startup depending on whether a ferrite bead is in use or not. So, we now handle an optional second memory range in the driver's probe method, add the 'ferrite_bead' field to the driver's platform data, and add an extra (optional) step to the USB-PHY startup routine which sets up the extended registers. Also mark in the driver's Kconfig section that R8A7778 is now supported and generally clarify that section, uppercasing the word "phy" and also changing the module name that got lost in the big driver rename, while at it... The patch has been tested on the Marzen and BOCK-W boards. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Sergei Shtylyov · Simon Horman
1 parent 7173e59e6b
Showing 3 changed files with 39 additions and 12 deletions Side-by-side Diff
drivers/usb/phy/Kconfig
drivers/usb/phy/phy-rcar-usb.c
include/linux/platform_data/usb-rcar-phy.h
@@ -181,15 +181,15 @@
 	  MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
  
 config USB_RCAR_PHY
-	tristate "Renesas R-Car USB phy support"
+	tristate "Renesas R-Car USB PHY support"
 	depends on USB || USB_GADGET
 	help
-	  Say Y here to add support for the Renesas R-Car USB phy driver.
-	  This chip is typically used as USB phy for USB host, gadget.
-	  This driver supports: R8A7779
+	  Say Y here to add support for the Renesas R-Car USB common PHY driver.
+	  This chip is typically used as USB PHY for USB host, gadget.
+	  This driver supports R8A7778 and R8A7779.
  
 	  To compile this driver as a module, choose M here: the
-	  module will be called rcar-phy.
+	  module will be called phy-rcar-usb.
  
 config USB_ULPI
 	bool "Generic ULPI Transceiver Driver"
@@ -26,15 +26,21 @@
 #define USBOH0		0x1C
 #define USBCTL0		0x58
  
+/* High-speed signal quality characteristic control registers (R8A7778 only) */
+#define HSQCTL1		0x24
+#define HSQCTL2		0x28
+
 /* USBPCTRL0 */
-#define OVC2		(1 << 10) /* Switches the OVC input pin for port 2: */
+#define OVC2		(1 << 10) /* (R8A7779 only)			*/
+				/* Switches the OVC input pin for port 2: */
 				/* 1: USB_OVC2, 0: OVC2			*/
 #define OVC1_VBUS1	(1 << 9) /* Switches the OVC input pin for port 1: */
 				/* 1: USB_OVC1, 0: OVC1/VBUS1		*/
 				/* Function mode: set to 0		*/
 #define OVC0		(1 << 8) /* Switches the OVC input pin for port 0: */
 				/* 1: USB_OVC0 pin, 0: OVC0		*/
-#define OVC2_ACT 	(1 << 6) /* Host mode: OVC2 polarity:		*/
+#define OVC2_ACT 	(1 << 6) /* (R8A7779 only)			*/
+				/* Host mode: OVC2 polarity:		*/
 				/* 1: active-high, 0: active-low	*/
 #define PENC		(1 << 4) /* Function mode: output level of PENC1 pin: */
 				/* 1: high, 0: low			*/
@@ -59,6 +65,7 @@
 	spinlock_t lock;
  
 	void __iomem *reg0;
+	void __iomem *reg1;
 	int counter;
 };
  
@@ -78,6 +85,7 @@
 	struct device *dev = phy->dev;
 	struct rcar_phy_platform_data *pdata = dev->platform_data;
 	void __iomem *reg0 = priv->reg0;
+	void __iomem *reg1 = priv->reg1;
 	static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT };
 	int i;
 	u32 val;
@@ -96,7 +104,16 @@
 		/* (2) start USB-PHY internal PLL */
 		iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1));
  
-		/* (3) USB module status check */
+		/* (3) set USB-PHY in accord with the conditions of usage */
+		if (reg1) {
+			u32 hsqctl1 = pdata->ferrite_bead ? 0x41 : 0;
+			u32 hsqctl2 = pdata->ferrite_bead ? 0x0d : 7;
+
+			iowrite32(hsqctl1, reg1 + HSQCTL1);
+			iowrite32(hsqctl2, reg1 + HSQCTL2);
+		}
+
+		/* (4) USB module status check */
 		for (i = 0; i < 1024; i++) {
 			udelay(10);
 			val = ioread32(reg0 + USBST);
@@ -109,7 +126,7 @@
 			goto phy_init_end;
 		}
  
-		/* (4) USB-PHY reset clear */
+		/* (5) USB-PHY reset clear */
 		iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1));
  
 		/* Board specific port settings */
  
@@ -162,9 +179,9 @@
 static int rcar_usb_phy_probe(struct platform_device *pdev)
 {
 	struct rcar_usb_phy_priv *priv;
-	struct resource *res0;
+	struct resource *res0, *res1;
 	struct device *dev = &pdev->dev;
-	void __iomem *reg0;
+	void __iomem *reg0, *reg1 = NULL;
 	int ret;
  
 	if (!pdev->dev.platform_data) {
@@ -182,6 +199,13 @@
 	if (IS_ERR(reg0))
 		return PTR_ERR(reg0);
  
+	res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (res1) {
+		reg1 = devm_ioremap_resource(dev, res1);
+		if (IS_ERR(reg1))
+			return PTR_ERR(reg1);
+	}
+
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv) {
 		dev_err(dev, "priv data allocation error\n");
@@ -189,6 +213,7 @@
 	}
  
 	priv->reg0		= reg0;
+	priv->reg1		= reg1;
 	priv->counter		= 0;
 	priv->phy.dev		= dev;
 	priv->phy.label		= dev_name(dev);
@@ -13,6 +13,8 @@
 #include <linux/types.h>
  
 struct rcar_phy_platform_data {
+	bool ferrite_bead:1;	/* (R8A7778 only)			*/
+
 	bool port1_func:1;	/* true: port 1 used by function, false: host */
 	unsigned penc1:1;	/* Output of the PENC1 pin in function mode */
 	struct {		/* Overcurrent pin control for ports 0..2 */
@@ -20,7 +22,7 @@
 				/* Set to false on port 1 in function mode */
 		bool active_high:1; /* true: active  high, false: active low */
 				/* Set to true  on port 1 in function mode */
-	} ovc_pin[3];
+	} ovc_pin[3];		/* (R8A7778 only has 2 ports)		*/
 };
  
 #endif /* __USB_RCAR_PHY_H */
...	...	@@ -181,15 +181,15 @@
181	181	MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
182	182
183	183	config USB_RCAR_PHY
184		- tristate "Renesas R-Car USB phy support"
	184	+ tristate "Renesas R-Car USB PHY support"
185	185	depends on USB \|\| USB_GADGET
186	186	help
187		- Say Y here to add support for the Renesas R-Car USB phy driver.
188		- This chip is typically used as USB phy for USB host, gadget.
189		- This driver supports: R8A7779
	187	+ Say Y here to add support for the Renesas R-Car USB common PHY driver.
	188	+ This chip is typically used as USB PHY for USB host, gadget.
	189	+ This driver supports R8A7778 and R8A7779.
190	190
191	191	To compile this driver as a module, choose M here: the
192		- module will be called rcar-phy.
	192	+ module will be called phy-rcar-usb.
193	193
194	194	config USB_ULPI
195	195	bool "Generic ULPI Transceiver Driver"
...	...	@@ -26,15 +26,21 @@
26	26	#define USBOH0 0x1C
27	27	#define USBCTL0 0x58
28	28
	29	+/* High-speed signal quality characteristic control registers (R8A7778 only) */
	30	+#define HSQCTL1 0x24
	31	+#define HSQCTL2 0x28
	32	+
29	33	/* USBPCTRL0 */
30		-#define OVC2 (1 << 10) /* Switches the OVC input pin for port 2: */
	34	+#define OVC2 (1 << 10) /* (R8A7779 only) */
	35	+ /* Switches the OVC input pin for port 2: */
31	36	/* 1: USB_OVC2, 0: OVC2 */
32	37	#define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */
33	38	/* 1: USB_OVC1, 0: OVC1/VBUS1 */
34	39	/* Function mode: set to 0 */
35	40	#define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */
36	41	/* 1: USB_OVC0 pin, 0: OVC0 */
37		-#define OVC2_ACT (1 << 6) /* Host mode: OVC2 polarity: */
	42	+#define OVC2_ACT (1 << 6) /* (R8A7779 only) */
	43	+ /* Host mode: OVC2 polarity: */
38	44	/* 1: active-high, 0: active-low */
39	45	#define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */
40	46	/* 1: high, 0: low */
...	...	@@ -59,6 +65,7 @@
59	65	spinlock_t lock;
60	66
61	67	void __iomem *reg0;
	68	+ void __iomem *reg1;
62	69	int counter;
63	70	};
64	71
...	...	@@ -78,6 +85,7 @@
78	85	struct device *dev = phy->dev;
79	86	struct rcar_phy_platform_data *pdata = dev->platform_data;
80	87	void __iomem *reg0 = priv->reg0;
	88	+ void __iomem *reg1 = priv->reg1;
81	89	static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT };
82	90	int i;
83	91	u32 val;
...	...	@@ -96,7 +104,16 @@
96	104	/* (2) start USB-PHY internal PLL */
97	105	iowrite32(PHY_ENB \| PLL_ENB, (reg0 + USBPCTRL1));
98	106
99		- /* (3) USB module status check */
	107	+ /* (3) set USB-PHY in accord with the conditions of usage */
	108	+ if (reg1) {
	109	+ u32 hsqctl1 = pdata->ferrite_bead ? 0x41 : 0;
	110	+ u32 hsqctl2 = pdata->ferrite_bead ? 0x0d : 7;
	111	+
	112	+ iowrite32(hsqctl1, reg1 + HSQCTL1);
	113	+ iowrite32(hsqctl2, reg1 + HSQCTL2);
	114	+ }
	115	+
	116	+ /* (4) USB module status check */
100	117	for (i = 0; i < 1024; i++) {
101	118	udelay(10);
102	119	val = ioread32(reg0 + USBST);
...	...	@@ -109,7 +126,7 @@
109	126	goto phy_init_end;
110	127	}
111	128
112		- /* (4) USB-PHY reset clear */
	129	+ /* (5) USB-PHY reset clear */
113	130	iowrite32(PHY_ENB \| PLL_ENB \| PHY_RST, (reg0 + USBPCTRL1));
114	131
115	132	/* Board specific port settings */
116	133
...	...	@@ -162,9 +179,9 @@
162	179	static int rcar_usb_phy_probe(struct platform_device *pdev)
163	180	{
164	181	struct rcar_usb_phy_priv *priv;
165		- struct resource *res0;
	182	+ struct resource res0, res1;
166	183	struct device *dev = &pdev->dev;
167		- void __iomem *reg0;
	184	+ void __iomem reg0, reg1 = NULL;
168	185	int ret;
169	186
170	187	if (!pdev->dev.platform_data) {
...	...	@@ -182,6 +199,13 @@
182	199	if (IS_ERR(reg0))
183	200	return PTR_ERR(reg0);
184	201
	202	+ res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	203	+ if (res1) {
	204	+ reg1 = devm_ioremap_resource(dev, res1);
	205	+ if (IS_ERR(reg1))
	206	+ return PTR_ERR(reg1);
	207	+ }
	208	+
185	209	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
186	210	if (!priv) {
187	211	dev_err(dev, "priv data allocation error\n");
...	...	@@ -189,6 +213,7 @@
189	213	}
190	214
191	215	priv->reg0 = reg0;
	216	+ priv->reg1 = reg1;
192	217	priv->counter = 0;
193	218	priv->phy.dev = dev;
194	219	priv->phy.label = dev_name(dev);
...	...	@@ -13,6 +13,8 @@
13	13	#include <linux/types.h>
14	14
15	15	struct rcar_phy_platform_data {
	16	+ bool ferrite_bead:1; /* (R8A7778 only) */
	17	+
16	18	bool port1_func:1; /* true: port 1 used by function, false: host */
17	19	unsigned penc1:1; /* Output of the PENC1 pin in function mode */
18	20	struct { /* Overcurrent pin control for ports 0..2 */
...	...	@@ -20,7 +22,7 @@
20	22	/* Set to false on port 1 in function mode */
21	23	bool active_high:1; /* true: active high, false: active low */
22	24	/* Set to true on port 1 in function mode */
23		- } ovc_pin[3];
	25	+ } ovc_pin[3]; /* (R8A7778 only has 2 ports) */
24	26	};
25	27
26	28	#endif /* __USB_RCAR_PHY_H */