Commit 7a847f819063b80cc5b38d39e8aad4d60f6ca2fd

Authored by Paul Mundt
1 parent aa4a5db52a

sh: More tidying for large base pages.

There were a few more things that needed fixing up, namely THREAD_SIZE
and the TLB miss handler where certain PTRS_PER_PGD == PTRS_PER_PTE
assumptions were being made.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 4 changed files with 19 additions and 13 deletions Side-by-side Diff

... ... @@ -596,6 +596,8 @@
596 596 config ZERO_PAGE_OFFSET
597 597 hex "Zero page offset"
598 598 default "0x00004000" if SH_MPC1211 || SH_SH03
  599 + default "0x00010000" if PAGE_SIZE_64KB
  600 + default "0x00002000" if PAGE_SIZE_8KB
599 601 default "0x00001000"
600 602 help
601 603 This sets the default offset of zero page.
arch/sh/kernel/cpu/sh3/entry.S
... ... @@ -332,12 +332,6 @@
332 332 !
333 333 !
334 334  
335   -/* This code makes some assumptions to improve performance.
336   - * Make sure they are stil true. */
337   -#if PTRS_PER_PGD != PTRS_PER_PTE
338   -#error PGD and PTE sizes don't match
339   -#endif
340   -
341 335 /* gas doesn't flag impossible values for mov #immediate as an error */
342 336 #if (_PAGE_PRESENT >> 2) > 0x7f
343 337 #error cannot load PAGE_PRESENT as an immediate
... ... @@ -399,6 +393,7 @@
399 393  
400 394 bt 20f ! 110 BR
401 395  
  396 + mov.w 3f, k3 ! 8 LS (latency=2) (PTRS_PER_PTE-1) << 2
402 397 and k3, k0 ! 78 EX
403 398 mov.w 5f, k4 ! 8 LS (latency=2) _PAGE_PRESENT
404 399  
405 400  
... ... @@ -491,8 +486,9 @@
491 486 .align 5
492 487 ! Once cache line if possible...
493 488 1: .long swapper_pg_dir
  489 +3: .short (PTRS_PER_PTE-1) << 2
494 490 4: .short (PTRS_PER_PGD-1) << 2
495   -5: .short _PAGE_PRESENT
  491 +5: .long _PAGE_PRESENT
496 492 7: .long _PAGE_FLAGS_HARDWARE_MASK
497 493 8: .long MMU_PTEH
498 494 #ifdef COUNT_EXCEPTIONS
include/asm-sh/pgtable.h
... ... @@ -47,13 +47,13 @@
47 47 #define PGDIR_MASK (~(PGDIR_SIZE-1))
48 48  
49 49 /* Entries per level */
50   -#define PTRS_PER_PTE (PAGE_SIZE / 4)
  50 +#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
51 51 #define PTRS_PER_PGD (PAGE_SIZE / 4)
52 52  
53 53 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
54 54 #define FIRST_USER_ADDRESS 0
55 55  
56   -#define PTE_PHYS_MASK 0x1ffff000
  56 +#define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE)
57 57  
58 58 /*
59 59 * First 1MB map is used by fixed purpose.
include/asm-sh/thread_info.h
... ... @@ -32,12 +32,20 @@
32 32  
33 33 #define PREEMPT_ACTIVE 0x10000000
34 34  
35   -#ifdef CONFIG_4KSTACKS
36   -#define THREAD_SIZE (PAGE_SIZE)
  35 +#if defined(CONFIG_4KSTACKS)
  36 +#define THREAD_SIZE_ORDER (0)
  37 +#elif defined(CONFIG_PAGE_SIZE_4KB)
  38 +#define THREAD_SIZE_ORDER (1)
  39 +#elif defined(CONFIG_PAGE_SIZE_8KB)
  40 +#define THREAD_SIZE_ORDER (1)
  41 +#elif defined(CONFIG_PAGE_SIZE_64KB)
  42 +#define THREAD_SIZE_ORDER (0)
37 43 #else
38   -#define THREAD_SIZE (PAGE_SIZE * 2)
  44 +#error "Unknown thread size"
39 45 #endif
40   -#define STACK_WARN (THREAD_SIZE / 8)
  46 +
  47 +#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
  48 +#define STACK_WARN (THREAD_SIZE >> 3)
41 49  
42 50 /*
43 51 * macros/functions for gaining access to the thread information structure