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Commit 8f7b130d2b86d8e939052277aabcf71cd141c6a7

Authored by Eric Lee
1 parent f88566037c
Exists in smarc-imx_3.10.53_1.1.0_ga

Stable release for 3.10.53 kernel branch

Showing 20 changed files with 1786 additions and 359 deletions Inline Diff

Documentation/devicetree/bindings/power/bq2477x-charger.txt
Diff comments   View file @ 8f7b130
File was created 1 bq2477x charger
2 ~~~~~~~~~~~~~~~
3
4 Required properties :
5 - compatible : should contain "ti,bq2477x".
6 - ti,dac-ichg : Charge current that must be programmed
7 - ti,dac-v : The maximum charge voltage that must be programmed
8 - ti,dac-minsv : The minimum System voltage that must be programmed
9 - ti,dac-iin : The input current that must be programmed
10 - ti,wdt-refresh-timeout : watch dog timer that must be programmed
11 - ti,charger-detect-gpio : a GPIO spec for AC adapter detection. The flag
12 that determines if AC adapter presence is indicated by active low.
13 Set this to GPIO_ACTIVE_LOW if active low indicates adapter is present,
14 else GPIO_ACTIVE_HIGH.
15
16 Example:
17
18 bq2477x@6a {
19 compatible = "ti,bq2477x";
20 reg = <0x6a>;
21 ti,dac-ichg = <2240>;
22 ti,dac-v = <9008>;
23 ti,dac-minsv = <4608>;
24 ti,dac-iin = <4992>;
25 ti,wdt-refresh-timeout = <40>;
26 ti,charger-detect-gpio = <&gpio TEGRA_GPIO(J, 0) GPIO_ACTIVE_LOW>;
27 };
28
arch/arm/boot/dts/imx6dl-smarcfimx6-1080p.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6dl-smarcfimx6.dts"
10
11 /* Dual-Channel LVDS Panel for AUO G240HW01 V0 24-inch Color TFT 1920x1080 Panel Settings */
12 &ldb {
13 status = "okay";
14 split-mode;
15
16 lvds-channel@0 {
17 fsl,data-mapping = "spwg";
18 fsl,data-width = <24>;
19 primary;
20 status = "okay";
21
22 display-timings {
23 native-mode = <&timing0>;
24 timing0: g24hw01 {
25 clock-frequency = <130005200>;
26 hactive = <1920>;
27 vactive = <1080>;
28 hback-porch = <100>;
29 hfront-porch = <40>;
30 vback-porch = <30>;
31 vfront-porch = <3>;
32 hsync-len = <10>;
33 vsync-len = <2>;
34 };
35 };
36 };
37
38 lvds-channel@1 {
39 fsl,data-mapping = "spwg";
40 fsl,data-width = <24>;
41 status = "okay";
42
43 display-timings {
44 native-mode = <&timing1>;
45 timing1: g24hw01 {
46 clock-frequency = <130005200>;
47 hactive = <1920>;
48 vactive = <1080>;
49 hback-porch = <100>;
50 hfront-porch = <40>;
51 vback-porch = <30>;
52 vfront-porch = <3>;
53 hsync-len = <10>;
54 vsync-len = <2>;
55 };
56 };
57 };
58 };
59
arch/arm/boot/dts/imx6dl-smarcfimx6-wvga.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6dl-smarcfimx6.dts"
10
11 /* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */
12 &ldb {
13 status = "okay";
14
15 lvds-channel@0 {
16 fsl,data-mapping = "spwg";
17 fsl,data-width = <24>;
18 primary;
19 status = "okay";
20
21 display-timings {
22 native-mode = <&timing0>;
23 timing0: g070vw01 {
24 clock-frequency = <33300000>;
25 hactive = <800>;
26 vactive = <480>;
27 hback-porch = <64>;
28 hfront-porch = <64>;
29 vback-porch = <12>;
30 vfront-porch = <4>;
31 hsync-len = <128>;
32 vsync-len = <12>;
33 };
34 };
35 };
36
37 lvds-channel@1 {
38 fsl,data-mapping = "spwg";
39 fsl,data-width = <24>;
40 status = "okay";
41
42 display-timings {
43 native-mode = <&timing1>;
44 timing1: g070vw01 {
45 clock-frequency = <33300000>;
46 hactive = <800>;
47 vactive = <480>;
48 hback-porch = <64>;
49 hfront-porch = <64>;
50 vback-porch = <12>;
51 vfront-porch = <4>;
52 hsync-len = <128>;
53 vsync-len = <12>;
54 };
55 };
56 };
57 };
58
arch/arm/boot/dts/imx6dl-smarcfimx6-wxga.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6dl-smarcfimx6.dts"
10
11 /* LVDS Panel for AUO G185XW01 V2 18.5-inch Color TFT 1360x768 Panel Settings */
12 &ldb {
13 status = "okay";
14
15 lvds-channel@0 {
16 fsl,data-mapping = "spwg";
17 fsl,data-width = <24>;
18 primary;
19 status = "okay";
20
21 display-timings {
22 native-mode = <&timing0>;
23 timing0: g185xw01 {
24 clock-frequency = <78000000>;
25 hactive = <1360>;
26 vactive = <768>;
27 hback-porch = <60>;
28 hfront-porch = <60>;
29 vback-porch = <18>;
30 vfront-porch = <4>;
31 hsync-len = <120>;
32 vsync-len = <18>;
33 };
34 };
35 };
36
37 lvds-channel@1 {
38 fsl,data-mapping = "spwg";
39 fsl,data-width = <24>;
40 status = "okay";
41
42 display-timings {
43 native-mode = <&timing1>;
44 timing1: g185xw01 {
45 clock-frequency = <78000000>;
46 hactive = <1360>;
47 vactive = <768>;
48 hback-porch = <60>;
49 hfront-porch = <60>;
50 vback-porch = <18>;
51 vfront-porch = <4>;
52 hsync-len = <120>;
53 vsync-len = <18>;
54 };
55 };
56 };
57 };
58
arch/arm/boot/dts/imx6dl-smarcfimx6-xga.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6dl-smarcfimx6.dts"
10
11 &ldb {
12 status = "okay";
13
14 lvds-channel@0 {
15 fsl,data-mapping = "spwg";
16 fsl,data-width = <24>;
17 primary;
18 status = "okay";
19
20 display-timings {
21 native-mode = <&timing0>;
22 timing0: hsd100pxn1 {
23 clock-frequency = <65000000>;
24 hactive = <1024>;
25 vactive = <768>;
26 hback-porch = <220>;
27 hfront-porch = <40>;
28 vback-porch = <21>;
29 vfront-porch = <7>;
30 hsync-len = <60>;
31 vsync-len = <10>;
32 };
33 };
34 };
35
36 lvds-channel@1 {
37 fsl,data-mapping = "spwg";
38 fsl,data-width = <24>;
39 status = "okay";
40
41 display-timings {
42 native-mode = <&timing1>;
43 timing1: hsd100pxn1 {
44 clock-frequency = <65000000>;
45 hactive = <1024>;
46 vactive = <768>;
47 hback-porch = <220>;
48 hfront-porch = <40>;
49 vback-porch = <21>;
50 vfront-porch = <7>;
51 hsync-len = <60>;
52 vsync-len = <10>;
53 };
54 };
55 };
56 };
57
arch/arm/boot/dts/imx6dl-smarcfimx6.dts
Diff comments   View file @ 8f7b130
1 /* 1 /*
2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. 2 * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include "imx6dl-smarc.dtsi" 11 #include "imx6dl-smarc.dtsi"
12 #include "imx6qdl-smarcfimx6.dtsi" 12 #include "imx6qdl-smarcfimx6.dtsi"
13 #include "imx6dl-smarc-common.dtsi" 13 #include "imx6dl-smarc-common.dtsi"
14 14
15 / { 15 / {
16 model = "Freescale i.MX6 DualLite SABRE Smart Device Board(PFUZE100)"; 16 model = "Freescale i.MX6 DualLite SABRE Smart Device Board(PFUZE100)";
17 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl", "fsl, imx6dl-smarcfimx6"; 17 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl", "fsl, imx6dl-smarcfimx6";
18 }; 18 };
19 19
20 &cpu0 { 20 &ldb {
21 arm-supply = <&reg_arm>; 21 lvds-channel@0 {
22 soc-supply = <&reg_soc>; 22 crtc = "ipu1-di0";
23 pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */ 23 };
24
25 lvds-channel@1 {
26 crtc = "ipu1-di1";
27 };
24 }; 28 };
25 29
26 &gpc { 30 &mxcfb1 {
27 fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */ 31 status = "okay";
28 fsl,wdog-reset = <1>; /* watchdog select of reset source */
29 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
30 }; 32 };
31 33
32 &gpu { 34 &mxcfb2 {
33 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ 35 status = "okay";
36 };
37
38 &pxp {
39 status = "okay";
34 }; 40 };
35 41
36 &vpu { 42 &vpu {
37 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ 43 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
38 }; 44 };
39 45
40 &wdog1 { 46 &wdog1 {
41 status = "okay"; 47 status = "okay";
42 }; 48 };
43 49
44 &wdog2 { 50 &wdog2 {
45 status = "disabled"; 51 status = "disabled";
arch/arm/boot/dts/imx6q-smarcfimx6-1080p.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6q-smarcfimx6.dts"
10
11 /* Dual-Channel LVDS Panel for AUO G240HW01 V0 24-inch Color TFT 1920x1080 Panel Settings */
12 &ldb {
13 status = "okay";
14 split-mode;
15
16 lvds-channel@0 {
17 fsl,data-mapping = "spwg";
18 fsl,data-width = <24>;
19 primary;
20 status = "okay";
21
22 display-timings {
23 native-mode = <&timing0>;
24 timing0: g24hw01 {
25 clock-frequency = <130005200>;
26 hactive = <1920>;
27 vactive = <1080>;
28 hback-porch = <100>;
29 hfront-porch = <40>;
30 vback-porch = <30>;
31 vfront-porch = <3>;
32 hsync-len = <10>;
33 vsync-len = <2>;
34 };
35 };
36 };
37
38 lvds-channel@1 {
39 fsl,data-mapping = "spwg";
40 fsl,data-width = <24>;
41 status = "okay";
42
43 display-timings {
44 native-mode = <&timing1>;
45 timing1: g24hw01 {
46 clock-frequency = <130005200>;
47 hactive = <1920>;
48 vactive = <1080>;
49 hback-porch = <100>;
50 hfront-porch = <40>;
51 vback-porch = <30>;
52 vfront-porch = <3>;
53 hsync-len = <10>;
54 vsync-len = <2>;
55 };
56 };
57 };
58 };
59
arch/arm/boot/dts/imx6q-smarcfimx6-wvga.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6q-smarcfimx6.dts"
10
11 /* LVDS Panel for AUO G070VW01 V0 7-inch Color TFT 800x480 Panel Settings */
12 &ldb {
13 status = "okay";
14
15 lvds-channel@0 {
16 fsl,data-mapping = "spwg";
17 fsl,data-width = <24>;
18 primary;
19 status = "okay";
20
21 display-timings {
22 native-mode = <&timing0>;
23 timing0: g070vw01 {
24 clock-frequency = <33300000>;
25 hactive = <800>;
26 vactive = <480>;
27 hback-porch = <64>;
28 hfront-porch = <64>;
29 vback-porch = <12>;
30 vfront-porch = <4>;
31 hsync-len = <128>;
32 vsync-len = <12>;
33 /*hsync-active = <0>;
34 vsync-active = <0>;*/
35 };
36 };
37 };
38
39 lvds-channel@1 {
40 fsl,data-mapping = "spwg";
41 fsl,data-width = <24>;
42 status = "okay";
43
44 display-timings {
45 native-mode = <&timing1>;
46 timing1: g070vw01 {
47 clock-frequency = <33300000>;
48 hactive = <800>;
49 vactive = <480>;
50 hback-porch = <64>;
51 hfront-porch = <64>;
52 vback-porch = <12>;
53 vfront-porch = <4>;
54 hsync-len = <128>;
55 vsync-len = <12>;
56 /*hsync-active = <0>;
57 vsync-active = <0>;*/
58 };
59 };
60 };
61 };
62
arch/arm/boot/dts/imx6q-smarcfimx6-wxga.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6q-smarcfimx6.dts"
10
11 /* LVDS Panel for AUO G185XW01 V2 18.5-inch Color TFT 1360x768 Panel Settings */
12 &ldb {
13 status = "okay";
14
15 lvds-channel@0 {
16 fsl,data-mapping = "spwg";
17 fsl,data-width = <24>;
18 primary;
19 status = "okay";
20
21 display-timings {
22 native-mode = <&timing0>;
23 timing0: g185xw01 {
24 clock-frequency = <78000000>;
25 hactive = <1360>;
26 vactive = <768>;
27 hback-porch = <60>;
28 hfront-porch = <60>;
29 vback-porch = <18>;
30 vfront-porch = <4>;
31 hsync-len = <120>;
32 vsync-len = <18>;
33 };
34 };
35 };
36
37 lvds-channel@1 {
38 fsl,data-mapping = "spwg";
39 fsl,data-width = <24>;
40 status = "okay";
41
42 display-timings {
43 native-mode = <&timing1>;
44 timing1: g185xw01 {
45 clock-frequency = <78000000>;
46 hactive = <1360>;
47 vactive = <768>;
48 hback-porch = <60>;
49 hfront-porch = <60>;
50 vback-porch = <18>;
51 vfront-porch = <4>;
52 hsync-len = <120>;
53 vsync-len = <18>;
54 };
55 };
56 };
57 };
58
arch/arm/boot/dts/imx6q-smarcfimx6-xga.dts
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * Copyright (C) 2015 Embedian, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include "imx6q-smarcfimx6.dts"
10
11 &ldb {
12 status = "okay";
13
14 lvds-channel@0 {
15 fsl,data-mapping = "spwg";
16 fsl,data-width = <24>;
17 primary;
18 status = "okay";
19
20 display-timings {
21 native-mode = <&timing0>;
22 timing0: hsd100pxn1 {
23 clock-frequency = <65000000>;
24 hactive = <1024>;
25 vactive = <768>;
26 hback-porch = <220>;
27 hfront-porch = <40>;
28 vback-porch = <21>;
29 vfront-porch = <7>;
30 hsync-len = <60>;
31 vsync-len = <10>;
32 };
33 };
34 };
35
36 lvds-channel@1 {
37 fsl,data-mapping = "spwg";
38 fsl,data-width = <24>;
39 status = "okay";
40
41 display-timings {
42 native-mode = <&timing1>;
43 timing1: hsd100pxn1 {
44 clock-frequency = <65000000>;
45 hactive = <1024>;
46 vactive = <768>;
47 hback-porch = <220>;
48 hfront-porch = <40>;
49 vback-porch = <21>;
50 vfront-porch = <7>;
51 hsync-len = <60>;
52 vsync-len = <10>;
53 };
54 };
55 };
56 };
57
arch/arm/boot/dts/imx6q-smarcfimx6.dts
Diff comments   View file @ 8f7b130
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations: 7 * Version 2 or later at the following locations:
8 * 8 *
9 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13 /dts-v1/; 13 /dts-v1/;
14 14
15 #include "imx6q-smarc.dtsi" 15 #include "imx6q-smarc.dtsi"
16 #include "imx6qdl-smarcfimx6.dtsi" 16 #include "imx6qdl-smarcfimx6.dtsi"
17 17
18 / { 18 / {
19 model = "Freescale i.MX6 Dual/Quad SMARC-FiMX6 Computer on Module"; 19 model = "Freescale i.MX6 Dual/Quad SMARC-FiMX6 Computer on Module";
20 compatible = "fsl,imx6q-sabresd", "fsl,imx6q", "fsl,imx6q-smarcfimx6"; 20 compatible = "fsl,imx6q-sabresd", "fsl,imx6q", "fsl,imx6q-smarcfimx6";
21 }; 21 };
22 22
23 &battery {
24 offset-charger = <1900>;
25 offset-discharger = <1694>;
26 offset-usb-charger = <1685>;
27 };
28
29 &ldb { 23 &ldb {
30 lvds-channel@0 { 24 lvds-channel@0 {
31 crtc = "ipu2-di0"; 25 crtc = "ipu2-di0";
32 }; 26 };
33 27
34 lvds-channel@1 { 28 lvds-channel@1 {
35 crtc = "ipu2-di1"; 29 crtc = "ipu2-di1";
36 }; 30 };
37 }; 31 };
38 32
39 &mxcfb1 { 33 &mxcfb1 {
40 status = "okay"; 34 status = "okay";
41 }; 35 };
42 36
43 &mxcfb2 { 37 &mxcfb2 {
44 status = "okay"; 38 status = "okay";
45 }; 39 };
46 40
47 &mxcfb3 { 41 &mxcfb3 {
48 status = "okay"; 42 status = "okay";
49 }; 43 };
50 44
51 &mxcfb4 { 45 &mxcfb4 {
52 status = "okay"; 46 status = "okay";
53 }; 47 };
54 48
55 &sata { 49 &sata {
56 status = "okay"; 50 status = "okay";
57 };
58
59 &cpu0 {
60 arm-supply = <&reg_arm>;
61 soc-supply = <&reg_soc>;
62 pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */
63 };
64
65 &gpc {
66 fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */
67 fsl,wdog-reset = <1>; /* watchdog select of reset source */
68 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
69 }; 51 };
70 52
71 &gpu { 53 &gpu {
72 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ 54 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
73 }; 55 };
74 56
75 &vpu { 57 &vpu {
76 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ 58 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
77 }; 59 };
78 60
79 &wdog1 { 61 &wdog1 {
80 status = "okay"; 62 status = "okay";
81 }; 63 };
82 64
83 &wdog2 { 65 &wdog2 {
84 status = "disabled"; 66 status = "disabled";
85 }; 67 };
86 68
arch/arm/boot/dts/imx6qdl-smarc.dtsi
Diff comments   View file @ 8f7b130
1 /* 1 /*
2 * Copyright 2011 Freescale Semiconductor, Inc. 2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations: 7 * Version 2 or later at the following locations:
8 * 8 *
9 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13 #include "skeleton.dtsi" 13 #include "skeleton.dtsi"
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 15
16 / { 16 / {
17 aliases { 17 aliases {
18 gpio0 = &gpio1; 18 gpio0 = &gpio1;
19 gpio1 = &gpio2; 19 gpio1 = &gpio2;
20 gpio2 = &gpio3; 20 gpio2 = &gpio3;
21 gpio3 = &gpio4; 21 gpio3 = &gpio4;
22 gpio4 = &gpio5; 22 gpio4 = &gpio5;
23 gpio5 = &gpio6; 23 gpio5 = &gpio6;
24 gpio6 = &gpio7; 24 gpio6 = &gpio7;
25 ipu0 = &ipu1; 25 ipu0 = &ipu1;
26 mmc0 = &usdhc1; 26 mmc0 = &usdhc1;
27 mmc1 = &usdhc2; 27 mmc1 = &usdhc2;
28 mmc2 = &usdhc3; 28 mmc2 = &usdhc3;
29 mmc3 = &usdhc4; 29 mmc3 = &usdhc4;
30 serial0 = &uart1; 30 serial0 = &uart1;
31 serial1 = &uart2; 31 serial1 = &uart2;
32 serial2 = &uart3; 32 serial2 = &uart3;
33 serial3 = &uart4; 33 serial3 = &uart4;
34 serial4 = &uart5; 34 serial4 = &uart5;
35 usbphy0 = &usbphy1; 35 usbphy0 = &usbphy1;
36 usbphy1 = &usbphy2; 36 usbphy1 = &usbphy2;
37 }; 37 };
38 38
39 intc: interrupt-controller@00a01000 { 39 intc: interrupt-controller@00a01000 {
40 compatible = "arm,cortex-a9-gic"; 40 compatible = "arm,cortex-a9-gic";
41 #interrupt-cells = <3>; 41 #interrupt-cells = <3>;
42 #address-cells = <1>; 42 /*#address-cells = <1>;
43 #size-cells = <1>; 43 #size-cells = <1>;*/
44 interrupt-controller; 44 interrupt-controller;
45 reg = <0x00a01000 0x1000>, 45 reg = <0x00a01000 0x1000>,
46 <0x00a00100 0x100>; 46 <0x00a00100 0x100>;
47 }; 47 };
48 48
49 clocks { 49 clocks {
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 52
53 ckil { 53 ckil {
54 compatible = "fsl,imx-ckil", "fixed-clock"; 54 compatible = "fsl,imx-ckil", "fixed-clock";
55 clock-frequency = <32768>; 55 clock-frequency = <32768>;
56 }; 56 };
57 57
58 ckih1 { 58 ckih1 {
59 compatible = "fsl,imx-ckih1", "fixed-clock"; 59 compatible = "fsl,imx-ckih1", "fixed-clock";
60 clock-frequency = <0>; 60 clock-frequency = <0>;
61 }; 61 };
62 62
63 osc { 63 osc {
64 compatible = "fsl,imx-osc", "fixed-clock"; 64 compatible = "fsl,imx-osc", "fixed-clock";
65 clock-frequency = <24000000>; 65 clock-frequency = <24000000>;
66 }; 66 };
67 }; 67 };
68 68
69 pu_dummy: pudummy_reg { 69 pu_dummy: pudummy_reg {
70 compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */ 70 compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
71 }; 71 };
72 72
73 mxs_viim { 73 mxs_viim {
74 compatible = "fsl,mxs_viim"; 74 compatible = "fsl,mxs_viim";
75 reg = <0x02098000 0x1000>, /* GPT base */ 75 reg = <0x02098000 0x1000>, /* GPT base */
76 <0x021bc000 0x1000>; /* OCOTP base */ 76 <0x021bc000 0x1000>; /* OCOTP base */
77 }; 77 };
78 78
79 soc { 79 soc {
80 #address-cells = <1>; 80 #address-cells = <1>;
81 #size-cells = <1>; 81 #size-cells = <1>;
82 compatible = "simple-bus"; 82 compatible = "simple-bus";
83 interrupt-parent = <&intc>; 83 interrupt-parent = <&intc>;
84 ranges; 84 ranges;
85 85
86 caam_sm: caam-sm@00100000 { 86 caam_sm: caam-sm@00100000 {
87 compatible = "fsl,imx6q-caam-sm"; 87 compatible = "fsl,imx6q-caam-sm";
88 reg = <0x00100000 0x3fff>; 88 reg = <0x00100000 0x3fff>;
89 }; 89 };
90 90
91 dma_apbh: dma-apbh@00110000 { 91 dma_apbh: dma-apbh@00110000 {
92 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 92 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
93 reg = <0x00110000 0x2000>; 93 reg = <0x00110000 0x2000>;
94 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>; 94 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
96 #dma-cells = <1>; 96 #dma-cells = <1>;
97 dma-channels = <4>; 97 dma-channels = <4>;
98 clocks = <&clks 106>; 98 clocks = <&clks 106>;
99 }; 99 };
100 100
101 irq_sec_vio: caam_secvio { 101 irq_sec_vio: caam_secvio {
102 compatible = "fsl,imx6q-caam-secvio"; 102 compatible = "fsl,imx6q-caam-secvio";
103 interrupts = <0 20 0x04>; 103 interrupts = <0 20 0x04>;
104 secvio_src = <0x8000001d>; 104 secvio_src = <0x8000001d>;
105 }; 105 };
106 106
107 gpmi: gpmi-nand@00112000 { 107 gpmi: gpmi-nand@00112000 {
108 compatible = "fsl,imx6q-gpmi-nand"; 108 compatible = "fsl,imx6q-gpmi-nand";
109 #address-cells = <1>; 109 #address-cells = <1>;
110 #size-cells = <1>; 110 #size-cells = <1>;
111 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 111 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
112 reg-names = "gpmi-nand", "bch"; 112 reg-names = "gpmi-nand", "bch";
113 interrupts = <0 15 0x04>; 113 interrupts = <0 15 0x04>;
114 interrupt-names = "bch"; 114 interrupt-names = "bch";
115 clocks = <&clks 152>, <&clks 153>, <&clks 151>, 115 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
116 <&clks 150>, <&clks 149>; 116 <&clks 150>, <&clks 149>;
117 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 117 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
118 "gpmi_bch_apb", "per1_bch"; 118 "gpmi_bch_apb", "per1_bch";
119 dmas = <&dma_apbh 0>; 119 dmas = <&dma_apbh 0>;
120 dma-names = "rx-tx"; 120 dma-names = "rx-tx";
121 status = "disabled"; 121 status = "disabled";
122 }; 122 };
123 123
124 timer@00a00600 { 124 timer@00a00600 {
125 compatible = "arm,cortex-a9-twd-timer"; 125 compatible = "arm,cortex-a9-twd-timer";
126 reg = <0x00a00600 0x20>; 126 reg = <0x00a00600 0x20>;
127 interrupts = <1 13 0xf01>; 127 interrupts = <1 13 0xf01>;
128 clocks = <&clks 15>; 128 clocks = <&clks 15>;
129 }; 129 };
130 130
131 L2: l2-cache@00a02000 { 131 L2: l2-cache@00a02000 {
132 compatible = "arm,pl310-cache"; 132 compatible = "arm,pl310-cache";
133 reg = <0x00a02000 0x1000>; 133 reg = <0x00a02000 0x1000>;
134 interrupts = <0 92 0x04>; 134 interrupts = <0 92 0x04>;
135 cache-unified; 135 cache-unified;
136 cache-level = <2>; 136 cache-level = <2>;
137 arm,tag-latency = <4 2 3>; 137 arm,tag-latency = <4 2 3>;
138 arm,data-latency = <4 2 3>; 138 arm,data-latency = <4 2 3>;
139 }; 139 };
140 140
141 pcie: pcie@0x01000000 { 141 pcie: pcie@0x01000000 {
142 compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; 142 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
143 reg = <0x01ffc000 0x4000>; /* DBI */ 143 reg = <0x01ffc000 0x4000>; /* DBI */
144 #address-cells = <3>; 144 #address-cells = <3>;
145 #size-cells = <2>; 145 #size-cells = <2>;
146 device_type = "pci"; 146 device_type = "pci";
147 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ 147 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
148 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 148 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
149 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 149 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
150 num-lanes = <1>; 150 num-lanes = <1>;
151 interrupts = <0 123 0x04>; 151 interrupts = <0 123 0x04>;
152 clocks = <&clks 189>, <&clks 187>, <&clks 144>, <&clks 212>; 152 clocks = <&clks 189>, <&clks 187>, <&clks 144>, <&clks 212>;
153 clock-names = "pcie_ref_125m", "sata_ref_100m", "pcie_axi", "lvds_gate"; 153 clock-names = "pcie_ref_125m", "sata_ref_100m", "pcie_axi", "lvds_gate";
154 status = "disabled"; 154 status = "disabled";
155 }; 155 };
156 156
157 pmu { 157 pmu {
158 compatible = "arm,cortex-a9-pmu"; 158 compatible = "arm,cortex-a9-pmu";
159 interrupts = <0 94 0x04>; 159 interrupts = <0 94 0x04>;
160 }; 160 };
161 161
162 aips-bus@02000000 { /* AIPS1 */ 162 aips-bus@02000000 { /* AIPS1 */
163 compatible = "fsl,aips-bus", "simple-bus"; 163 compatible = "fsl,aips-bus", "simple-bus";
164 #address-cells = <1>; 164 #address-cells = <1>;
165 #size-cells = <1>; 165 #size-cells = <1>;
166 reg = <0x02000000 0x100000>; 166 reg = <0x02000000 0x100000>;
167 ranges; 167 ranges;
168 168
169 spba-bus@02000000 { 169 spba-bus@02000000 {
170 compatible = "fsl,spba-bus", "simple-bus"; 170 compatible = "fsl,spba-bus", "simple-bus";
171 #address-cells = <1>; 171 #address-cells = <1>;
172 #size-cells = <1>; 172 #size-cells = <1>;
173 reg = <0x02000000 0x40000>; 173 reg = <0x02000000 0x40000>;
174 ranges; 174 ranges;
175 175
176 spdif: spdif@02004000 { 176 spdif: spdif@02004000 {
177 compatible = "fsl,imx6q-spdif", 177 compatible = "fsl,imx6q-spdif",
178 "fsl,imx35-spdif"; 178 "fsl,imx35-spdif";
179 reg = <0x02004000 0x4000>; 179 reg = <0x02004000 0x4000>;
180 interrupts = <0 52 0x04>; 180 interrupts = <0 52 0x04>;
181 dmas = <&sdma 14 18 0>, 181 dmas = <&sdma 14 18 0>,
182 <&sdma 15 18 0>; 182 <&sdma 15 18 0>;
183 dma-names = "rx", "tx"; 183 dma-names = "rx", "tx";
184 clocks = <&clks 197>, <&clks 3>, 184 clocks = <&clks 197>, <&clks 3>,
185 <&clks 197>, <&clks 0>, 185 <&clks 197>, <&clks 0>,
186 <&clks 0>, <&clks 0>, 186 <&clks 0>, <&clks 0>,
187 <&clks 62>, <&clks 0>, 187 <&clks 62>, <&clks 0>,
188 <&clks 0>, <&clks 156>; 188 <&clks 0>, <&clks 156>;
189 clock-names = "core", "rxtx0", 189 clock-names = "core", "rxtx0",
190 "rxtx1", "rxtx2", 190 "rxtx1", "rxtx2",
191 "rxtx3", "rxtx4", 191 "rxtx3", "rxtx4",
192 "rxtx5", "rxtx6", 192 "rxtx5", "rxtx6",
193 "rxtx7", "dma"; 193 "rxtx7", "dma";
194 status = "disabled"; 194 status = "disabled";
195 }; 195 };
196 196
197 ecspi1: ecspi@02008000 { 197 ecspi1: ecspi@02008000 {
198 #address-cells = <1>; 198 #address-cells = <1>;
199 #size-cells = <0>; 199 #size-cells = <0>;
200 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 200 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
201 reg = <0x02008000 0x4000>; 201 reg = <0x02008000 0x4000>;
202 interrupts = <0 31 0x04>; 202 interrupts = <0 31 0x04>;
203 clocks = <&clks 112>, <&clks 112>; 203 clocks = <&clks 112>, <&clks 112>;
204 clock-names = "ipg", "per"; 204 clock-names = "ipg", "per";
205 status = "disabled"; 205 status = "disabled";
206 }; 206 };
207 207
208 ecspi2: ecspi@0200c000 { 208 ecspi2: ecspi@0200c000 {
209 #address-cells = <1>; 209 #address-cells = <1>;
210 #size-cells = <0>; 210 #size-cells = <0>;
211 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 211 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
212 reg = <0x0200c000 0x4000>; 212 reg = <0x0200c000 0x4000>;
213 interrupts = <0 32 0x04>; 213 interrupts = <0 32 0x04>;
214 clocks = <&clks 113>, <&clks 113>; 214 clocks = <&clks 113>, <&clks 113>;
215 clock-names = "ipg", "per"; 215 clock-names = "ipg", "per";
216 status = "disabled"; 216 status = "disabled";
217 }; 217 };
218 218
219 ecspi3: ecspi@02010000 { 219 ecspi3: ecspi@02010000 {
220 #address-cells = <1>; 220 #address-cells = <1>;
221 #size-cells = <0>; 221 #size-cells = <0>;
222 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 222 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
223 reg = <0x02010000 0x4000>; 223 reg = <0x02010000 0x4000>;
224 interrupts = <0 33 0x04>; 224 interrupts = <0 33 0x04>;
225 clocks = <&clks 114>, <&clks 114>; 225 clocks = <&clks 114>, <&clks 114>;
226 clock-names = "ipg", "per"; 226 clock-names = "ipg", "per";
227 status = "disabled"; 227 status = "disabled";
228 }; 228 };
229 229
230 ecspi4: ecspi@02014000 { 230 ecspi4: ecspi@02014000 {
231 #address-cells = <1>; 231 #address-cells = <1>;
232 #size-cells = <0>; 232 #size-cells = <0>;
233 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 233 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
234 reg = <0x02014000 0x4000>; 234 reg = <0x02014000 0x4000>;
235 interrupts = <0 34 0x04>; 235 interrupts = <0 34 0x04>;
236 clocks = <&clks 115>, <&clks 115>; 236 clocks = <&clks 115>, <&clks 115>;
237 clock-names = "ipg", "per"; 237 clock-names = "ipg", "per";
238 status = "disabled"; 238 status = "disabled";
239 }; 239 };
240 240
241 uart1: serial@02020000 { 241 uart1: serial@02020000 {
242 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 242 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
243 reg = <0x02020000 0x4000>; 243 reg = <0x02020000 0x4000>;
244 interrupts = <0 26 0x04>; 244 interrupts = <0 26 0x04>;
245 clocks = <&clks 160>, <&clks 161>; 245 clocks = <&clks 160>, <&clks 161>;
246 clock-names = "ipg", "per"; 246 clock-names = "ipg", "per";
247 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 247 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
248 dma-names = "rx", "tx"; 248 dma-names = "rx", "tx";
249 status = "disabled"; 249 status = "disabled";
250 }; 250 };
251 251
252 esai: esai@02024000 { 252 esai: esai@02024000 {
253 compatible = "fsl,imx35-esai"; 253 compatible = "fsl,imx35-esai";
254 reg = <0x02024000 0x4000>; 254 reg = <0x02024000 0x4000>;
255 interrupts = <0 51 0x04>; 255 interrupts = <0 51 0x04>;
256 clocks = <&clks 228>, <&clks 229>, <&clks 118>, <&clks 228>, <&clks 156>; 256 clocks = <&clks 228>, <&clks 229>, <&clks 118>, <&clks 228>, <&clks 156>;
257 clock-names = "core", "mem", "extal", "fsys", "dma"; 257 clock-names = "core", "mem", "extal", "fsys", "dma";
258 fsl,esai-dma-events = <24 23>; 258 fsl,esai-dma-events = <24 23>;
259 fsl,flags = <1>; 259 fsl,flags = <1>;
260 status = "disabled"; 260 status = "disabled";
261 }; 261 };
262 262
263 ssi1: ssi@02028000 { 263 ssi1: ssi@02028000 {
264 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 264 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
265 reg = <0x02028000 0x4000>; 265 reg = <0x02028000 0x4000>;
266 interrupts = <0 46 0x04>; 266 interrupts = <0 46 0x04>;
267 clocks = <&clks 178>, <&clks 157>; 267 clocks = <&clks 178>, <&clks 157>;
268 clock-names = "ipg", "baud"; 268 clock-names = "ipg", "baud";
269 dmas = <&sdma 37 1 0>, 269 dmas = <&sdma 37 1 0>,
270 <&sdma 38 1 0>; 270 <&sdma 38 1 0>;
271 dma-names = "rx", "tx"; 271 dma-names = "rx", "tx";
272 status = "disabled"; 272 status = "disabled";
273 }; 273 };
274 274
275 ssi2: ssi@0202c000 { 275 ssi2: ssi@0202c000 {
276 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 276 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
277 reg = <0x0202c000 0x4000>; 277 reg = <0x0202c000 0x4000>;
278 interrupts = <0 47 0x04>; 278 interrupts = <0 47 0x04>;
279 clocks = <&clks 179>, <&clks 158>; 279 clocks = <&clks 179>, <&clks 158>;
280 clock-names = "ipg", "baud"; 280 clock-names = "ipg", "baud";
281 dmas = <&sdma 41 1 0>, 281 dmas = <&sdma 41 1 0>,
282 <&sdma 42 1 0>; 282 <&sdma 42 1 0>;
283 dma-names = "rx", "tx"; 283 dma-names = "rx", "tx";
284 status = "disabled"; 284 status = "disabled";
285 }; 285 };
286 286
287 ssi3: ssi@02030000 { 287 ssi3: ssi@02030000 {
288 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; 288 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
289 reg = <0x02030000 0x4000>; 289 reg = <0x02030000 0x4000>;
290 interrupts = <0 48 0x04>; 290 interrupts = <0 48 0x04>;
291 clocks = <&clks 180>, <&clks 159>; 291 clocks = <&clks 180>, <&clks 159>;
292 clock-names = "ipg", "baud"; 292 clock-names = "ipg", "baud";
293 dmas = <&sdma 45 1 0>, 293 dmas = <&sdma 45 1 0>,
294 <&sdma 46 1 0>; 294 <&sdma 46 1 0>;
295 dma-names = "rx", "tx"; 295 dma-names = "rx", "tx";
296 status = "disabled"; 296 status = "disabled";
297 }; 297 };
298 298
299 asrc: asrc@02034000 { 299 asrc: asrc@02034000 {
300 compatible = "fsl,imx53-asrc"; 300 compatible = "fsl,imx53-asrc";
301 reg = <0x02034000 0x4000>; 301 reg = <0x02034000 0x4000>;
302 interrupts = <0 50 0x04>; 302 interrupts = <0 50 0x04>;
303 clocks = <&clks 227>, <&clks 226>, 303 clocks = <&clks 227>, <&clks 226>,
304 <&clks 225>, <&clks 156>; 304 <&clks 225>, <&clks 156>;
305 clock-names = "mem", "ipg", "asrck", "dma"; 305 clock-names = "mem", "ipg", "asrck", "dma";
306 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>, 306 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>,
307 <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>; 307 <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>;
308 dma-names = "rxa", "rxb", "rxc", 308 dma-names = "rxa", "rxb", "rxc",
309 "txa", "txb", "txc"; 309 "txa", "txb", "txc";
310 status = "okay"; 310 status = "okay";
311 }; 311 };
312 312
313 asrc_p2p: asrc_p2p { 313 asrc_p2p: asrc_p2p {
314 compatible = "fsl,imx6q-asrc-p2p"; 314 compatible = "fsl,imx6q-asrc-p2p";
315 fsl,p2p-rate = <48000>; 315 fsl,p2p-rate = <48000>;
316 fsl,p2p-width = <16>; 316 fsl,p2p-width = <16>;
317 fsl,asrc-dma-rx-events = <17 18 19>; 317 fsl,asrc-dma-rx-events = <17 18 19>;
318 fsl,asrc-dma-tx-events = <20 21 22>; 318 fsl,asrc-dma-tx-events = <20 21 22>;
319 status = "okay"; 319 status = "okay";
320 }; 320 };
321 321
322 spba@0203c000 { 322 spba@0203c000 {
323 reg = <0x0203c000 0x4000>; 323 reg = <0x0203c000 0x4000>;
324 }; 324 };
325 }; 325 };
326 326
327 vpu: vpu@02040000 { 327 vpu: vpu@02040000 {
328 compatible = "fsl,imx6-vpu"; 328 compatible = "fsl,imx6-vpu";
329 reg = <0x02040000 0x3c000>; 329 reg = <0x02040000 0x3c000>;
330 reg-names = "vpu_regs"; 330 reg-names = "vpu_regs";
331 interrupts = <0 3 0x01>, <0 12 0x04>; 331 interrupts = <0 3 0x01>, <0 12 0x04>;
332 interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; 332 interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
333 clocks = <&clks 168>, <&clks 140>, <&clks 142>; 333 clocks = <&clks 168>, <&clks 140>, <&clks 142>;
334 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; 334 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
335 iramsize = <0x21000>; 335 iramsize = <0x21000>;
336 iram = <&ocram>; 336 iram = <&ocram>;
337 resets = <&src 1>; 337 resets = <&src 1>;
338 pu-supply = <&reg_pu>; 338 pu-supply = <&reg_pu>;
339 status = "disabled"; 339 status = "disabled";
340 }; 340 };
341 341
342 aipstz@0207c000 { /* AIPSTZ1 */ 342 aipstz@0207c000 { /* AIPSTZ1 */
343 reg = <0x0207c000 0x4000>; 343 reg = <0x0207c000 0x4000>;
344 }; 344 };
345 345
346 pwm1: pwm@02080000 { 346 pwm1: pwm@02080000 {
347 #pwm-cells = <2>; 347 #pwm-cells = <2>;
348 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 348 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
349 reg = <0x02080000 0x4000>; 349 reg = <0x02080000 0x4000>;
350 interrupts = <0 83 0x04>; 350 interrupts = <0 83 0x04>;
351 clocks = <&clks 62>, <&clks 145>; 351 clocks = <&clks 62>, <&clks 145>;
352 clock-names = "ipg", "per"; 352 clock-names = "ipg", "per";
353 }; 353 };
354 354
355 pwm2: pwm@02084000 { 355 pwm2: pwm@02084000 {
356 #pwm-cells = <2>; 356 #pwm-cells = <2>;
357 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 357 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
358 reg = <0x02084000 0x4000>; 358 reg = <0x02084000 0x4000>;
359 interrupts = <0 84 0x04>; 359 interrupts = <0 84 0x04>;
360 clocks = <&clks 62>, <&clks 146>; 360 clocks = <&clks 62>, <&clks 146>;
361 clock-names = "ipg", "per"; 361 clock-names = "ipg", "per";
362 }; 362 };
363 363
364 pwm3: pwm@02088000 { 364 pwm3: pwm@02088000 {
365 #pwm-cells = <2>; 365 #pwm-cells = <2>;
366 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 366 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
367 reg = <0x02088000 0x4000>; 367 reg = <0x02088000 0x4000>;
368 interrupts = <0 85 0x04>; 368 interrupts = <0 85 0x04>;
369 clocks = <&clks 62>, <&clks 147>; 369 clocks = <&clks 62>, <&clks 147>;
370 clock-names = "ipg", "per"; 370 clock-names = "ipg", "per";
371 }; 371 };
372 372
373 pwm4: pwm@0208c000 { 373 pwm4: pwm@0208c000 {
374 #pwm-cells = <2>; 374 #pwm-cells = <2>;
375 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 375 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
376 reg = <0x0208c000 0x4000>; 376 reg = <0x0208c000 0x4000>;
377 interrupts = <0 86 0x04>; 377 interrupts = <0 86 0x04>;
378 clocks = <&clks 62>, <&clks 148>; 378 clocks = <&clks 62>, <&clks 148>;
379 clock-names = "ipg", "per"; 379 clock-names = "ipg", "per";
380 }; 380 };
381 381
382 flexcan1: can@02090000 { 382 flexcan1: can@02090000 {
383 compatible = "fsl,imx6q-flexcan"; 383 compatible = "fsl,imx6q-flexcan";
384 reg = <0x02090000 0x4000>; 384 reg = <0x02090000 0x4000>;
385 interrupts = <0 110 0x04>; 385 interrupts = <0 110 0x04>;
386 clocks = <&clks 108>, <&clks 109>; 386 clocks = <&clks 108>, <&clks 109>;
387 clock-names = "ipg", "per"; 387 clock-names = "ipg", "per";
388 stop-mode = <&gpr 0x34 28 0x10 17>; 388 stop-mode = <&gpr 0x34 28 0x10 17>;
389 status = "disabled"; 389 status = "disabled";
390 }; 390 };
391 391
392 flexcan2: can@02094000 { 392 flexcan2: can@02094000 {
393 compatible = "fsl,imx6q-flexcan"; 393 compatible = "fsl,imx6q-flexcan";
394 reg = <0x02094000 0x4000>; 394 reg = <0x02094000 0x4000>;
395 interrupts = <0 111 0x04>; 395 interrupts = <0 111 0x04>;
396 clocks = <&clks 110>, <&clks 111>; 396 clocks = <&clks 110>, <&clks 111>;
397 clock-names = "ipg", "per"; 397 clock-names = "ipg", "per";
398 stop-mode = <&gpr 0x34 29 0x10 18>; 398 stop-mode = <&gpr 0x34 29 0x10 18>;
399 status = "disabled"; 399 status = "disabled";
400 }; 400 };
401 401
402 gpt: gpt@02098000 { 402 gpt: gpt@02098000 {
403 compatible = "fsl,imx6q-gpt"; 403 compatible = "fsl,imx6q-gpt";
404 reg = <0x02098000 0x4000>; 404 reg = <0x02098000 0x4000>;
405 interrupts = <0 55 0x04>; 405 interrupts = <0 55 0x04>;
406 clocks = <&clks 119>, <&clks 120>; 406 clocks = <&clks 119>, <&clks 120>;
407 clock-names = "ipg", "per"; 407 clock-names = "ipg", "per";
408 }; 408 };
409 409
410 gpio1: gpio@0209c000 { 410 gpio1: gpio@0209c000 {
411 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 411 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
412 reg = <0x0209c000 0x4000>; 412 reg = <0x0209c000 0x4000>;
413 interrupts = <0 66 0x04 0 67 0x04>; 413 interrupts = <0 66 0x04 0 67 0x04>;
414 gpio-controller; 414 gpio-controller;
415 #gpio-cells = <2>; 415 #gpio-cells = <2>;
416 interrupt-controller; 416 interrupt-controller;
417 #interrupt-cells = <2>; 417 #interrupt-cells = <2>;
418 }; 418 };
419 419
420 gpio2: gpio@020a0000 { 420 gpio2: gpio@020a0000 {
421 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 421 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
422 reg = <0x020a0000 0x4000>; 422 reg = <0x020a0000 0x4000>;
423 interrupts = <0 68 0x04 0 69 0x04>; 423 interrupts = <0 68 0x04 0 69 0x04>;
424 gpio-controller; 424 gpio-controller;
425 #gpio-cells = <2>; 425 #gpio-cells = <2>;
426 interrupt-controller; 426 interrupt-controller;
427 #interrupt-cells = <2>; 427 #interrupt-cells = <2>;
428 }; 428 };
429 429
430 gpio3: gpio@020a4000 { 430 gpio3: gpio@020a4000 {
431 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 431 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
432 reg = <0x020a4000 0x4000>; 432 reg = <0x020a4000 0x4000>;
433 interrupts = <0 70 0x04 0 71 0x04>; 433 interrupts = <0 70 0x04 0 71 0x04>;
434 gpio-controller; 434 gpio-controller;
435 #gpio-cells = <2>; 435 #gpio-cells = <2>;
436 interrupt-controller; 436 interrupt-controller;
437 #interrupt-cells = <2>; 437 #interrupt-cells = <2>;
438 }; 438 };
439 439
440 gpio4: gpio@020a8000 { 440 gpio4: gpio@020a8000 {
441 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 441 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
442 reg = <0x020a8000 0x4000>; 442 reg = <0x020a8000 0x4000>;
443 interrupts = <0 72 0x04 0 73 0x04>; 443 interrupts = <0 72 0x04 0 73 0x04>;
444 gpio-controller; 444 gpio-controller;
445 #gpio-cells = <2>; 445 #gpio-cells = <2>;
446 interrupt-controller; 446 interrupt-controller;
447 #interrupt-cells = <2>; 447 #interrupt-cells = <2>;
448 }; 448 };
449 449
450 gpio5: gpio@020ac000 { 450 gpio5: gpio@020ac000 {
451 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 451 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
452 reg = <0x020ac000 0x4000>; 452 reg = <0x020ac000 0x4000>;
453 interrupts = <0 74 0x04 0 75 0x04>; 453 interrupts = <0 74 0x04 0 75 0x04>;
454 gpio-controller; 454 gpio-controller;
455 #gpio-cells = <2>; 455 #gpio-cells = <2>;
456 interrupt-controller; 456 interrupt-controller;
457 #interrupt-cells = <2>; 457 #interrupt-cells = <2>;
458 }; 458 };
459 459
460 gpio6: gpio@020b0000 { 460 gpio6: gpio@020b0000 {
461 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 461 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
462 reg = <0x020b0000 0x4000>; 462 reg = <0x020b0000 0x4000>;
463 interrupts = <0 76 0x04 0 77 0x04>; 463 interrupts = <0 76 0x04 0 77 0x04>;
464 gpio-controller; 464 gpio-controller;
465 #gpio-cells = <2>; 465 #gpio-cells = <2>;
466 interrupt-controller; 466 interrupt-controller;
467 #interrupt-cells = <2>; 467 #interrupt-cells = <2>;
468 }; 468 };
469 469
470 gpio7: gpio@020b4000 { 470 gpio7: gpio@020b4000 {
471 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 471 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
472 reg = <0x020b4000 0x4000>; 472 reg = <0x020b4000 0x4000>;
473 interrupts = <0 78 0x04 0 79 0x04>; 473 interrupts = <0 78 0x04 0 79 0x04>;
474 gpio-controller; 474 gpio-controller;
475 #gpio-cells = <2>; 475 #gpio-cells = <2>;
476 interrupt-controller; 476 interrupt-controller;
477 #interrupt-cells = <2>; 477 #interrupt-cells = <2>;
478 }; 478 };
479 479
480 kpp: kpp@020b8000 { 480 kpp: kpp@020b8000 {
481 reg = <0x020b8000 0x4000>; 481 reg = <0x020b8000 0x4000>;
482 interrupts = <0 82 0x04>; 482 interrupts = <0 82 0x04>;
483 }; 483 };
484 484
485 wdog1: wdog@020bc000 { 485 wdog1: wdog@020bc000 {
486 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 486 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
487 reg = <0x020bc000 0x4000>; 487 reg = <0x020bc000 0x4000>;
488 interrupts = <0 80 0x04>; 488 interrupts = <0 80 0x04>;
489 clocks = <&clks 0>; 489 clocks = <&clks 0>;
490 }; 490 };
491 491
492 wdog2: wdog@020c0000 { 492 wdog2: wdog@020c0000 {
493 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 493 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
494 reg = <0x020c0000 0x4000>; 494 reg = <0x020c0000 0x4000>;
495 interrupts = <0 81 0x04>; 495 interrupts = <0 81 0x04>;
496 clocks = <&clks 0>; 496 clocks = <&clks 0>;
497 status = "disabled"; 497 status = "disabled";
498 }; 498 };
499 499
500 clks: ccm@020c4000 { 500 clks: ccm@020c4000 {
501 compatible = "fsl,imx6q-ccm"; 501 compatible = "fsl,imx6q-ccm";
502 reg = <0x020c4000 0x4000>; 502 reg = <0x020c4000 0x4000>;
503 interrupts = <0 87 0x04 0 88 0x04>; 503 interrupts = <0 87 0x04 0 88 0x04>;
504 #clock-cells = <1>; 504 #clock-cells = <1>;
505 }; 505 };
506 506
507 anatop: anatop@020c8000 { 507 anatop: anatop@020c8000 {
508 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; 508 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
509 reg = <0x020c8000 0x1000>; 509 reg = <0x020c8000 0x1000>;
510 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; 510 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
511 511
512 regulator-1p1@110 { 512 regulator-1p1@110 {
513 compatible = "fsl,anatop-regulator"; 513 compatible = "fsl,anatop-regulator";
514 regulator-name = "vdd1p1"; 514 regulator-name = "vdd1p1";
515 regulator-min-microvolt = <800000>; 515 regulator-min-microvolt = <800000>;
516 regulator-max-microvolt = <1375000>; 516 regulator-max-microvolt = <1375000>;
517 regulator-always-on; 517 regulator-always-on;
518 anatop-reg-offset = <0x110>; 518 anatop-reg-offset = <0x110>;
519 anatop-vol-bit-shift = <8>; 519 anatop-vol-bit-shift = <8>;
520 anatop-vol-bit-width = <5>; 520 anatop-vol-bit-width = <5>;
521 anatop-min-bit-val = <4>; 521 anatop-min-bit-val = <4>;
522 anatop-min-voltage = <800000>; 522 anatop-min-voltage = <800000>;
523 anatop-max-voltage = <1375000>; 523 anatop-max-voltage = <1375000>;
524 }; 524 };
525 525
526 regulator-3p0@120 { 526 regulator-3p0@120 {
527 compatible = "fsl,anatop-regulator"; 527 compatible = "fsl,anatop-regulator";
528 regulator-name = "vdd3p0"; 528 regulator-name = "vdd3p0";
529 regulator-min-microvolt = <2800000>; 529 regulator-min-microvolt = <2800000>;
530 regulator-max-microvolt = <3150000>; 530 regulator-max-microvolt = <3150000>;
531 regulator-always-on; 531 regulator-always-on;
532 anatop-reg-offset = <0x120>; 532 anatop-reg-offset = <0x120>;
533 anatop-vol-bit-shift = <8>; 533 anatop-vol-bit-shift = <8>;
534 anatop-vol-bit-width = <5>; 534 anatop-vol-bit-width = <5>;
535 anatop-min-bit-val = <0>; 535 anatop-min-bit-val = <0>;
536 anatop-min-voltage = <2625000>; 536 anatop-min-voltage = <2625000>;
537 anatop-max-voltage = <3400000>; 537 anatop-max-voltage = <3400000>;
538 }; 538 };
539 539
540 regulator-2p5@130 { 540 regulator-2p5@130 {
541 compatible = "fsl,anatop-regulator"; 541 compatible = "fsl,anatop-regulator";
542 regulator-name = "vdd2p5"; 542 regulator-name = "vdd2p5";
543 regulator-min-microvolt = <2000000>; 543 regulator-min-microvolt = <2000000>;
544 regulator-max-microvolt = <2750000>; 544 regulator-max-microvolt = <2750000>;
545 regulator-always-on; 545 regulator-always-on;
546 anatop-reg-offset = <0x130>; 546 anatop-reg-offset = <0x130>;
547 anatop-vol-bit-shift = <8>; 547 anatop-vol-bit-shift = <8>;
548 anatop-vol-bit-width = <5>; 548 anatop-vol-bit-width = <5>;
549 anatop-min-bit-val = <0>; 549 anatop-min-bit-val = <0>;
550 anatop-min-voltage = <2000000>; 550 anatop-min-voltage = <2000000>;
551 anatop-max-voltage = <2750000>; 551 anatop-max-voltage = <2750000>;
552 }; 552 };
553 553
554 reg_arm: regulator-vddcore@140 { 554 reg_arm: regulator-vddcore@140 {
555 compatible = "fsl,anatop-regulator"; 555 compatible = "fsl,anatop-regulator";
556 regulator-name = "cpu"; 556 regulator-name = "cpu";
557 regulator-min-microvolt = <725000>; 557 regulator-min-microvolt = <725000>;
558 regulator-max-microvolt = <1450000>; 558 regulator-max-microvolt = <1450000>;
559 regulator-always-on; 559 regulator-always-on;
560 anatop-reg-offset = <0x140>; 560 anatop-reg-offset = <0x140>;
561 anatop-vol-bit-shift = <0>; 561 anatop-vol-bit-shift = <0>;
562 anatop-vol-bit-width = <5>; 562 anatop-vol-bit-width = <5>;
563 anatop-delay-reg-offset = <0x170>; 563 anatop-delay-reg-offset = <0x170>;
564 anatop-delay-bit-shift = <24>; 564 anatop-delay-bit-shift = <24>;
565 anatop-delay-bit-width = <2>; 565 anatop-delay-bit-width = <2>;
566 anatop-min-bit-val = <1>; 566 anatop-min-bit-val = <1>;
567 anatop-min-voltage = <725000>; 567 anatop-min-voltage = <725000>;
568 anatop-max-voltage = <1450000>; 568 anatop-max-voltage = <1450000>;
569 }; 569 };
570 570
571 reg_pu: regulator-vddpu@140 { 571 reg_pu: regulator-vddpu@140 {
572 compatible = "fsl,anatop-regulator"; 572 compatible = "fsl,anatop-regulator";
573 regulator-name = "vddpu"; 573 regulator-name = "vddpu";
574 regulator-min-microvolt = <725000>; 574 regulator-min-microvolt = <725000>;
575 regulator-max-microvolt = <1450000>; 575 regulator-max-microvolt = <1450000>;
576 anatop-reg-offset = <0x140>; 576 anatop-reg-offset = <0x140>;
577 anatop-vol-bit-shift = <9>; 577 anatop-vol-bit-shift = <9>;
578 anatop-vol-bit-width = <5>; 578 anatop-vol-bit-width = <5>;
579 anatop-delay-reg-offset = <0x170>; 579 anatop-delay-reg-offset = <0x170>;
580 anatop-delay-bit-shift = <26>; 580 anatop-delay-bit-shift = <26>;
581 anatop-delay-bit-width = <2>; 581 anatop-delay-bit-width = <2>;
582 anatop-min-bit-val = <1>; 582 anatop-min-bit-val = <1>;
583 anatop-min-voltage = <725000>; 583 anatop-min-voltage = <725000>;
584 anatop-max-voltage = <1450000>; 584 anatop-max-voltage = <1450000>;
585 }; 585 };
586 586
587 reg_soc: regulator-vddsoc@140 { 587 reg_soc: regulator-vddsoc@140 {
588 compatible = "fsl,anatop-regulator"; 588 compatible = "fsl,anatop-regulator";
589 regulator-name = "vddsoc"; 589 regulator-name = "vddsoc";
590 regulator-min-microvolt = <725000>; 590 regulator-min-microvolt = <725000>;
591 regulator-max-microvolt = <1450000>; 591 regulator-max-microvolt = <1450000>;
592 regulator-always-on; 592 regulator-always-on;
593 anatop-reg-offset = <0x140>; 593 anatop-reg-offset = <0x140>;
594 anatop-vol-bit-shift = <18>; 594 anatop-vol-bit-shift = <18>;
595 anatop-vol-bit-width = <5>; 595 anatop-vol-bit-width = <5>;
596 anatop-delay-reg-offset = <0x170>; 596 anatop-delay-reg-offset = <0x170>;
597 anatop-delay-bit-shift = <28>; 597 anatop-delay-bit-shift = <28>;
598 anatop-delay-bit-width = <2>; 598 anatop-delay-bit-width = <2>;
599 anatop-min-bit-val = <1>; 599 anatop-min-bit-val = <1>;
600 anatop-min-voltage = <725000>; 600 anatop-min-voltage = <725000>;
601 anatop-max-voltage = <1450000>; 601 anatop-max-voltage = <1450000>;
602 }; 602 };
603 }; 603 };
604 604
605 tempmon: tempmon { 605 tempmon: tempmon {
606 compatible = "fsl,imx6q-tempmon"; 606 compatible = "fsl,imx6q-tempmon";
607 interrupts = <0 49 0x04>; 607 interrupts = <0 49 0x04>;
608 fsl,tempmon = <&anatop>; 608 fsl,tempmon = <&anatop>;
609 fsl,tempmon-data = <&ocotp>; 609 fsl,tempmon-data = <&ocotp>;
610 clocks = <&clks 172>; 610 clocks = <&clks 172>;
611 }; 611 };
612 612
613 usbphy1: usbphy@020c9000 { 613 usbphy1: usbphy@020c9000 {
614 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 614 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
615 reg = <0x020c9000 0x1000>; 615 reg = <0x020c9000 0x1000>;
616 interrupts = <0 44 0x04>; 616 interrupts = <0 44 0x04>;
617 clocks = <&clks 182>; 617 clocks = <&clks 182>;
618 fsl,anatop = <&anatop>; 618 fsl,anatop = <&anatop>;
619 }; 619 };
620 620
621 usbphy2: usbphy@020ca000 { 621 usbphy2: usbphy@020ca000 {
622 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 622 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
623 reg = <0x020ca000 0x1000>; 623 reg = <0x020ca000 0x1000>;
624 interrupts = <0 45 0x04>; 624 interrupts = <0 45 0x04>;
625 clocks = <&clks 183>; 625 clocks = <&clks 183>;
626 fsl,anatop = <&anatop>; 626 fsl,anatop = <&anatop>;
627 }; 627 };
628 628
629 usbphy_nop1: usbphy_nop1 { 629 usbphy_nop1: usbphy_nop1 {
630 compatible = "usb-nop-xceiv"; 630 compatible = "usb-nop-xceiv";
631 clocks = <&clks 182>; 631 clocks = <&clks 182>;
632 clock-names = "main_clk"; 632 clock-names = "main_clk";
633 }; 633 };
634 634
635 usbphy_nop2: usbphy_nop2 { 635 usbphy_nop2: usbphy_nop2 {
636 compatible = "usb-nop-xceiv"; 636 compatible = "usb-nop-xceiv";
637 clocks = <&clks 182>; 637 clocks = <&clks 182>;
638 clock-names = "main_clk"; 638 clock-names = "main_clk";
639 }; 639 };
640 640
641 caam_snvs: caam-snvs@020cc000 { 641 caam_snvs: caam-snvs@020cc000 {
642 compatible = "fsl,imx6q-caam-snvs"; 642 compatible = "fsl,imx6q-caam-snvs";
643 reg = <0x020cc000 0x4000>; 643 reg = <0x020cc000 0x4000>;
644 }; 644 };
645 645
646 snvs@020cc000 { 646 snvs@020cc000 {
647 compatible = "fsl,sec-v4.0-mon", "simple-bus"; 647 compatible = "fsl,sec-v4.0-mon", "simple-bus";
648 #address-cells = <1>; 648 #address-cells = <1>;
649 #size-cells = <1>; 649 #size-cells = <1>;
650 ranges = <0 0x020cc000 0x4000>; 650 ranges = <0 0x020cc000 0x4000>;
651 651
652 snvs-rtc-lp@34 { 652 snvs-rtc-lp@34 {
653 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 653 compatible = "fsl,sec-v4.0-mon-rtc-lp";
654 reg = <0x34 0x58>; 654 reg = <0x34 0x58>;
655 interrupts = <0 19 0x04 0 20 0x04>; 655 interrupts = <0 19 0x04 0 20 0x04>;
656 }; 656 };
657 }; 657 };
658 658
659 epit1: epit@020d0000 { /* EPIT1 */ 659 epit1: epit@020d0000 { /* EPIT1 */
660 reg = <0x020d0000 0x4000>; 660 reg = <0x020d0000 0x4000>;
661 interrupts = <0 56 0x04>; 661 interrupts = <0 56 0x04>;
662 }; 662 };
663 663
664 epit2: epit@020d4000 { /* EPIT2 */ 664 epit2: epit@020d4000 { /* EPIT2 */
665 reg = <0x020d4000 0x4000>; 665 reg = <0x020d4000 0x4000>;
666 interrupts = <0 57 0x04>; 666 interrupts = <0 57 0x04>;
667 }; 667 };
668 668
669 src: src@020d8000 { 669 src: src@020d8000 {
670 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 670 compatible = "fsl,imx6q-src", "fsl,imx51-src";
671 reg = <0x020d8000 0x4000>; 671 reg = <0x020d8000 0x4000>;
672 interrupts = <0 91 0x04 0 96 0x04>; 672 interrupts = <0 91 0x04 0 96 0x04>;
673 #reset-cells = <1>; 673 #reset-cells = <1>;
674 }; 674 };
675 675
676 gpc: gpc@020dc000 { 676 gpc: gpc@020dc000 {
677 compatible = "fsl,imx6q-gpc"; 677 compatible = "fsl,imx6q-gpc";
678 reg = <0x020dc000 0x4000>; 678 reg = <0x020dc000 0x4000>;
679 interrupts = <0 89 0x04 0 90 0x04>; 679 interrupts = <0 89 0x04 0 90 0x04>;
680 clocks = <&clks 122>, <&clks 74>, <&clks 121>, 680 clocks = <&clks 122>, <&clks 74>, <&clks 121>,
681 <&clks 26>, <&clks 143>, <&clks 168>, <&clks 62>; 681 <&clks 26>, <&clks 143>, <&clks 168>, <&clks 62>;
682 clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core", 682 clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core",
683 "gpu2d_axi", "openvg_axi", "vpu_axi", "ipg"; 683 "gpu2d_axi", "openvg_axi", "vpu_axi", "ipg";
684 pu-supply = <&reg_pu>; 684 pu-supply = <&reg_pu>;
685 }; 685 };
686 686
687 gpr: iomuxc-gpr@020e0000 { 687 gpr: iomuxc-gpr@020e0000 {
688 compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; 688 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
689 reg = <0x020e0000 0x38>; 689 reg = <0x020e0000 0x38>;
690 }; 690 };
691 691
692 iomuxc: iomuxc@020e0000 { 692 iomuxc: iomuxc@020e0000 {
693 reg = <0x020e0000 0x4000>; 693 reg = <0x020e0000 0x4000>;
694 }; 694 };
695 695
696 ldb: ldb@020e0008 { 696 ldb: ldb@020e0008 {
697 #address-cells = <1>; 697 #address-cells = <1>;
698 #size-cells = <0>; 698 #size-cells = <0>;
699 gpr = <&gpr>; 699 gpr = <&gpr>;
700 status = "disabled"; 700 status = "disabled";
701 701
702 lvds-channel@0 { 702 lvds-channel@0 {
703 reg = <0>; 703 reg = <0>;
704 status = "disabled"; 704 status = "disabled";
705 }; 705 };
706 706
707 lvds-channel@1 { 707 lvds-channel@1 {
708 reg = <1>; 708 reg = <1>;
709 status = "disabled"; 709 status = "disabled";
710 }; 710 };
711 }; 711 };
712 712
713 dcic1: dcic@020e4000 { 713 dcic1: dcic@020e4000 {
714 compatible = "fsl,imx6q-dcic"; 714 compatible = "fsl,imx6q-dcic";
715 reg = <0x020e4000 0x4000>; 715 reg = <0x020e4000 0x4000>;
716 interrupts = <0 124 0x04>; 716 interrupts = <0 124 0x04>;
717 clocks = <&clks 231>, <&clks 231>; 717 clocks = <&clks 231>, <&clks 231>;
718 clock-names = "dcic", "disp-axi"; 718 clock-names = "dcic", "disp-axi";
719 gpr = <&gpr>; 719 gpr = <&gpr>;
720 status = "disabled"; 720 status = "disabled";
721 }; 721 };
722 722
723 dcic2: dcic@020e8000 { 723 dcic2: dcic@020e8000 {
724 compatible = "fsl,imx6q-dcic"; 724 compatible = "fsl,imx6q-dcic";
725 reg = <0x020e8000 0x4000>; 725 reg = <0x020e8000 0x4000>;
726 interrupts = <0 125 0x04>; 726 interrupts = <0 125 0x04>;
727 clocks = <&clks 232>, <&clks 232>; 727 clocks = <&clks 232>, <&clks 232>;
728 clock-names = "dcic", "disp-axi"; 728 clock-names = "dcic", "disp-axi";
729 gpr = <&gpr>; 729 gpr = <&gpr>;
730 status = "disabled"; 730 status = "disabled";
731 }; 731 };
732 732
733 sdma: sdma@020ec000 { 733 sdma: sdma@020ec000 {
734 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 734 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
735 reg = <0x020ec000 0x4000>; 735 reg = <0x020ec000 0x4000>;
736 interrupts = <0 2 0x04>; 736 interrupts = <0 2 0x04>;
737 clocks = <&clks 155>, <&clks 155>; 737 clocks = <&clks 155>, <&clks 155>;
738 clock-names = "ipg", "ahb"; 738 clock-names = "ipg", "ahb";
739 #dma-cells = <3>; 739 #dma-cells = <3>;
740 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 740 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
741 }; 741 };
742 }; 742 };
743 743
744 aips-bus@02100000 { /* AIPS2 */ 744 aips-bus@02100000 { /* AIPS2 */
745 compatible = "fsl,aips-bus", "simple-bus"; 745 compatible = "fsl,aips-bus", "simple-bus";
746 #address-cells = <1>; 746 #address-cells = <1>;
747 #size-cells = <1>; 747 #size-cells = <1>;
748 reg = <0x02100000 0x100000>; 748 reg = <0x02100000 0x100000>;
749 ranges; 749 ranges;
750 750
751 crypto: caam@2100000 { 751 crypto: caam@2100000 {
752 compatible = "fsl,sec-v4.0"; 752 compatible = "fsl,sec-v4.0";
753 #address-cells = <1>; 753 #address-cells = <1>;
754 #size-cells = <1>; 754 #size-cells = <1>;
755 reg = <0x2100000 0x40000>; 755 reg = <0x2100000 0x40000>;
756 ranges = <0 0x2100000 0x40000>; 756 ranges = <0 0x2100000 0x40000>;
757 interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */ 757 interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
758 clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>; 758 clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>;
759 clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow"; 759 clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
760 760
761 sec_jr0: jr0@1000 { 761 sec_jr0: jr0@1000 {
762 compatible = "fsl,sec-v4.0-job-ring"; 762 compatible = "fsl,sec-v4.0-job-ring";
763 reg = <0x1000 0x1000>; 763 reg = <0x1000 0x1000>;
764 interrupt-parent = <&intc>; 764 interrupt-parent = <&intc>;
765 interrupts = <0 105 0x4>; 765 interrupts = <0 105 0x4>;
766 }; 766 };
767 767
768 sec_jr1: jr1@2000 { 768 sec_jr1: jr1@2000 {
769 compatible = "fsl,sec-v4.0-job-ring"; 769 compatible = "fsl,sec-v4.0-job-ring";
770 reg = <0x2000 0x1000>; 770 reg = <0x2000 0x1000>;
771 interrupt-parent = <&intc>; 771 interrupt-parent = <&intc>;
772 interrupts = <0 106 0x4>; 772 interrupts = <0 106 0x4>;
773 }; 773 };
774 }; 774 };
775 775
776 aipstz@0217c000 { /* AIPSTZ2 */ 776 aipstz@0217c000 { /* AIPSTZ2 */
777 reg = <0x0217c000 0x4000>; 777 reg = <0x0217c000 0x4000>;
778 }; 778 };
779 779
780 usbotg: usb@02184000 { 780 usbotg: usb@02184000 {
781 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 781 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
782 reg = <0x02184000 0x200>; 782 reg = <0x02184000 0x200>;
783 interrupts = <0 43 0x04>; 783 interrupts = <0 43 0x04>;
784 clocks = <&clks 162>; 784 clocks = <&clks 162>;
785 fsl,usbphy = <&usbphy1>; 785 fsl,usbphy = <&usbphy1>;
786 fsl,usbmisc = <&usbmisc 0>; 786 fsl,usbmisc = <&usbmisc 0>;
787 fsl,anatop = <&anatop>; 787 fsl,anatop = <&anatop>;
788 status = "disabled"; 788 status = "disabled";
789 }; 789 };
790 790
791 usbh1: usb@02184200 { 791 usbh1: usb@02184200 {
792 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 792 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
793 reg = <0x02184200 0x200>; 793 reg = <0x02184200 0x200>;
794 interrupts = <0 40 0x04>; 794 interrupts = <0 40 0x04>;
795 clocks = <&clks 162>; 795 clocks = <&clks 162>;
796 fsl,usbphy = <&usbphy2>; 796 fsl,usbphy = <&usbphy2>;
797 fsl,usbmisc = <&usbmisc 1>; 797 fsl,usbmisc = <&usbmisc 1>;
798 status = "disabled"; 798 status = "disabled";
799 }; 799 };
800 800
801 usbh2: usb@02184400 { 801 usbh2: usb@02184400 {
802 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 802 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
803 reg = <0x02184400 0x200>; 803 reg = <0x02184400 0x200>;
804 interrupts = <0 41 0x04>; 804 interrupts = <0 41 0x04>;
805 clocks = <&clks 162>; 805 clocks = <&clks 162>;
806 fsl,usbmisc = <&usbmisc 2>; 806 fsl,usbmisc = <&usbmisc 2>;
807 phy_type = "hsic"; 807 phy_type = "hsic";
808 fsl,usbphy = <&usbphy_nop1>; 808 fsl,usbphy = <&usbphy_nop1>;
809 fsl,anatop = <&anatop>; 809 fsl,anatop = <&anatop>;
810 status = "disabled"; 810 status = "disabled";
811 }; 811 };
812 812
813 usbh3: usb@02184600 { 813 usbh3: usb@02184600 {
814 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 814 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
815 reg = <0x02184600 0x200>; 815 reg = <0x02184600 0x200>;
816 interrupts = <0 42 0x04>; 816 interrupts = <0 42 0x04>;
817 clocks = <&clks 162>; 817 clocks = <&clks 162>;
818 fsl,usbmisc = <&usbmisc 3>; 818 fsl,usbmisc = <&usbmisc 3>;
819 phy_type = "hsic"; 819 phy_type = "hsic";
820 fsl,usbphy = <&usbphy_nop2>; 820 fsl,usbphy = <&usbphy_nop2>;
821 fsl,anatop = <&anatop>; 821 fsl,anatop = <&anatop>;
822 status = "disabled"; 822 status = "disabled";
823 }; 823 };
824 824
825 usbmisc: usbmisc: usbmisc@02184800 { 825 usbmisc: usbmisc: usbmisc@02184800 {
826 #index-cells = <1>; 826 #index-cells = <1>;
827 compatible = "fsl,imx6q-usbmisc"; 827 compatible = "fsl,imx6q-usbmisc";
828 reg = <0x02184800 0x200>; 828 reg = <0x02184800 0x200>;
829 clocks = <&clks 162>; 829 clocks = <&clks 162>;
830 }; 830 };
831 831
832 fec: ethernet@02188000 { 832 fec: ethernet@02188000 {
833 compatible = "fsl,imx6q-fec"; 833 compatible = "fsl,imx6q-fec";
834 reg = <0x02188000 0x4000>; 834 reg = <0x02188000 0x4000>;
835 interrupts-extended = <&intc 0 118 0x04>, 835 interrupts-extended = <&intc 0 118 0x04>,
836 <&intc 0 119 0x04>; 836 <&intc 0 119 0x04>;
837 clocks = <&clks 117>, <&clks 117>, <&clks 190>; 837 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
838 clock-names = "ipg", "ahb", "ptp"; 838 clock-names = "ipg", "ahb", "ptp";
839 status = "disabled"; 839 status = "disabled";
840 }; 840 };
841 841
842 mlb: mlb@0218c000 { 842 mlb: mlb@0218c000 {
843 compatible = "fsl,imx6q-mlb150"; 843 compatible = "fsl,imx6q-mlb150";
844 reg = <0x0218c000 0x4000>; 844 reg = <0x0218c000 0x4000>;
845 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; 845 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
846 clocks = <&clks 139>, <&clks 175>; 846 clocks = <&clks 139>, <&clks 175>;
847 clock-names = "mlb", "pll8_mlb"; 847 clock-names = "mlb", "pll8_mlb";
848 iram = <&ocram>; 848 iram = <&ocram>;
849 status = "disabled"; 849 status = "disabled";
850 }; 850 };
851 851
852 usdhc1: usdhc@02190000 { 852 usdhc1: usdhc@02190000 {
853 compatible = "fsl,imx6q-usdhc"; 853 compatible = "fsl,imx6q-usdhc";
854 reg = <0x02190000 0x4000>; 854 reg = <0x02190000 0x4000>;
855 interrupts = <0 22 0x04>; 855 interrupts = <0 22 0x04>;
856 clocks = <&clks 163>, <&clks 163>, <&clks 163>; 856 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
857 clock-names = "ipg", "ahb", "per"; 857 clock-names = "ipg", "ahb", "per";
858 bus-width = <4>; 858 bus-width = <4>;
859 status = "disabled"; 859 status = "disabled";
860 }; 860 };
861 861
862 usdhc2: usdhc@02194000 { 862 usdhc2: usdhc@02194000 {
863 compatible = "fsl,imx6q-usdhc"; 863 compatible = "fsl,imx6q-usdhc";
864 reg = <0x02194000 0x4000>; 864 reg = <0x02194000 0x4000>;
865 interrupts = <0 23 0x04>; 865 interrupts = <0 23 0x04>;
866 clocks = <&clks 164>, <&clks 164>, <&clks 164>; 866 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
867 clock-names = "ipg", "ahb", "per"; 867 clock-names = "ipg", "ahb", "per";
868 bus-width = <4>; 868 bus-width = <4>;
869 status = "disabled"; 869 status = "disabled";
870 }; 870 };
871 871
872 usdhc3: usdhc@02198000 { 872 usdhc3: usdhc@02198000 {
873 compatible = "fsl,imx6q-usdhc"; 873 compatible = "fsl,imx6q-usdhc";
874 reg = <0x02198000 0x4000>; 874 reg = <0x02198000 0x4000>;
875 interrupts = <0 24 0x04>; 875 interrupts = <0 24 0x04>;
876 clocks = <&clks 165>, <&clks 165>, <&clks 165>; 876 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
877 clock-names = "ipg", "ahb", "per"; 877 clock-names = "ipg", "ahb", "per";
878 bus-width = <4>; 878 bus-width = <4>;
879 status = "disabled"; 879 status = "disabled";
880 }; 880 };
881 881
882 usdhc4: usdhc@0219c000 { 882 usdhc4: usdhc@0219c000 {
883 compatible = "fsl,imx6q-usdhc"; 883 compatible = "fsl,imx6q-usdhc";
884 reg = <0x0219c000 0x4000>; 884 reg = <0x0219c000 0x4000>;
885 interrupts = <0 25 0x04>; 885 interrupts = <0 25 0x04>;
886 clocks = <&clks 166>, <&clks 166>, <&clks 166>; 886 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
887 clock-names = "ipg", "ahb", "per"; 887 clock-names = "ipg", "ahb", "per";
888 bus-width = <4>; 888 bus-width = <4>;
889 status = "disabled"; 889 status = "disabled";
890 }; 890 };
891 891
892 i2c1: i2c@021a0000 { 892 i2c1: i2c@021a0000 {
893 #address-cells = <1>; 893 #address-cells = <1>;
894 #size-cells = <0>; 894 #size-cells = <0>;
895 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 895 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
896 reg = <0x021a0000 0x4000>; 896 reg = <0x021a0000 0x4000>;
897 interrupts = <0 36 0x04>; 897 interrupts = <0 36 0x04>;
898 clocks = <&clks 125>; 898 clocks = <&clks 125>;
899 status = "disabled"; 899 status = "disabled";
900 }; 900 };
901 901
902 i2c2: i2c@021a4000 { 902 i2c2: i2c@021a4000 {
903 #address-cells = <1>; 903 #address-cells = <1>;
904 #size-cells = <0>; 904 #size-cells = <0>;
905 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 905 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
906 reg = <0x021a4000 0x4000>; 906 reg = <0x021a4000 0x4000>;
907 interrupts = <0 37 0x04>; 907 interrupts = <0 37 0x04>;
908 clocks = <&clks 126>; 908 clocks = <&clks 126>;
909 status = "disabled"; 909 status = "disabled";
910 }; 910 };
911 911
912 i2c3: i2c@021a8000 { 912 i2c3: i2c@021a8000 {
913 #address-cells = <1>; 913 #address-cells = <1>;
914 #size-cells = <0>; 914 #size-cells = <0>;
915 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 915 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
916 reg = <0x021a8000 0x4000>; 916 reg = <0x021a8000 0x4000>;
917 interrupts = <0 38 0x04>; 917 interrupts = <0 38 0x04>;
918 clocks = <&clks 127>; 918 clocks = <&clks 127>;
919 status = "disabled"; 919 status = "disabled";
920 }; 920 };
921 921
922 romcp@021ac000 { 922 romcp@021ac000 {
923 reg = <0x021ac000 0x4000>; 923 reg = <0x021ac000 0x4000>;
924 }; 924 };
925 925
926 mmdc0-1@021b0000 { /* MMDC0-1 */ 926 mmdc0-1@021b0000 { /* MMDC0-1 */
927 compatible = "fsl,imx6q-mmdc-combine"; 927 compatible = "fsl,imx6q-mmdc-combine";
928 reg = <0x021b0000 0x8000>; 928 reg = <0x021b0000 0x8000>;
929 }; 929 };
930 930
931 mmdc0: mmdc@021b0000 { /* MMDC0 */ 931 mmdc0: mmdc@021b0000 { /* MMDC0 */
932 compatible = "fsl,imx6q-mmdc"; 932 compatible = "fsl,imx6q-mmdc";
933 reg = <0x021b0000 0x4000>; 933 reg = <0x021b0000 0x4000>;
934 }; 934 };
935 935
936 mmdc1: mmdc@021b4000 { /* MMDC1 */ 936 mmdc1: mmdc@021b4000 { /* MMDC1 */
937 reg = <0x021b4000 0x4000>; 937 reg = <0x021b4000 0x4000>;
938 }; 938 };
939 939
940 weim: weim@021b8000 { 940 weim: weim@021b8000 {
941 compatible = "fsl,imx6q-weim"; 941 compatible = "fsl,imx6q-weim";
942 reg = <0x021b8000 0x4000>; 942 reg = <0x021b8000 0x4000>;
943 interrupts = <0 14 0x04>; 943 interrupts = <0 14 0x04>;
944 clocks = <&clks 196>; 944 clocks = <&clks 196>;
945 }; 945 };
946 946
947 ocotp: ocotp-ctrl@021bc000 { 947 ocotp: ocotp-ctrl@021bc000 {
948 compatible = "syscon"; 948 compatible = "syscon";
949 reg = <0x021bc000 0x4000>; 949 reg = <0x021bc000 0x4000>;
950 clocks = <&clks 128>; 950 clocks = <&clks 128>;
951 }; 951 };
952 952
953 ocotp-fuse@021bc000 { 953 ocotp-fuse@021bc000 {
954 compatible = "fsl,imx6q-ocotp"; 954 compatible = "fsl,imx6q-ocotp";
955 reg = <0x021bc000 0x4000>; 955 reg = <0x021bc000 0x4000>;
956 clocks = <&clks 128>; 956 clocks = <&clks 128>;
957 }; 957 };
958 958
959 tzasc@021d0000 { /* TZASC1 */ 959 tzasc@021d0000 { /* TZASC1 */
960 reg = <0x021d0000 0x4000>; 960 reg = <0x021d0000 0x4000>;
961 interrupts = <0 108 0x04>; 961 interrupts = <0 108 0x04>;
962 }; 962 };
963 963
964 tzasc@021d4000 { /* TZASC2 */ 964 tzasc@021d4000 { /* TZASC2 */
965 reg = <0x021d4000 0x4000>; 965 reg = <0x021d4000 0x4000>;
966 interrupts = <0 109 0x04>; 966 interrupts = <0 109 0x04>;
967 }; 967 };
968 968
969 audmux: audmux@021d8000 { 969 audmux: audmux@021d8000 {
970 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 970 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
971 reg = <0x021d8000 0x4000>; 971 reg = <0x021d8000 0x4000>;
972 status = "disabled"; 972 status = "disabled";
973 }; 973 };
974 974
975 mipi_csi: mipi_csi@021dc000 { 975 mipi_csi: mipi_csi@021dc000 {
976 compatible = "fsl,imx6q-mipi-csi2"; 976 compatible = "fsl,imx6q-mipi-csi2";
977 reg = <0x021dc000 0x4000>; 977 reg = <0x021dc000 0x4000>;
978 interrupts = <0 100 0x04>, <0 101 0x04>; 978 interrupts = <0 100 0x04>, <0 101 0x04>;
979 clocks = <&clks 138>, <&clks 53>, <&clks 204>; 979 clocks = <&clks 138>, <&clks 53>, <&clks 204>;
980 /* Note: clks 138 is hsi_tx, however, the dphy_c 980 /* Note: clks 138 is hsi_tx, however, the dphy_c
981 * hsi_tx and pll_refclk use the same clk gate. 981 * hsi_tx and pll_refclk use the same clk gate.
982 * In current clk driver, open/close clk gate do 982 * In current clk driver, open/close clk gate do
983 * use hsi_tx for a temporary debug purpose. 983 * use hsi_tx for a temporary debug purpose.
984 */ 984 */
985 clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; 985 clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
986 status = "disabled"; 986 status = "disabled";
987 }; 987 };
988 988
989 vdoa@021e4000 { 989 vdoa@021e4000 {
990 compatible = "fsl,imx6q-vdoa"; 990 compatible = "fsl,imx6q-vdoa";
991 reg = <0x021e4000 0x4000>; 991 reg = <0x021e4000 0x4000>;
992 interrupts = <0 18 0x04>; 992 interrupts = <0 18 0x04>;
993 clocks = <&clks 202>; 993 clocks = <&clks 202>;
994 iram = <&ocram>; 994 iram = <&ocram>;
995 }; 995 };
996 996
997 uart2: serial@021e8000 { 997 uart2: serial@021e8000 {
998 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 998 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
999 reg = <0x021e8000 0x4000>; 999 reg = <0x021e8000 0x4000>;
1000 interrupts = <0 27 0x04>; 1000 interrupts = <0 27 0x04>;
1001 clocks = <&clks 160>, <&clks 161>; 1001 clocks = <&clks 160>, <&clks 161>;
1002 clock-names = "ipg", "per"; 1002 clock-names = "ipg", "per";
1003 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1003 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1004 dma-names = "rx", "tx"; 1004 dma-names = "rx", "tx";
1005 status = "disabled"; 1005 status = "disabled";
1006 }; 1006 };
1007 1007
1008 uart3: serial@021ec000 { 1008 uart3: serial@021ec000 {
1009 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1009 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1010 reg = <0x021ec000 0x4000>; 1010 reg = <0x021ec000 0x4000>;
1011 interrupts = <0 28 0x04>; 1011 interrupts = <0 28 0x04>;
1012 clocks = <&clks 160>, <&clks 161>; 1012 clocks = <&clks 160>, <&clks 161>;
1013 clock-names = "ipg", "per"; 1013 clock-names = "ipg", "per";
1014 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1014 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1015 dma-names = "rx", "tx"; 1015 dma-names = "rx", "tx";
1016 status = "disabled"; 1016 status = "disabled";
1017 }; 1017 };
1018 1018
1019 uart4: serial@021f0000 { 1019 uart4: serial@021f0000 {
1020 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1020 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1021 reg = <0x021f0000 0x4000>; 1021 reg = <0x021f0000 0x4000>;
1022 interrupts = <0 29 0x04>; 1022 interrupts = <0 29 0x04>;
1023 clocks = <&clks 160>, <&clks 161>; 1023 clocks = <&clks 160>, <&clks 161>;
1024 clock-names = "ipg", "per"; 1024 clock-names = "ipg", "per";
1025 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1025 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1026 dma-names = "rx", "tx"; 1026 dma-names = "rx", "tx";
1027 status = "disabled"; 1027 status = "disabled";
1028 }; 1028 };
1029 1029
1030 uart5: serial@021f4000 { 1030 uart5: serial@021f4000 {
1031 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1031 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1032 reg = <0x021f4000 0x4000>; 1032 reg = <0x021f4000 0x4000>;
1033 interrupts = <0 30 0x04>; 1033 interrupts = <0 30 0x04>;
1034 clocks = <&clks 160>, <&clks 161>; 1034 clocks = <&clks 160>, <&clks 161>;
1035 clock-names = "ipg", "per"; 1035 clock-names = "ipg", "per";
1036 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1036 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1037 dma-names = "rx", "tx"; 1037 dma-names = "rx", "tx";
1038 status = "disabled"; 1038 status = "disabled";
1039 }; 1039 };
1040 }; 1040 };
1041 1041
1042 ipu1: ipu@02400000 { 1042 ipu1: ipu@02400000 {
1043 compatible = "fsl,imx6q-ipu"; 1043 compatible = "fsl,imx6q-ipu";
1044 reg = <0x02400000 0x400000>; 1044 reg = <0x02400000 0x400000>;
1045 interrupts = <0 6 0x4 0 5 0x4>; 1045 interrupts = <0 6 0x4 0 5 0x4>;
1046 clocks = <&clks 130>, <&clks 131>, <&clks 132>, 1046 clocks = <&clks 130>, <&clks 131>, <&clks 132>,
1047 <&clks 39>, <&clks 40>, 1047 <&clks 39>, <&clks 40>,
1048 <&clks 135>, <&clks 136>; 1048 <&clks 135>, <&clks 136>;
1049 clock-names = "bus", "di0", "di1", 1049 clock-names = "bus", "di0", "di1",
1050 "di0_sel", "di1_sel", 1050 "di0_sel", "di1_sel",
1051 "ldb_di0", "ldb_di1"; 1051 "ldb_di0", "ldb_di1";
1052 resets = <&src 2>; 1052 resets = <&src 2>;
1053 bypass_reset = <0>; 1053 bypass_reset = <0>;
1054 }; 1054 };
1055 }; 1055 };
1056 }; 1056 };
1057 1057
1058 1058
1059 &iomuxc { 1059 &iomuxc {
1060 audmux { 1060 audmux {
1061 pinctrl_audmux_1: audmux-1 { 1061 pinctrl_audmux_1: audmux-1 {
1062 fsl,pins = < 1062 fsl,pins = <
1063 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 1063 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
1064 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 1064 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
1065 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 1065 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
1066 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 1066 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
1067 >; 1067 >;
1068 }; 1068 };
1069 1069
1070 pinctrl_audmux_2: audmux-2 { 1070 pinctrl_audmux_2: audmux-2 {
1071 fsl,pins = < 1071 fsl,pins = <
1072 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 1072 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
1073 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 1073 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
1074 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 1074 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
1075 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 1075 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
1076 >; 1076 >;
1077 }; 1077 };
1078 1078
1079 pinctrl_audmux_3: audmux-3 { 1079 pinctrl_audmux_3: audmux-3 {
1080 fsl,pins = < 1080 fsl,pins = <
1081 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 1081 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
1082 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 1082 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
1083 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 1083 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
1084 >; 1084 >;
1085 }; 1085 };
1086 }; 1086 };
1087 1087
1088 ecspi1 { 1088 ecspi1 {
1089 pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { 1089 pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
1090 fsl,pins = < 1090 fsl,pins = <
1091 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 1091 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
1092 >; 1092 >;
1093 }; 1093 };
1094 pinctrl_ecspi1_cs_2: ecspi1_cs_grp-2 { 1094 pinctrl_ecspi1_cs_2: ecspi1_cs_grp-2 {
1095 fsl,pins = < 1095 fsl,pins = <
1096 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x80000000 1096 MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x80000000
1097 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 1097 MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x80000000
1098 >; 1098 >;
1099 }; 1099 };
1100 1100
1101 pinctrl_ecspi1_1: ecspi1grp-1 { 1101 pinctrl_ecspi1_1: ecspi1grp-1 {
1102 fsl,pins = < 1102 fsl,pins = <
1103 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 1103 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
1104 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 1104 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
1105 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 1105 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
1106 >; 1106 >;
1107 }; 1107 };
1108 1108
1109 pinctrl_ecspi1_2: ecspi1grp-2 { 1109 pinctrl_ecspi1_2: ecspi1grp-2 {
1110 fsl,pins = < 1110 fsl,pins = <
1111 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 1111 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
1112 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 1112 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
1113 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 1113 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
1114 >; 1114 >;
1115 }; 1115 };
1116 }; 1116 };
1117 1117
1118 ecspi2 { 1118 ecspi2 {
1119 pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 { 1119 pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 {
1120 fsl,pins = < 1120 fsl,pins = <
1121 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x80000000 1121 MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x80000000
1122 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x80000000 1122 MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x80000000
1123 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 1123 MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x80000000
1124 >; 1124 >;
1125 }; 1125 };
1126 1126
1127 1127
1128 1128
1129 pinctrl_ecspi2_1: ecspi2grp-1 { 1129 pinctrl_ecspi2_1: ecspi2grp-1 {
1130 fsl,pins = < 1130 fsl,pins = <
1131 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 1131 MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
1132 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 1132 MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
1133 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 1133 MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
1134 >; 1134 >;
1135 }; 1135 };
1136 }; 1136 };
1137 1137
1138 ecspi3 { 1138 ecspi3 {
1139 pinctrl_ecspi3_1: ecspi3grp-1 { 1139 pinctrl_ecspi3_1: ecspi3grp-1 {
1140 fsl,pins = < 1140 fsl,pins = <
1141 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 1141 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
1142 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 1142 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
1143 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 1143 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
1144 >; 1144 >;
1145 }; 1145 };
1146 }; 1146 };
1147 1147
1148 enet { 1148 enet {
1149 pinctrl_enet_1: enetgrp-1 { 1149 pinctrl_enet_1: enetgrp-1 {
1150 fsl,pins = < 1150 fsl,pins = <
1151 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 1151 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
1152 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 1152 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
1153 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 1153 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
1154 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 1154 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
1155 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 1155 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
1156 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 1156 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
1157 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 1157 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
1158 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 1158 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
1159 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 1159 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
1160 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 1160 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
1161 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 1161 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
1162 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 1162 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
1163 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 1163 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
1164 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 1164 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
1165 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 1165 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
1166 /*MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8*/
1167 /* AR8035 interrupt */
1168 /*MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000*/
1169 >; 1166 >;
1170 }; 1167 };
1171 1168
1172 pinctrl_enet_2: enetgrp-2 { 1169 pinctrl_enet_2: enetgrp-2 {
1173 fsl,pins = < 1170 fsl,pins = <
1174 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 1171 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
1175 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 1172 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
1176 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 1173 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
1177 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 1174 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
1178 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 1175 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
1179 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 1176 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
1180 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 1177 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
1181 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 1178 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
1182 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 1179 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
1183 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 1180 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
1184 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 1181 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
1185 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 1182 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
1186 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 1183 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
1187 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 1184 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
1188 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 1185 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
1189 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 1186 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
1190 >; 1187 >;
1191 }; 1188 };
1192 1189
1193 pinctrl_enet_3: enetgrp-3 { 1190 pinctrl_enet_3: enetgrp-3 {
1194 fsl,pins = < 1191 fsl,pins = <
1195 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 1192 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
1196 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 1193 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
1197 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 1194 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
1198 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 1195 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
1199 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 1196 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
1200 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 1197 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
1201 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 1198 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
1202 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 1199 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
1203 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 1200 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
1204 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 1201 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
1205 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 1202 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
1206 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 1203 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
1207 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 1204 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
1208 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 1205 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
1209 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 1206 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
1210 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 1207 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
1211 >; 1208 >;
1212 }; 1209 };
1213 1210
1214 pinctrl_enet_irq: enetirqgrp { 1211 pinctrl_enet_irq: enetirqgrp {
1215 fsl,pins = < 1212 fsl,pins = <
1213 /* AR8035 interrupt */
1216 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x000b1 1214 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x000b1
1217 >; 1215 >;
1218 }; 1216 };
1219 }; 1217 };
1220 1218
1221 esai { 1219 esai {
1222 pinctrl_esai_1: esaigrp-1 { 1220 pinctrl_esai_1: esaigrp-1 {
1223 fsl,pins = < 1221 fsl,pins = <
1224 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 1222 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
1225 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 1223 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
1226 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 1224 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
1227 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 1225 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
1228 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 1226 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
1229 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 1227 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
1230 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 1228 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
1231 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 1229 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
1232 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 1230 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
1233 >; 1231 >;
1234 }; 1232 };
1235 1233
1236 pinctrl_esai_2: esaigrp-2 { 1234 pinctrl_esai_2: esaigrp-2 {
1237 fsl,pins = < 1235 fsl,pins = <
1238 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 1236 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
1239 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 1237 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
1240 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 1238 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
1241 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 1239 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
1242 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 1240 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
1243 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 1241 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
1244 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 1242 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
1245 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 1243 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
1246 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 1244 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
1247 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030 1245 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
1248 >; 1246 >;
1249 }; 1247 };
1250 }; 1248 };
1251 1249
1252 flexcan1 { 1250 flexcan1 {
1253 pinctrl_flexcan1_1: flexcan1grp-1 { 1251 pinctrl_flexcan1_1: flexcan1grp-1 {
1254 fsl,pins = < 1252 fsl,pins = <
1255 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 1253 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
1256 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 1254 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
1257 >; 1255 >;
1258 }; 1256 };
1259 1257
1260 pinctrl_flexcan1_2: flexcan1grp-2 { 1258 pinctrl_flexcan1_2: flexcan1grp-2 {
1261 fsl,pins = < 1259 fsl,pins = <
1262 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 1260 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
1263 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 1261 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
1264 >; 1262 >;
1265 }; 1263 };
1266 1264
1267 pinctrl_flexcan1_3: flexcan1grp-3 { 1265 pinctrl_flexcan1_3: flexcan1grp-3 {
1268 fsl,pins = < 1266 fsl,pins = <
1269 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 1267 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
1270 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000 1268 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000
1271 >; 1269 >;
1272 }; 1270 };
1273 }; 1271 };
1274 1272
1275 flexcan2 { 1273 flexcan2 {
1276 pinctrl_flexcan2_1: flexcan2grp-1 { 1274 pinctrl_flexcan2_1: flexcan2grp-1 {
1277 fsl,pins = < 1275 fsl,pins = <
1278 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 1276 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
1279 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 1277 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
1280 >; 1278 >;
1281 }; 1279 };
1282 }; 1280 };
1283 1281
1284 gpmi-nand { 1282 gpmi-nand {
1285 pinctrl_gpmi_nand_1: gpmi-nand-1 { 1283 pinctrl_gpmi_nand_1: gpmi-nand-1 {
1286 fsl,pins = < 1284 fsl,pins = <
1287 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 1285 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
1288 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 1286 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
1289 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 1287 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
1290 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 1288 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
1291 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 1289 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
1292 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 1290 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
1293 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 1291 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
1294 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 1292 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
1295 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 1293 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
1296 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 1294 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
1297 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 1295 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
1298 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 1296 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
1299 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 1297 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
1300 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 1298 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
1301 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 1299 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
1302 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 1300 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
1303 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 1301 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
1304 >; 1302 >;
1305 }; 1303 };
1306 }; 1304 };
1307 1305
1308 hdmi_hdcp { 1306 hdmi_hdcp {
1309 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 { 1307 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
1310 fsl,pins = < 1308 fsl,pins = <
1311 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 1309 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
1312 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 1310 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
1313 >; 1311 >;
1314 }; 1312 };
1315 1313
1316 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 { 1314 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
1317 fsl,pins = < 1315 fsl,pins = <
1318 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 1316 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
1319 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 1317 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
1320 >; 1318 >;
1321 }; 1319 };
1322 1320
1323 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 { 1321 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
1324 fsl,pins = < 1322 fsl,pins = <
1325 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 1323 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
1326 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 1324 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
1327 >; 1325 >;
1328 }; 1326 };
1329 }; 1327 };
1330 1328
1331 hdmi_cec { 1329 hdmi_cec {
1332 pinctrl_hdmi_cec_1: hdmicecgrp-1 { 1330 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
1333 fsl,pins = < 1331 fsl,pins = <
1334 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 1332 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
1335 >; 1333 >;
1336 }; 1334 };
1337 1335
1338 pinctrl_hdmi_cec_2: hdmicecgrp-2 { 1336 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
1339 fsl,pins = < 1337 fsl,pins = <
1340 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 1338 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
1341 >; 1339 >;
1342 }; 1340 };
1343 }; 1341 };
1344 1342
1345 i2c1 { 1343 i2c1 {
1346 pinctrl_i2c1_1: i2c1grp-1 { 1344 pinctrl_i2c1_1: i2c1grp-1 {
1347 fsl,pins = < 1345 fsl,pins = <
1348 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 1346 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
1349 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 1347 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
1350 >; 1348 >;
1351 }; 1349 };
1352 1350
1353 pinctrl_i2c1_2: i2c1grp-2 { 1351 pinctrl_i2c1_2: i2c1grp-2 {
1354 fsl,pins = < 1352 fsl,pins = <
1355 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 1353 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
1356 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 1354 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
1357 >; 1355 >;
1358 }; 1356 };
1359 }; 1357 };
1360 1358
1361 i2c2 { 1359 i2c2 {
1362 pinctrl_i2c2_1: i2c2grp-1 { 1360 pinctrl_i2c2_1: i2c2grp-1 {
1363 fsl,pins = < 1361 fsl,pins = <
1364 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 1362 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
1365 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 1363 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
1366 >; 1364 >;
1367 }; 1365 };
1368 1366
1369 pinctrl_i2c2_2: i2c2grp-2 { 1367 pinctrl_i2c2_2: i2c2grp-2 {
1370 fsl,pins = < 1368 fsl,pins = <
1371 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 1369 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
1372 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 1370 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
1373 >; 1371 >;
1374 }; 1372 };
1375 1373
1376 pinctrl_i2c2_3: i2c2grp-3 { 1374 pinctrl_i2c2_3: i2c2grp-3 {
1377 fsl,pins = < 1375 fsl,pins = <
1378 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 1376 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
1379 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 1377 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
1380 >; 1378 >;
1381 }; 1379 };
1382 }; 1380 };
1383 1381
1384 i2c3 { 1382 i2c3 {
1385 pinctrl_i2c3_1: i2c3grp-1 { 1383 pinctrl_i2c3_1: i2c3grp-1 {
1386 fsl,pins = < 1384 fsl,pins = <
1387 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 1385 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
1388 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 1386 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
1389 >; 1387 >;
1390 }; 1388 };
1391 1389
1392 pinctrl_i2c3_2: i2c3grp-2 { 1390 pinctrl_i2c3_2: i2c3grp-2 {
1393 fsl,pins = < 1391 fsl,pins = <
1394 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 1392 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
1395 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 1393 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
1396 >; 1394 >;
1397 }; 1395 };
1398 1396
1399 pinctrl_i2c3_3: i2c3grp-3 { 1397 pinctrl_i2c3_3: i2c3grp-3 {
1400 fsl,pins = < 1398 fsl,pins = <
1401 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 1399 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
1402 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 1400 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
1403 >; 1401 >;
1404 }; 1402 };
1405 1403
1406 pinctrl_i2c3_4: i2c3grp-4 { 1404 pinctrl_i2c3_4: i2c3grp-4 {
1407 fsl,pins = < 1405 fsl,pins = <
1408 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 1406 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
1409 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 1407 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
1410 >; 1408 >;
1411 }; 1409 };
1412 }; 1410 };
1413 1411
1414 ipu1 { 1412 ipu1 {
1415 pinctrl_ipu1_1: ipu1grp-1 { 1413 pinctrl_ipu1_1: ipu1grp-1 {
1416 fsl,pins = < 1414 fsl,pins = <
1417 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 1415 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xe1
1418 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 1416 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xe1
1419 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 1417 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xe1
1420 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 1418 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xe1
1421 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 1419 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
1422 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 1420 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xe1
1423 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 1421 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xe1
1424 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 1422 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xe1
1425 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 1423 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xe1
1426 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 1424 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xe1
1427 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 1425 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xe1
1428 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 1426 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xe1
1429 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 1427 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xe1
1430 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 1428 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xe1
1431 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 1429 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xe1
1432 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 1430 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xe1
1433 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 1431 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xe1
1434 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 1432 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xe1
1435 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 1433 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xe1
1436 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 1434 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1
1437 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 1435 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xe1
1438 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 1436 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xe1
1439 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 1437 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xe1
1440 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 1438 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xe1
1441 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 1439 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xe1
1442 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 1440 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xe1
1443 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 1441 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xe1
1444 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 1442 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xe1
1445 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 1443 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xe1
1446 >; 1444 >;
1447 }; 1445 };
1448 1446
1449 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ 1447 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
1450 fsl,pins = < 1448 fsl,pins = <
1451 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 1449 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
1452 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 1450 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
1453 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 1451 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
1454 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 1452 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
1455 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 1453 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
1456 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 1454 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
1457 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 1455 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
1458 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 1456 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
1459 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 1457 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
1460 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 1458 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
1461 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 1459 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
1462 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 1460 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
1463 >; 1461 >;
1464 }; 1462 };
1465 1463
1466 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */ 1464 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
1467 fsl,pins = < 1465 fsl,pins = <
1468 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 1466 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
1469 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 1467 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
1470 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 1468 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
1471 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 1469 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
1472 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 1470 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
1473 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 1471 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
1474 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 1472 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
1475 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 1473 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
1476 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 1474 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
1477 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 1475 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
1478 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 1476 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
1479 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 1477 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
1480 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 1478 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
1481 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 1479 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
1482 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 1480 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
1483 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 1481 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
1484 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 1482 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
1485 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 1483 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
1486 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 1484 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
1487 >; 1485 >;
1488 }; 1486 };
1489 }; 1487 };
1490 1488
1491 mlb { 1489 mlb {
1492 pinctrl_mlb_1: mlbgrp-1 { 1490 pinctrl_mlb_1: mlbgrp-1 {
1493 fsl,pins = < 1491 fsl,pins = <
1494 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 1492 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
1495 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 1493 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
1496 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71 1494 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
1497 >; 1495 >;
1498 }; 1496 };
1499 1497
1500 pinctrl_mlb_2: mlbgrp-2 { 1498 pinctrl_mlb_2: mlbgrp-2 {
1501 fsl,pins = < 1499 fsl,pins = <
1502 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 1500 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
1503 MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 1501 MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
1504 MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 1502 MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
1505 >; 1503 >;
1506 }; 1504 };
1507 }; 1505 };
1508 1506
1509 pwm1 { 1507 pwm1 {
1510 pinctrl_pwm1_1: pwm1grp-1 { 1508 pinctrl_pwm1_1: pwm1grp-1 {
1511 fsl,pins = < 1509 fsl,pins = <
1512 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 1510 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
1513 >; 1511 >;
1514 }; 1512 };
1515 }; 1513 };
1516 1514
1517 pwm2 { 1515 pwm2 {
1518 pinctrl_pwm2_1: pwm2grp-1 { 1516 pinctrl_pwm2_1: pwm2grp-1 {
1519 fsl,pins = < 1517 fsl,pins = <
1520 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 1518 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
1521 >; 1519 >;
1522 }; 1520 };
1523 }; 1521 };
1524 1522
1525 pwm3 { 1523 pwm3 {
1526 pinctrl_pwm3_1: pwm3grp-1 { 1524 pinctrl_pwm3_1: pwm3grp-1 {
1527 fsl,pins = < 1525 fsl,pins = <
1528 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 1526 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
1529 >; 1527 >;
1530 }; 1528 };
1531 }; 1529 };
1532 1530
1533 spdif { 1531 spdif {
1534 pinctrl_spdif_1: spdifgrp-1 { 1532 pinctrl_spdif_1: spdifgrp-1 {
1535 fsl,pins = < 1533 fsl,pins = <
1536 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0 1534 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1537 >; 1535 >;
1538 }; 1536 };
1539 1537
1540 pinctrl_spdif_2: spdifgrp-2 { 1538 pinctrl_spdif_2: spdifgrp-2 {
1541 fsl,pins = < 1539 fsl,pins = <
1542 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 1540 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1543 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1541 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1544 >; 1542 >;
1545 }; 1543 };
1546 }; 1544 };
1547 1545
1548 uart1 { 1546 uart1 {
1549 pinctrl_uart1_1: uart1grp-1 { 1547 pinctrl_uart1_1: uart1grp-1 {
1550 fsl,pins = < 1548 fsl,pins = <
1551 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1549 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1552 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1550 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1553 >; 1551 >;
1554 }; 1552 };
1555 pinctrl_uart1_2: uart1grp-2 { 1553 pinctrl_uart1_2: uart1grp-2 {
1556 fsl,pins = < 1554 fsl,pins = <
1557 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 1555 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
1558 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 1556 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
1559 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 1557 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
1560 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 1558 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
1561 >; 1559 >;
1562 }; 1560 };
1563 }; 1561 };
1564 1562
1565 uart2 { 1563 uart2 {
1566 pinctrl_uart2_1: uart2grp-1 { 1564 pinctrl_uart2_1: uart2grp-1 {
1567 fsl,pins = < 1565 fsl,pins = <
1568 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 1566 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1569 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 1567 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1570 >; 1568 >;
1571 }; 1569 };
1572 1570
1573 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */ 1571 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1574 fsl,pins = < 1572 fsl,pins = <
1575 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 1573 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1576 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 1574 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1577 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 1575 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1578 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 1576 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1579 >; 1577 >;
1580 }; 1578 };
1581 }; 1579 };
1582 1580
1583 uart3 { 1581 uart3 {
1584 pinctrl_uart3_1: uart3grp-1 { 1582 pinctrl_uart3_1: uart3grp-1 {
1585 fsl,pins = < 1583 fsl,pins = <
1586 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 1584 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1587 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 1585 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1588 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 1586 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1589 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 1587 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1590 >; 1588 >;
1591 }; 1589 };
1592 1590
1593 pinctrl_uart3dte_1: uart3dtegrp-1 { 1591 pinctrl_uart3dte_1: uart3dtegrp-1 {
1594 fsl,pins = < 1592 fsl,pins = <
1595 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 1593 MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
1596 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 1594 MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
1597 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 1595 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
1598 MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 1596 MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
1599 >; 1597 >;
1600 }; 1598 };
1601 }; 1599 };
1602 1600
1603 uart4 { 1601 uart4 {
1604 pinctrl_uart4_1: uart4grp-1 { 1602 pinctrl_uart4_1: uart4grp-1 {
1605 fsl,pins = < 1603 fsl,pins = <
1606 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 1604 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1607 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 1605 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1608 >; 1606 >;
1609 }; 1607 };
1610 1608
1611 pinctrl_uart4_2: uart4grp-2 { 1609 pinctrl_uart4_2: uart4grp-2 {
1612 fsl,pins = < 1610 fsl,pins = <
1613 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 1611 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
1614 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 1612 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
1615 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 1613 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
1616 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 1614 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
1617 >; 1615 >;
1618 }; 1616 };
1619 }; 1617 };
1620 1618
1621 uart5 { 1619 uart5 {
1622 pinctrl_uart5_1: uart5grp-1 { 1620 pinctrl_uart5_1: uart5grp-1 {
1623 fsl,pins = < 1621 fsl,pins = <
1624 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 1622 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
1625 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 1623 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
1626 MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 1624 MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1
1627 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 1625 MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1
1628 >; 1626 >;
1629 }; 1627 };
1630 1628
1631 pinctrl_uart5dte_1: uart5dtegrp-1 { 1629 pinctrl_uart5dte_1: uart5dtegrp-1 {
1632 fsl,pins = < 1630 fsl,pins = <
1633 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 1631 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
1634 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 1632 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
1635 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 1633 MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1
1636 MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 1634 MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1
1637 >; 1635 >;
1638 }; 1636 };
1639 1637
1640 pinctrl_uart5_2: uart5grp-2 { 1638 pinctrl_uart5_2: uart5grp-2 {
1641 fsl,pins = < 1639 fsl,pins = <
1642 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 1640 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
1643 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 1641 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
1644 >; 1642 >;
1645 }; 1643 };
1646 1644
1647 }; 1645 };
1648 1646
1649 usbotg { 1647 usbotg {
1650 pinctrl_usbotg_1: usbotggrp-1 { 1648 pinctrl_usbotg_1: usbotggrp-1 {
1651 fsl,pins = < 1649 fsl,pins = <
1652 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 1650 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1653 >; 1651 >;
1654 }; 1652 };
1655 1653
1656 pinctrl_usbotg_2: usbotggrp-2 { 1654 pinctrl_usbotg_2: usbotggrp-2 {
1657 fsl,pins = < 1655 fsl,pins = <
1658 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 1656 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1659 >; 1657 >;
1660 }; 1658 };
1661 }; 1659 };
1662 1660
1663 usbh2 { 1661 usbh2 {
1664 pinctrl_usbh2_1: usbh2grp-1 { 1662 pinctrl_usbh2_1: usbh2grp-1 {
1665 fsl,pins = < 1663 fsl,pins = <
1666 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 1664 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1667 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 1665 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1668 >; 1666 >;
1669 }; 1667 };
1670 1668
1671 pinctrl_usbh2_2: usbh2grp-2 { 1669 pinctrl_usbh2_2: usbh2grp-2 {
1672 fsl,pins = < 1670 fsl,pins = <
1673 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 1671 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1674 >; 1672 >;
1675 }; 1673 };
1676 }; 1674 };
1677 1675
1678 usbh3 { 1676 usbh3 {
1679 pinctrl_usbh3_1: usbh3grp-1 { 1677 pinctrl_usbh3_1: usbh3grp-1 {
1680 fsl,pins = < 1678 fsl,pins = <
1681 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 1679 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1682 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 1680 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1683 >; 1681 >;
1684 }; 1682 };
1685 1683
1686 pinctrl_usbh3_2: usbh3grp-2 { 1684 pinctrl_usbh3_2: usbh3grp-2 {
1687 fsl,pins = < 1685 fsl,pins = <
1688 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 1686 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1689 >; 1687 >;
1690 }; 1688 };
1691 }; 1689 };
1692 1690
1693 usdhc1 { 1691 usdhc1 {
1694 pinctrl_usdhc1_1: usdhc1grp-1 { 1692 pinctrl_usdhc1_1: usdhc1grp-1 {
1695 fsl,pins = < 1693 fsl,pins = <
1696 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1694 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
1697 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1695 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
1698 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1696 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
1699 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1697 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
1700 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1698 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
1701 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1699 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
1702 >; 1700 >;
1703 }; 1701 };
1704 }; 1702 };
1705 1703
1706 usdhc2 { 1704 usdhc2 {
1707 pinctrl_usdhc2_1: usdhc2grp-1 { 1705 pinctrl_usdhc2_1: usdhc2grp-1 {
1708 fsl,pins = < 1706 fsl,pins = <
1709 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 1707 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1710 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 1708 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1711 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 1709 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1712 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 1710 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1713 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 1711 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1714 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 1712 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1715 /*MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1716 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1717 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1718 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059*/
1719 >; 1713 >;
1720 }; 1714 };
1721 1715
1722 pinctrl_usdhc2_2: usdhc2grp-2 { 1716 pinctrl_usdhc2_2: usdhc2grp-2 {
1723 fsl,pins = < 1717 fsl,pins = <
1724 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 1718 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1725 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 1719 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1726 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 1720 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1727 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 1721 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1728 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 1722 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1729 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 1723 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1730 >; 1724 >;
1731 }; 1725 };
1732 }; 1726 };
1733 1727
1734 usdhc3 { 1728 usdhc3 {
1735 pinctrl_usdhc3_1: usdhc3grp-1 { 1729 pinctrl_usdhc3_1: usdhc3grp-1 {
1736 fsl,pins = < 1730 fsl,pins = <
1737 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1731 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1738 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1732 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1739 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1733 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1740 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1734 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1741 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1735 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1742 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1736 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1743 /*MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1737 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
1744 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1745 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1746 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059*/
1747 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
1748 >; 1738 >;
1749 }; 1739 };
1750 1740
1751 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */ 1741 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
1752 fsl,pins = < 1742 fsl,pins = <
1753 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 1743 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
1754 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 1744 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
1755 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 1745 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
1756 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 1746 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
1757 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 1747 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
1758 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 1748 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
1759 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170B9 1749 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
1760 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170B9 1750 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
1761 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170B9 1751 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
1762 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170B9 1752 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170B9
1763 >; 1753 >;
1764 }; 1754 };
1765 1755
1766 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */ 1756 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
1767 fsl,pins = < 1757 fsl,pins = <
1768 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 1758 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
1769 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 1759 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
1770 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 1760 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
1771 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 1761 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
1772 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 1762 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
1773 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 1763 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
1774 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170F9 1764 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
1775 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170F9 1765 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
1776 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170F9 1766 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
1777 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170F9 1767 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170F9
1778 >; 1768 >;
1779 }; 1769 };
1780 1770
1781 pinctrl_usdhc3_2: usdhc3grp-2 { 1771 pinctrl_usdhc3_2: usdhc3grp-2 {
1782 fsl,pins = < 1772 fsl,pins = <
1783 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1773 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1784 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1774 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1785 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1775 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1786 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1776 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1787 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1777 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1788 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1778 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1789 >; 1779 >;
1790 }; 1780 };
1791 }; 1781 };
1792 1782
1793 usdhc4 { 1783 usdhc4 {
1794 pinctrl_usdhc4_1: usdhc4grp-1 { 1784 pinctrl_usdhc4_1: usdhc4grp-1 {
1795 fsl,pins = < 1785 fsl,pins = <
1796 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 1786 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1797 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 1787 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1798 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 1788 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1799 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 1789 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1800 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 1790 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1801 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 1791 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1802 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 1792 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1803 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 1793 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1804 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 1794 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1805 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 1795 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1806 >; 1796 >;
1807 }; 1797 };
1808 1798
1809 pinctrl_usdhc4_2: usdhc4grp-2 { 1799 pinctrl_usdhc4_2: usdhc4grp-2 {
1810 fsl,pins = < 1800 fsl,pins = <
1811 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 1801 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1812 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 1802 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1813 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 1803 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1814 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 1804 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1815 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 1805 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1816 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 1806 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1817 >; 1807 >;
1818 }; 1808 };
1819 }; 1809 };
1820 1810
1821 weim { 1811 weim {
1822 pinctrl_weim_cs0_1: weim_cs0grp-1 { 1812 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1823 fsl,pins = < 1813 fsl,pins = <
1824 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 1814 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1825 >; 1815 >;
1826 }; 1816 };
1827 1817
1828 pinctrl_weim_nor_1: weim_norgrp-1 { 1818 pinctrl_weim_nor_1: weim_norgrp-1 {
1829 fsl,pins = < 1819 fsl,pins = <
1830 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 1820 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1831 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 1821 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1832 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 1822 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1833 /* data */ 1823 /* data */
1834 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 1824 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1835 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 1825 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1836 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 1826 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1837 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 1827 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1838 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 1828 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1839 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 1829 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1840 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 1830 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1841 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 1831 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1842 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 1832 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1843 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 1833 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1844 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 1834 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1845 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 1835 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1846 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 1836 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1847 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 1837 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1848 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 1838 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1849 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 1839 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1850 /* address */ 1840 /* address */
1851 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 1841 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1852 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 1842 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1853 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 1843 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1854 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 1844 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1855 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 1845 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1856 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 1846 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1857 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 1847 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1858 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 1848 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1859 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 1849 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1860 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 1850 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1861 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 1851 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1862 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 1852 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1863 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 1853 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1864 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 1854 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1865 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 1855 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1866 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 1856 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1867 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 1857 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1868 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 1858 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1869 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 1859 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1870 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 1860 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1871 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 1861 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1872 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 1862 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1873 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 1863 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1874 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 1864 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1875 >; 1865 >;
1876 }; 1866 };
1877 }; 1867 };
1878 }; 1868 };
arch/arm/boot/dts/imx6qdl-smarcfimx6.dtsi
Diff comments   View file @ 8f7b130
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations: 7 * Version 2 or later at the following locations:
8 * 8 *
9 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13 / { 13 / {
14 aliases { 14 aliases {
15 mxcfb0 = &mxcfb1; 15 mxcfb0 = &mxcfb1;
16 mxcfb1 = &mxcfb2; 16 mxcfb1 = &mxcfb2;
17 mxcfb2 = &mxcfb3; 17 mxcfb2 = &mxcfb3;
18 mxcfb3 = &mxcfb4; 18 mxcfb3 = &mxcfb4;
19 }; 19 };
20 20
21 memory { 21 memory {
22 reg = <0x10000000 0x40000000>; 22 reg = <0x10000000 0x40000000>;
23 }; 23 };
24 24
25 battery: max8903@0 {
26 compatible = "fsl,max8903-charger";
27 pinctrl-names = "default";
28 dok_input = <&gpio2 24 1>;
29 uok_input = <&gpio1 27 1>;
30 chg_input = <&gpio3 23 1>;
31 flt_input = <&gpio5 2 1>;
32 fsl,dcm_always_high;
33 fsl,dc_valid;
34 fsl,usb_valid;
35 status = "okay";
36 };
37
38 hannstar_cabc { 25 hannstar_cabc {
39 compatible = "hannstar,cabc"; 26 compatible = "hannstar,cabc";
40 27
41 lvds0 { 28 lvds0 {
42 gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; 29 gpios = <&gpio1 00 GPIO_ACTIVE_HIGH>;
43 }; 30 };
44 31
45 lvds1 { 32 lvds1 {
46 gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; 33 gpios = <&gpio1 00 GPIO_ACTIVE_HIGH>;
47 }; 34 };
48 }; 35 };
49 36
50 regulators { 37 regulators {
51 compatible = "simple-bus"; 38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <0>;
52 41
53 reg_usb_otg_vbus: usb_otg_vbus { 42 reg_usb_otg_vbus: usb_otg_vbus {
54 compatible = "regulator-fixed"; 43 compatible = "regulator-fixed";
55 regulator-name = "usb_otg_vbus"; 44 regulator-name = "usb_otg_vbus";
56 regulator-min-microvolt = <5000000>; 45 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>; 46 regulator-max-microvolt = <5000000>;
58 gpio = <&gpio3 22 0>; 47 gpio = <&gpio1 29 0>;
59 enable-active-high; 48 enable-active-high;
60 }; 49 };
61 50
62 reg_usb_h1_vbus: usb_h1_vbus { 51 reg_usb_h1_vbus: usb_h1_vbus {
63 compatible = "regulator-fixed"; 52 compatible = "regulator-fixed";
64 regulator-name = "usb_h1_vbus"; 53 regulator-name = "usb_h1_vbus";
65 regulator-min-microvolt = <5000000>; 54 regulator-min-microvolt = <5000000>;
66 regulator-max-microvolt = <5000000>; 55 regulator-max-microvolt = <5000000>;
67 gpio = <&gpio1 29 0>; 56 gpio = <&gpio1 26 0>;
68 enable-active-high; 57 enable-active-high;
69 }; 58 };
70 59
60 reg_1p8v: 1p8v {
61 compatible = "regulator-fixed";
62 regulator-name = "1P8V";
63 regulator-min-microvolt = <1800000>;
64 regulator-max-microvolt = <1800000>;
65 regulator-always-on;
66 };
67
71 reg_2p5v: 2p5v { 68 reg_2p5v: 2p5v {
72 compatible = "regulator-fixed"; 69 compatible = "regulator-fixed";
73 regulator-name = "2P5V"; 70 regulator-name = "2P5V";
74 regulator-min-microvolt = <2500000>; 71 regulator-min-microvolt = <2500000>;
75 regulator-max-microvolt = <2500000>; 72 regulator-max-microvolt = <2500000>;
76 regulator-always-on; 73 regulator-always-on;
77 }; 74 };
78 75
79 reg_3p3v: 3p3v { 76 reg_3p3v: 3p3v {
80 compatible = "regulator-fixed"; 77 compatible = "regulator-fixed";
81 regulator-name = "3P3V"; 78 regulator-name = "3P3V";
82 regulator-min-microvolt = <3300000>; 79 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>; 80 regulator-max-microvolt = <3300000>;
84 regulator-always-on; 81 regulator-always-on;
85 }; 82 };
86 83
87 reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
88 compatible = "regulator-fixed";
89 regulator-name = "mipi_dsi_pwr_on";
90 gpio = <&gpio6 14 0>;
91 enable-active-high;
92 };
93
94 reg_sensor: sensor_supply { 84 reg_sensor: sensor_supply {
95 compatible = "regulator-fixed"; 85 compatible = "regulator-fixed";
96 regulator-name = "sensor-supply"; 86 regulator-name = "sensor-supply";
97 regulator-min-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>;
98 regulator-max-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>;
99 gpio = <&gpio2 31 0>; 89 gpio = <&gpio2 31 0>;
100 startup-delay-us = <500>; 90 startup-delay-us = <500>;
101 enable-active-high; 91 enable-active-high;
102 }; 92 };
103 }; 93 };
104 94
105 sound { 95 sound {
106 compatible = "fsl,imx6q-sabrelite-sgtl5000", 96 compatible = "fsl,imx6q-sabrelite-sgtl5000",
107 "fsl,imx-audio-sgtl5000"; 97 "fsl,imx-audio-sgtl5000";
108 model = "sgtl5000 sound card"; 98 model = "sgtl5000 sound card";
109 cpu-dai = <&ssi1>; 99 cpu-dai = <&ssi1>;
110 audio-codec = <&codec>; 100 audio-codec = <&codec>;
111 audio-routing = 101 audio-routing =
112 "MIC_IN", "Mic Jack", 102 "MIC_IN", "Mic Jack",
113 "Mic Jack", "Mic Bias", 103 "Mic Jack", "Mic Bias",
114 "Headphone Jack", "HP_OUT"; 104 "Headphone Jack", "HP_OUT";
115 mux-int-port = <1>; 105 mux-int-port = <1>;
116 mux-ext-port = <3>; 106 mux-ext-port = <3>;
117 }; 107 };
118 108
109 sound-spdif {
110 compatible = "fsl,imx-audio-spdif";
111 model = "imx-spdif";
112 spdif-controller = <&spdif>;
113 spdif-in;
114 spdif-out;
115 };
116
119 sound-hdmi { 117 sound-hdmi {
120 compatible = "fsl,imx6q-audio-hdmi", 118 compatible = "fsl,imx6q-audio-hdmi",
121 "fsl,imx-audio-hdmi"; 119 "fsl,imx-audio-hdmi";
122 model = "imx-audio-hdmi"; 120 model = "imx-audio-hdmi";
123 hdmi-controller = <&hdmi_audio>; 121 hdmi-controller = <&hdmi_audio>;
124 }; 122 };
125 123
126 mxcfb1: fb@0 { 124 mxcfb1: fb@0 {
127 compatible = "fsl,mxc_sdc_fb"; 125 compatible = "fsl,mxc_sdc_fb";
128 disp_dev = "ldb"; 126 disp_dev = "ldb";
129 interface_pix_fmt = "RGB666"; 127 interface_pix_fmt = "RGB24";
130 default_bpp = <16>; 128 default_bpp = <24>;
131 int_clk = <0>; 129 int_clk = <0>;
132 late_init = <0>; 130 late_init = <0>;
133 status = "disabled"; 131 status = "disabled";
134 }; 132 };
135 133
136 mxcfb2: fb@1 { 134 mxcfb2: fb@1 {
137 compatible = "fsl,mxc_sdc_fb"; 135 compatible = "fsl,mxc_sdc_fb";
138 disp_dev = "hdmi"; 136 disp_dev = "hdmi";
139 interface_pix_fmt = "RGB24"; 137 interface_pix_fmt = "RGB24";
140 mode_str ="1920x1080M@60"; 138 mode_str ="1920x1080M@60";
141 default_bpp = <24>; 139 default_bpp = <24>;
142 int_clk = <0>; 140 int_clk = <0>;
143 late_init = <0>; 141 late_init = <0>;
144 status = "disabled"; 142 status = "disabled";
145 }; 143 };
146 144
147 mxcfb3: fb@2 { 145 mxcfb3: fb@2 {
148 compatible = "fsl,mxc_sdc_fb"; 146 compatible = "fsl,mxc_sdc_fb";
149 disp_dev = "lcd"; 147 disp_dev = "lcd";
150 interface_pix_fmt = "RGB565"; 148 interface_pix_fmt = "RGB24";
151 mode_str ="CLAA-WVGA"; 149 mode_str ="CLAA-WVGA";
152 default_bpp = <16>; 150 default_bpp = <16>;
153 int_clk = <0>; 151 int_clk = <0>;
154 late_init = <0>; 152 late_init = <0>;
155 status = "disabled"; 153 status = "disabled";
156 }; 154 };
157 155
158 mxcfb4: fb@3 { 156 mxcfb4: fb@3 {
159 compatible = "fsl,mxc_sdc_fb"; 157 compatible = "fsl,mxc_sdc_fb";
160 disp_dev = "ldb"; 158 disp_dev = "ldb";
161 interface_pix_fmt = "RGB666"; 159 interface_pix_fmt = "RGB24";
162 default_bpp = <16>; 160 default_bpp = <24>;
163 int_clk = <0>; 161 int_clk = <0>;
164 late_init = <0>; 162 late_init = <0>;
165 status = "disabled"; 163 status = "disabled";
166 }; 164 };
167 165
168 lcd@0 { 166 lcd@0 {
169 compatible = "fsl,lcd"; 167 compatible = "fsl,lcd";
170 ipu_id = <0>; 168 ipu_id = <0>;
171 disp_id = <0>; 169 disp_id = <0>;
172 default_ifmt = "RGB565"; 170 default_ifmt = "RGB24";
173 pinctrl-names = "default"; 171 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_ipu1_1>; 172 pinctrl-0 = <&pinctrl_ipu1_1>;
175 status = "okay"; 173 status = "okay";
176 }; 174 };
177 175
178 backlight { 176 backlight {
179 compatible = "pwm-backlight"; 177 compatible = "pwm-backlight";
180 pwms = <&pwm2 0 5000000>; 178 pwms = <&pwm2 0 5000000>;
181 brightness-levels = <0 4 8 16 32 64 128 255>; 179 brightness-levels = <0 4 8 16 32 64 128 255>;
180 /*set default brightness level to 7, 7 is the brightest*/
182 default-brightness-level = <7>; 181 default-brightness-level = <7>;
183 }; 182 };
184 183
185 v4l2_cap_0 { 184 v4l2_cap_0 {
186 compatible = "fsl,imx6q-v4l2-capture"; 185 compatible = "fsl,imx6q-v4l2-capture";
187 ipu_id = <0>; 186 ipu_id = <0>;
188 csi_id = <0>; 187 csi_id = <0>;
189 mclk_source = <0>; 188 mclk_source = <0>;
190 status = "okay"; 189 status = "disabled";
191 }; 190 };
192 191
193 v4l2_cap_1 { 192 v4l2_cap_1 {
194 compatible = "fsl,imx6q-v4l2-capture"; 193 compatible = "fsl,imx6q-v4l2-capture";
195 ipu_id = <0>; 194 ipu_id = <0>;
196 csi_id = <1>; 195 csi_id = <1>;
197 mclk_source = <0>; 196 mclk_source = <0>;
198 status = "okay"; 197 status = "disabled";
199 }; 198 };
200 199
201 v4l2_out { 200 v4l2_out {
202 compatible = "fsl,mxc_v4l2_output"; 201 compatible = "fsl,mxc_v4l2_output";
203 status = "okay"; 202 status = "disabled";
204 }; 203 };
205 204
206 mipi_dsi_reset: mipi-dsi-reset { 205 mipi_csi_reset: mipi-csi-reset {
207 compatible = "gpio-reset"; 206 compatible = "gpio-reset";
208 reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 207 reset-gpios = <&gpio2 06 GPIO_ACTIVE_LOW>,<&gpio2 03 GPIO_ACTIVE_LOW>; /*GPIO2 and GPIO3*/
209 reset-delay-us = <50>; 208 reset-delay-us = <50>;
210 #reset-cells = <0>; 209 #reset-cells = <0>;
211 }; 210 };
212 }; 211 };
213 212
214 &audmux { 213 &audmux {
215 pinctrl-names = "default"; 214 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_audmux_2>; 215 pinctrl-0 = <&pinctrl_audmux_2>;
217 status = "okay"; 216 status = "okay";
218 }; 217 };
219 218
220 &cpu0 { 219 &cpu0 {
221 arm-supply = <&sw1a_reg>; 220 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
222 soc-supply = <&sw1c_reg>;
223 pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
224 }; 221 };
225 222
223 &ecspi1 {
224 fsl,spi-num-chipselects = <2>;
225 cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>, <&gpio4 10 GPIO_ACTIVE_HIGH>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_ecspi1_2 &pinctrl_ecspi1_cs_2>;
228 status = "okay";
229
230 spidev@0x00 {
231 compatible = "spidev";
232 spi-max-frequency = <16000000>;
233 reg = <0>;
234 };
235 spidev@0x01 {
236 compatible = "spidev";
237 spi-max-frequency = <16000000>;
238 reg = <1>;
239 };
240 };
241
226 &ecspi2 { 242 &ecspi2 {
227 fsl,spi-num-chipselects = <3>; 243 fsl,spi-num-chipselects = <4>;
228 cs-gpios = <&gpio5 29 0>, <&gpio3 24 0>, <&gpio3 25 0>; 244 cs-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>,<&gpio3 24 GPIO_ACTIVE_HIGH>,<&gpio3 25 GPIO_ACTIVE_HIGH>,<0>;
229 pinctrl-names = "default"; 245 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_ecspi2_1>, <&pinctrl_ecspi2_cs_1>; 246 pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>;
231 status = "okay"; 247 status = "okay";
232 248
233 flash: mx25u3235f0@0 { 249 flash: mx25u3235f0@0 {
234 #address-cells = <1>; 250 #address-cells = <1>;
235 #size-cells = <1>; 251 #size-cells = <1>;
236 compatible = "macronix,mx25u3235f"; 252 compatible = "macronix,mx25u3235f";
237 spi-max-frequency = <16000000>; 253 spi-max-frequency = <16000000>;
238 reg = <0>; 254 reg = <0>;
239 partition@0 { 255 partition@0 {
240 label = "U-Boot"; 256 label = "U-Boot";
241 reg = <0x0 0x100000>; 257 reg = <0x0 0x100000>;
242 }; 258 };
243 259
244 partition@100000 { 260 partition@100000 {
245 label = "U-Boot Environment"; 261 label = "U-Boot Environment";
246 reg = <0x100000 0x080000>; 262 reg = <0x100000 0x080000>;
247 }; 263 };
248 264
249 partition@180000 { 265 partition@180000 {
250 label = "Flattened Device Tree"; 266 label = "Flattened Device Tree";
251 reg = <0x180000 0x200000>; 267 reg = <0x180000 0x200000>;
252 }; 268 };
253 269
254 }; 270 };
255 };
256 271
257 &ecspi1 { 272 spidev@0x02 {
258 fsl,spi-num-chipselects = <2>; 273 #address-cells = <1>;
259 cs-gpios = <&gpio4 9 0>, <&gpio4 10 0>; 274 #size-cells = <0>;
260 pinctrl-names = "default"; 275 compatible = "spidev";
261 pinctrl-0 = <&pinctrl_ecspi1_2>, <&pinctrl_ecspi1_cs_2>; 276 reg = <2>;
262 status = "okay"; 277 spi-max-frequency = <16000000>;
263 278 };
264 spidev@0x00 { 279
265 compatible = "spidev"; 280 spidev@0x03 {
266 spi-max-frequency = <20000000>; 281 #address-cells = <1>;
267 reg = <0>; 282 #size-cells = <0>;
268 }; 283 compatible = "spidev";
269 spidev@0x01 { 284 reg = <3>;
270 compatible = "spidev"; 285 spi-max-frequency = <16000000>;
271 spi-max-frequency = <20000000>; 286 };
272 reg = <1>;
273 };
274 }; 287 };
275 288
276 &fec { 289 &fec {
277 pinctrl-names = "default"; 290 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_enet_1>, <&pinctrl_enet_irq>; 291 pinctrl-0 = <&pinctrl_enet_1>, <&pinctrl_enet_irq>;
279 /*interrupts-extended = <&gpio4 11 0x04>, <&intc 0 119 0x04>;*/
280 phy-mode = "rgmii"; 292 phy-mode = "rgmii";
293 fsl,magic-packet;
281 status = "okay"; 294 status = "okay";
282 }; 295 };
283 296
284 &gpc { 297 &gpc {
285 fsl,cpu_pupscr_sw2iso = <0xf>; 298 /* use ldo-enable, u-boot will check it and configure */
286 fsl,cpu_pupscr_sw = <0xf>; 299 fsl,ldo-bypass = <1>;
287 fsl,cpu_pdnscr_iso2sw = <0x1>; 300 /* watchdog select of reset source */
288 fsl,cpu_pdnscr_iso = <0x1>; 301 fsl,wdog-reset = <1>;
289 fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ 302 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
290 fsl,wdog-reset = <2>; /* watchdog select of reset source */
291 pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
292 }; 303 };
293 304
294 /*&wdog1 {
295 status = "disabled";
296 };
297
298 &wdog2 {
299 status = "okay";
300 };*/
301
302 &gpu { 305 &gpu {
303 pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */ 306 pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
304 }; 307 };
305 308
306 &hdmi_audio { 309 &hdmi_audio {
307 status = "okay"; 310 status = "okay";
308 }; 311 };
309 312
310 /*&hdmi_cec { 313 &hdmi_cec {
311 pinctrl-names = "default"; 314 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_hdmi_cec_2>; 315 /*pinctrl-0 = <&pinctrl_hdmi_cec_2>;*/
313 status = "okay"; 316 status = "okay";
314 };*/ 317 };
315 318
316 &hdmi_core { 319 &hdmi_core {
317 ipu_id = <0>; 320 ipu_id = <0>;
318 disp_id = <0>; 321 disp_id = <1>;
319 status = "okay"; 322 status = "okay";
320 }; 323 };
321 324
322 &hdmi_video { 325 &hdmi_video {
323 fsl,phy_reg_vlev = <0x0294>; 326 fsl,phy_reg_vlev = <0x0294>;
324 fsl,phy_reg_cksymtx = <0x800d>; 327 fsl,phy_reg_cksymtx = <0x800d>;
325 status = "okay"; 328 status = "okay";
326 }; 329 };
327 330
328 &i2c1 { 331 &i2c1 {
329 clock-frequency = <100000>; 332 clock-frequency = <100000>;
330 pinctrl-names = "default"; 333 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_i2c1_1>; 334 pinctrl-0 = <&pinctrl_i2c1_1>;
332 status = "okay"; 335 status = "okay";
333 336
334 baseboard_eeprom: baseboard_eeprom@50 { 337 baseboard_eeprom: baseboard_eeprom@50 {
335 compatible = "at,24c256"; 338 compatible = "at,24c256";
336 reg = <0x50>; 339 reg = <0x50>;
337 }; 340 };
338 341
339 codec: sgtl5000@0a { 342 codec: sgtl5000@0a {
340 compatible = "fsl,sgtl5000"; 343 compatible = "fsl,sgtl5000";
341 reg = <0x0a>; 344 reg = <0x0a>;
342 clocks = <&clks 201>; 345 clocks = <&clks 201>;
343 VDDA-supply = <&reg_2p5v>; 346 VDDA-supply = <&reg_2p5v>;
344 VDDIO-supply = <&reg_3p3v>; 347 VDDIO-supply = <&reg_3p3v>;
348 VDDD-supply = <&reg_1p8v>;
345 }; 349 };
346 350
347 s35390a: s35390a@30 { 351 s35390a: s35390a@30 {
348 compatible = "s35390a"; 352 compatible = "s35390a";
349 reg = <0x30>; 353 reg = <0x30>;
350 }; 354 };
351 355
352 cape_eeprom0: cape_eeprom@57 { 356 cape_eeprom0: cape_eeprom@57 {
353 compatible = "at,24c256"; 357 compatible = "at,24c256";
354 reg = <0x57>; 358 reg = <0x57>;
355 }; 359 };
360
361 bq2477x@09 {
362 compatible = "ti,bq2477x";
363 reg = <0x09>;
364 ti,dac-ichg = <2240>;
365 ti,dac-v = <9008>;
366 ti,dac-minsv = <4608>;
367 ti,dac-iin = <4992>;
368 ti,wdt-refresh-timeout = <40>;
369 ti,charger-detect-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
370 };
356 }; 371 };
357 372
358 &i2c2 { 373 &i2c2 {
359 clock-frequency = <100000>; 374 clock-frequency = <100000>;
360 pinctrl-names = "default"; 375 pinctrl-names = "default";
361 pinctrl-0 = <&pinctrl_i2c2_2>; 376 pinctrl-0 = <&pinctrl_i2c2_2>;
362 status = "okay"; 377 status = "okay";
363 378
364 hdmi: edid@50 { 379 hdmi: edid@50 {
365 compatible = "fsl,imx6-hdmi-i2c"; 380 compatible = "fsl,imx6-hdmi-i2c";
366 reg = <0x50>; 381 reg = <0x50>;
367 }; 382 };
368 }; 383 };
369 384
370 &i2c3 { 385 &i2c3 {
371 clock-frequency = <100000>; 386 clock-frequency = <100000>;
372 pinctrl-names = "default"; 387 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_i2c3_1>; 388 pinctrl-0 = <&pinctrl_i2c3_1>;
374 status = "okay"; 389 status = "okay";
375 390
376 i2c-switch@70 { 391 i2c-switch@70 {
377 compatible = "nxp,pca9545"; 392 compatible = "nxp,pca9545";
378 #address-cells = <1>; 393 #address-cells = <1>;
379 #size-cells = <0>; 394 #size-cells = <0>;
380 reg = <0x70>; 395 reg = <0x70>;
381
382 i2c@0 {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "nxp,pca954x-bus";
386 reg = <0>;
387
388 /*eeprom@54 {
389 compatible = "at,24c08";
390 reg = <0x54>;
391 };*/
392 };
393 396
394 i2c@1 { 397 i2c@0 {
395 #address-cells = <1>; 398 #address-cells = <1>;
396 #size-cells = <0>; 399 #size-cells = <0>;
397 compatible = "nxp,pca954x-bus"; 400 compatible = "nxp,pca954x-bus";
398 reg = <1>; 401 reg = <0>;
399
400 /* Example to add new i2c device */
401 /*rtc@51 {
402 compatible = "nxp,pcf8563";
403 reg = <0x51>;
404 };*/
405 };
406 402
403 /*eeprom@54 {
404 compatible = "at,24c08";
405 reg = <0x54>;
406 };*/
407 };
408
409 i2c@1 {
410 #address-cells = <1>;
411 #size-cells = <0>;
412 compatible = "nxp,pca954x-bus";
413 reg = <1>;
414
415 /* Example to add new i2c device */
416 /*rtc@51 {
417 compatible = "nxp,pcf8563";
418 reg = <0x51>;
419 };*/
420 eeprom@76 {
421 compatible = "at,24c256";
422 reg = <0x76>;
423 };
424 };
425
407 i2c@2 { 426 i2c@2 {
408 #address-cells = <1>; 427 #address-cells = <1>;
409 #size-cells = <0>; 428 #size-cells = <0>;
410 compatible = "nxp,pca954x-bus"; 429 compatible = "nxp,pca954x-bus";
411 reg = <2>; 430 reg = <2>;
412 }; 431 };
413 i2c@3 { 432 i2c@3 {
414 #address-cells = <1>; 433 #address-cells = <1>;
415 #size-cells = <0>; 434 #size-cells = <0>;
416 compatible = "nxp,pca954x-bus"; 435 compatible = "nxp,pca954x-bus";
417 reg = <3>; 436 reg = <3>;
418 }; 437 };
419 }; 438 };
420 }; 439 };
421 440
422 &iomuxc { 441 &iomuxc {
423 pinctrl-names = "default"; 442 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_hog_1>; 443 pinctrl-0 = <&pinctrl_hog_1>;
425 444
426 hog { 445 hog {
427 pinctrl_hog_1: hoggrp-1 { 446 pinctrl_hog_1: hoggrp-1 {
428 fsl,pins = < 447 fsl,pins = <
429 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 448 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
430 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 449 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
431 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 450 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000
432 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 451 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
433 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 452 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
434 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 453 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
435 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 454 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000
436 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 455 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000
437 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 456 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
438 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 457 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
439 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 458 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
440 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 459 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
441 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 460 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000
442 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 461 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
443 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 462 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
444 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 463 MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000
445 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 464 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
446 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 465 /*MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000*/
447 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 466 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
448 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 467 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
449 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 468 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
450 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 469 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
451 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 470 MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000
452 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 471 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
453 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 472 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
454 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 473 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0
455 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
456 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
457 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
458 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
459 MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
460 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0
461 >; 474 >;
462 }; 475 };
463 }; 476 };
464 }; 477 };
465 478
466 &ldb {
467 status = "okay";
468
469 lvds-channel@0 {
470 fsl,data-mapping = "spwg";
471 fsl,data-width = <18>;
472 status = "okay";
473
474 display-timings {
475 native-mode = <&timing0>;
476 timing0: hsd100pxn1 {
477 clock-frequency = <65000000>;
478 hactive = <1024>;
479 vactive = <768>;
480 hback-porch = <220>;
481 hfront-porch = <40>;
482 vback-porch = <21>;
483 vfront-porch = <7>;
484 hsync-len = <60>;
485 vsync-len = <10>;
486 };
487 };
488 };
489
490 lvds-channel@1 {
491 fsl,data-mapping = "spwg";
492 fsl,data-width = <18>;
493 primary;
494 status = "okay";
495
496 display-timings {
497 native-mode = <&timing1>;
498 timing1: hsd100pxn1 {
499 clock-frequency = <65000000>;
500 hactive = <1024>;
501 vactive = <768>;
502 hback-porch = <220>;
503 hfront-porch = <40>;
504 vback-porch = <21>;
505 vfront-porch = <7>;
506 hsync-len = <60>;
507 vsync-len = <10>;
508 };
509 };
510 };
511 };
512
513 &mipi_csi { 479 &mipi_csi {
514 status = "okay"; 480 status = "disabled";
515 ipu_id = <0>; 481 ipu_id = <0>;
516 csi_id = <1>; 482 csi_id = <1>;
517 v_channel = <0>; 483 v_channel = <0>;
518 lanes = <2>; 484 resets = <&mipi_csi_reset>;
485 lanes = <4>;
519 }; 486 };
520 487
521 &mipi_dsi {
522 dev_id = <0>;
523 disp_id = <1>;
524 lcd_panel = "TRULY-WVGA";
525 disp-power-on-supply = <&reg_mipi_dsi_pwr_on>;
526 resets = <&mipi_dsi_reset>;
527 status = "okay";
528 };
529
530 &dcic1 { 488 &dcic1 {
531 dcic_id = <0>; 489 dcic_id = <0>;
532 dcic_mux = "dcic-hdmi"; 490 dcic_mux = "dcic-hdmi";
533 status = "okay"; 491 status = "okay";
534 }; 492 };
535 493
536 &dcic2 { 494 &dcic2 {
537 dcic_id = <1>; 495 dcic_id = <1>;
538 dcic_mux = "dcic-lvds1"; 496 dcic_mux = "dcic-lvds1";
539 status = "okay"; 497 status = "okay";
540 }; 498 };
541 499
542 &pcie { 500 &pcie {
543 power-on-gpio = <&gpio3 19 0>; 501 /*power-on-gpio = <&gpio1 17 0>;*/
544 reset-gpio = <&gpio7 12 0>; 502 reset-gpio = <&gpio1 20 0>;
545 status = "okay"; 503 reset-delay-us = <50>;
504 status = "okay";
546 }; 505 };
547 506
507 &spdif {
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_spdif_2>;
510 status = "okay";
511 };
548 512
513 &pwm1 {
514 pinctrl-names = "default";
515 pinctrl-0 = <&pinctrl_pwm1_1>;
516 status = "okay";
517 };
518
549 &pwm2 { 519 &pwm2 {
550 pinctrl-names = "default"; 520 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_pwm2_1>; 521 pinctrl-0 = <&pinctrl_pwm2_1>;
552 status = "okay"; 522 status = "okay";
553 }; 523 };
554 524
555 &ssi1 { 525 &ssi1 {
556 fsl,mode = "i2s-slave"; 526 fsl,mode = "i2s-slave";
557 status = "okay"; 527 status = "okay";
558 }; 528 };
559 529
560 &uart1 { 530 &uart1 {
arch/arm/configs/smarcfimx6_defconfig
Diff comments   View file @ 8f7b130
1 # 1 #
2 # Automatically generated file; DO NOT EDIT. 2 # Automatically generated file; DO NOT EDIT.
3 # Linux/arm 3.10.53 Kernel Configuration 3 # Linux/arm 3.10.53 Kernel Configuration
4 # 4 #
5 CONFIG_ARM=y 5 CONFIG_ARM=y
6 CONFIG_MIGHT_HAVE_PCI=y 6 CONFIG_MIGHT_HAVE_PCI=y
7 CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8 CONFIG_HAVE_PROC_CPU=y 8 CONFIG_HAVE_PROC_CPU=y
9 CONFIG_STACKTRACE_SUPPORT=y 9 CONFIG_STACKTRACE_SUPPORT=y
10 CONFIG_LOCKDEP_SUPPORT=y 10 CONFIG_LOCKDEP_SUPPORT=y
11 CONFIG_TRACE_IRQFLAGS_SUPPORT=y 11 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
12 CONFIG_RWSEM_GENERIC_SPINLOCK=y 12 CONFIG_RWSEM_GENERIC_SPINLOCK=y
13 CONFIG_ARCH_HAS_CPUFREQ=y 13 CONFIG_ARCH_HAS_CPUFREQ=y
14 CONFIG_GENERIC_HWEIGHT=y 14 CONFIG_GENERIC_HWEIGHT=y
15 CONFIG_GENERIC_CALIBRATE_DELAY=y 15 CONFIG_GENERIC_CALIBRATE_DELAY=y
16 CONFIG_ZONE_DMA=y 16 CONFIG_ZONE_DMA=y
17 CONFIG_NEED_DMA_MAP_STATE=y 17 CONFIG_NEED_DMA_MAP_STATE=y
18 CONFIG_FIQ=y 18 CONFIG_FIQ=y
19 CONFIG_VECTORS_BASE=0xffff0000 19 CONFIG_VECTORS_BASE=0xffff0000
20 CONFIG_ARM_PATCH_PHYS_VIRT=y 20 CONFIG_ARM_PATCH_PHYS_VIRT=y
21 CONFIG_GENERIC_BUG=y 21 CONFIG_GENERIC_BUG=y
22 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 22 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
23 CONFIG_IRQ_WORK=y 23 CONFIG_IRQ_WORK=y
24 CONFIG_BUILDTIME_EXTABLE_SORT=y 24 CONFIG_BUILDTIME_EXTABLE_SORT=y
25 25
26 # 26 #
27 # General setup 27 # General setup
28 # 28 #
29 CONFIG_INIT_ENV_ARG_LIMIT=32 29 CONFIG_INIT_ENV_ARG_LIMIT=32
30 CONFIG_CROSS_COMPILE="" 30 CONFIG_CROSS_COMPILE=""
31 CONFIG_LOCALVERSION="" 31 CONFIG_LOCALVERSION=""
32 CONFIG_LOCALVERSION_AUTO=y 32 CONFIG_LOCALVERSION_AUTO=y
33 CONFIG_HAVE_KERNEL_GZIP=y 33 CONFIG_HAVE_KERNEL_GZIP=y
34 CONFIG_HAVE_KERNEL_LZMA=y 34 CONFIG_HAVE_KERNEL_LZMA=y
35 CONFIG_HAVE_KERNEL_XZ=y 35 CONFIG_HAVE_KERNEL_XZ=y
36 CONFIG_HAVE_KERNEL_LZO=y 36 CONFIG_HAVE_KERNEL_LZO=y
37 # CONFIG_KERNEL_GZIP is not set 37 # CONFIG_KERNEL_GZIP is not set
38 # CONFIG_KERNEL_LZMA is not set 38 # CONFIG_KERNEL_LZMA is not set
39 # CONFIG_KERNEL_XZ is not set 39 # CONFIG_KERNEL_XZ is not set
40 CONFIG_KERNEL_LZO=y 40 CONFIG_KERNEL_LZO=y
41 CONFIG_DEFAULT_HOSTNAME="(none)" 41 CONFIG_DEFAULT_HOSTNAME="(none)"
42 CONFIG_SWAP=y 42 CONFIG_SWAP=y
43 CONFIG_SYSVIPC=y 43 CONFIG_SYSVIPC=y
44 CONFIG_SYSVIPC_SYSCTL=y 44 CONFIG_SYSVIPC_SYSCTL=y
45 # CONFIG_POSIX_MQUEUE is not set 45 # CONFIG_POSIX_MQUEUE is not set
46 # CONFIG_FHANDLE is not set 46 # CONFIG_FHANDLE is not set
47 # CONFIG_AUDIT is not set 47 # CONFIG_AUDIT is not set
48 CONFIG_HAVE_GENERIC_HARDIRQS=y 48 CONFIG_HAVE_GENERIC_HARDIRQS=y
49 49
50 # 50 #
51 # IRQ subsystem 51 # IRQ subsystem
52 # 52 #
53 CONFIG_GENERIC_HARDIRQS=y 53 CONFIG_GENERIC_HARDIRQS=y
54 CONFIG_GENERIC_IRQ_PROBE=y 54 CONFIG_GENERIC_IRQ_PROBE=y
55 CONFIG_GENERIC_IRQ_SHOW=y 55 CONFIG_GENERIC_IRQ_SHOW=y
56 CONFIG_HARDIRQS_SW_RESEND=y 56 CONFIG_HARDIRQS_SW_RESEND=y
57 CONFIG_GENERIC_IRQ_CHIP=y 57 CONFIG_GENERIC_IRQ_CHIP=y
58 CONFIG_IRQ_DOMAIN=y 58 CONFIG_IRQ_DOMAIN=y
59 # CONFIG_IRQ_DOMAIN_DEBUG is not set 59 # CONFIG_IRQ_DOMAIN_DEBUG is not set
60 CONFIG_SPARSE_IRQ=y 60 CONFIG_SPARSE_IRQ=y
61 CONFIG_KTIME_SCALAR=y 61 CONFIG_KTIME_SCALAR=y
62 CONFIG_GENERIC_CLOCKEVENTS=y 62 CONFIG_GENERIC_CLOCKEVENTS=y
63 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 63 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
64 CONFIG_ARCH_HAS_TICK_BROADCAST=y 64 CONFIG_ARCH_HAS_TICK_BROADCAST=y
65 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y 65 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
66 66
67 # 67 #
68 # Timers subsystem 68 # Timers subsystem
69 # 69 #
70 CONFIG_TICK_ONESHOT=y 70 CONFIG_TICK_ONESHOT=y
71 CONFIG_NO_HZ_COMMON=y 71 CONFIG_NO_HZ_COMMON=y
72 # CONFIG_HZ_PERIODIC is not set 72 # CONFIG_HZ_PERIODIC is not set
73 CONFIG_NO_HZ_IDLE=y 73 CONFIG_NO_HZ_IDLE=y
74 CONFIG_NO_HZ=y 74 CONFIG_NO_HZ=y
75 CONFIG_HIGH_RES_TIMERS=y 75 CONFIG_HIGH_RES_TIMERS=y
76 76
77 # 77 #
78 # CPU/Task time and stats accounting 78 # CPU/Task time and stats accounting
79 # 79 #
80 CONFIG_TICK_CPU_ACCOUNTING=y 80 CONFIG_TICK_CPU_ACCOUNTING=y
81 # CONFIG_IRQ_TIME_ACCOUNTING is not set 81 # CONFIG_IRQ_TIME_ACCOUNTING is not set
82 # CONFIG_BSD_PROCESS_ACCT is not set 82 # CONFIG_BSD_PROCESS_ACCT is not set
83 # CONFIG_TASKSTATS is not set 83 # CONFIG_TASKSTATS is not set
84 84
85 # 85 #
86 # RCU Subsystem 86 # RCU Subsystem
87 # 87 #
88 CONFIG_TREE_PREEMPT_RCU=y 88 CONFIG_TREE_PREEMPT_RCU=y
89 CONFIG_PREEMPT_RCU=y 89 CONFIG_PREEMPT_RCU=y
90 CONFIG_RCU_STALL_COMMON=y 90 CONFIG_RCU_STALL_COMMON=y
91 # CONFIG_RCU_USER_QS is not set 91 # CONFIG_RCU_USER_QS is not set
92 CONFIG_RCU_FANOUT=32 92 CONFIG_RCU_FANOUT=32
93 CONFIG_RCU_FANOUT_LEAF=16 93 CONFIG_RCU_FANOUT_LEAF=16
94 # CONFIG_RCU_FANOUT_EXACT is not set 94 # CONFIG_RCU_FANOUT_EXACT is not set
95 # CONFIG_RCU_FAST_NO_HZ is not set 95 # CONFIG_RCU_FAST_NO_HZ is not set
96 # CONFIG_TREE_RCU_TRACE is not set 96 # CONFIG_TREE_RCU_TRACE is not set
97 # CONFIG_RCU_BOOST is not set 97 # CONFIG_RCU_BOOST is not set
98 # CONFIG_RCU_NOCB_CPU is not set 98 # CONFIG_RCU_NOCB_CPU is not set
99 CONFIG_IKCONFIG=y 99 CONFIG_IKCONFIG=y
100 CONFIG_IKCONFIG_PROC=y 100 CONFIG_IKCONFIG_PROC=y
101 CONFIG_LOG_BUF_SHIFT=18 101 CONFIG_LOG_BUF_SHIFT=18
102 CONFIG_CGROUPS=y 102 CONFIG_CGROUPS=y
103 # CONFIG_CGROUP_DEBUG is not set 103 # CONFIG_CGROUP_DEBUG is not set
104 # CONFIG_CGROUP_FREEZER is not set 104 # CONFIG_CGROUP_FREEZER is not set
105 # CONFIG_CGROUP_DEVICE is not set 105 # CONFIG_CGROUP_DEVICE is not set
106 # CONFIG_CPUSETS is not set 106 # CONFIG_CPUSETS is not set
107 # CONFIG_CGROUP_CPUACCT is not set 107 # CONFIG_CGROUP_CPUACCT is not set
108 # CONFIG_RESOURCE_COUNTERS is not set 108 # CONFIG_RESOURCE_COUNTERS is not set
109 # CONFIG_CGROUP_PERF is not set 109 # CONFIG_CGROUP_PERF is not set
110 # CONFIG_CGROUP_SCHED is not set 110 # CONFIG_CGROUP_SCHED is not set
111 # CONFIG_BLK_CGROUP is not set 111 # CONFIG_BLK_CGROUP is not set
112 # CONFIG_CHECKPOINT_RESTORE is not set 112 # CONFIG_CHECKPOINT_RESTORE is not set
113 # CONFIG_NAMESPACES is not set 113 # CONFIG_NAMESPACES is not set
114 CONFIG_UIDGID_CONVERTED=y 114 CONFIG_UIDGID_CONVERTED=y
115 # CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set 115 # CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
116 # CONFIG_SCHED_AUTOGROUP is not set 116 # CONFIG_SCHED_AUTOGROUP is not set
117 # CONFIG_SYSFS_DEPRECATED is not set 117 # CONFIG_SYSFS_DEPRECATED is not set
118 CONFIG_RELAY=y 118 CONFIG_RELAY=y
119 CONFIG_BLK_DEV_INITRD=y 119 CONFIG_BLK_DEV_INITRD=y
120 CONFIG_INITRAMFS_SOURCE="" 120 CONFIG_INITRAMFS_SOURCE=""
121 CONFIG_RD_GZIP=y 121 CONFIG_RD_GZIP=y
122 # CONFIG_RD_BZIP2 is not set 122 # CONFIG_RD_BZIP2 is not set
123 # CONFIG_RD_LZMA is not set 123 # CONFIG_RD_LZMA is not set
124 # CONFIG_RD_XZ is not set 124 # CONFIG_RD_XZ is not set
125 # CONFIG_RD_LZO is not set 125 # CONFIG_RD_LZO is not set
126 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 126 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
127 CONFIG_SYSCTL=y 127 CONFIG_SYSCTL=y
128 CONFIG_ANON_INODES=y 128 CONFIG_ANON_INODES=y
129 CONFIG_HAVE_UID16=y 129 CONFIG_HAVE_UID16=y
130 CONFIG_HOTPLUG=y 130 CONFIG_HOTPLUG=y
131 CONFIG_EXPERT=y 131 CONFIG_EXPERT=y
132 CONFIG_UID16=y 132 CONFIG_UID16=y
133 # CONFIG_SYSCTL_SYSCALL is not set 133 # CONFIG_SYSCTL_SYSCALL is not set
134 CONFIG_KALLSYMS=y 134 CONFIG_KALLSYMS=y
135 # CONFIG_KALLSYMS_ALL is not set 135 # CONFIG_KALLSYMS_ALL is not set
136 CONFIG_PRINTK=y 136 CONFIG_PRINTK=y
137 CONFIG_BUG=y 137 CONFIG_BUG=y
138 CONFIG_ELF_CORE=y 138 CONFIG_ELF_CORE=y
139 CONFIG_BASE_FULL=y 139 CONFIG_BASE_FULL=y
140 CONFIG_FUTEX=y 140 CONFIG_FUTEX=y
141 CONFIG_EPOLL=y 141 CONFIG_EPOLL=y
142 CONFIG_SIGNALFD=y 142 CONFIG_SIGNALFD=y
143 CONFIG_TIMERFD=y 143 CONFIG_TIMERFD=y
144 CONFIG_EVENTFD=y 144 CONFIG_EVENTFD=y
145 CONFIG_SHMEM=y 145 CONFIG_SHMEM=y
146 CONFIG_AIO=y 146 CONFIG_AIO=y
147 CONFIG_PCI_QUIRKS=y
147 # CONFIG_EMBEDDED is not set 148 # CONFIG_EMBEDDED is not set
148 CONFIG_HAVE_PERF_EVENTS=y 149 CONFIG_HAVE_PERF_EVENTS=y
149 CONFIG_PERF_USE_VMALLOC=y 150 CONFIG_PERF_USE_VMALLOC=y
150 151
151 # 152 #
152 # Kernel Performance Events And Counters 153 # Kernel Performance Events And Counters
153 # 154 #
154 CONFIG_PERF_EVENTS=y 155 CONFIG_PERF_EVENTS=y
155 # CONFIG_DEBUG_PERF_USE_VMALLOC is not set 156 # CONFIG_DEBUG_PERF_USE_VMALLOC is not set
156 CONFIG_VM_EVENT_COUNTERS=y 157 CONFIG_VM_EVENT_COUNTERS=y
157 # CONFIG_SLUB_DEBUG is not set 158 # CONFIG_SLUB_DEBUG is not set
158 # CONFIG_COMPAT_BRK is not set 159 # CONFIG_COMPAT_BRK is not set
159 # CONFIG_SLAB is not set 160 # CONFIG_SLAB is not set
160 CONFIG_SLUB=y 161 CONFIG_SLUB=y
161 # CONFIG_SLOB is not set 162 # CONFIG_SLOB is not set
162 # CONFIG_PROFILING is not set 163 # CONFIG_PROFILING is not set
163 CONFIG_HAVE_OPROFILE=y 164 CONFIG_HAVE_OPROFILE=y
164 # CONFIG_KPROBES is not set 165 # CONFIG_KPROBES is not set
165 # CONFIG_JUMP_LABEL is not set 166 # CONFIG_JUMP_LABEL is not set
166 # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set 167 # CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
167 CONFIG_HAVE_KPROBES=y 168 CONFIG_HAVE_KPROBES=y
168 CONFIG_HAVE_KRETPROBES=y 169 CONFIG_HAVE_KRETPROBES=y
169 CONFIG_HAVE_ARCH_TRACEHOOK=y 170 CONFIG_HAVE_ARCH_TRACEHOOK=y
170 CONFIG_HAVE_DMA_ATTRS=y 171 CONFIG_HAVE_DMA_ATTRS=y
171 CONFIG_HAVE_DMA_CONTIGUOUS=y 172 CONFIG_HAVE_DMA_CONTIGUOUS=y
172 CONFIG_USE_GENERIC_SMP_HELPERS=y 173 CONFIG_USE_GENERIC_SMP_HELPERS=y
173 CONFIG_GENERIC_SMP_IDLE_THREAD=y 174 CONFIG_GENERIC_SMP_IDLE_THREAD=y
174 CONFIG_GENERIC_IDLE_POLL_SETUP=y 175 CONFIG_GENERIC_IDLE_POLL_SETUP=y
175 CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y 176 CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
176 CONFIG_HAVE_CLK=y 177 CONFIG_HAVE_CLK=y
177 CONFIG_HAVE_DMA_API_DEBUG=y 178 CONFIG_HAVE_DMA_API_DEBUG=y
178 CONFIG_HAVE_HW_BREAKPOINT=y 179 CONFIG_HAVE_HW_BREAKPOINT=y
179 CONFIG_HAVE_ARCH_JUMP_LABEL=y 180 CONFIG_HAVE_ARCH_JUMP_LABEL=y
180 CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y 181 CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
181 CONFIG_HAVE_ARCH_SECCOMP_FILTER=y 182 CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
182 CONFIG_HAVE_CONTEXT_TRACKING=y 183 CONFIG_HAVE_CONTEXT_TRACKING=y
183 CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y 184 CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
184 CONFIG_HAVE_MOD_ARCH_SPECIFIC=y 185 CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
185 CONFIG_MODULES_USE_ELF_REL=y 186 CONFIG_MODULES_USE_ELF_REL=y
186 CONFIG_CLONE_BACKWARDS=y 187 CONFIG_CLONE_BACKWARDS=y
187 CONFIG_OLD_SIGSUSPEND3=y 188 CONFIG_OLD_SIGSUSPEND3=y
188 CONFIG_OLD_SIGACTION=y 189 CONFIG_OLD_SIGACTION=y
189 190
190 # 191 #
191 # GCOV-based kernel profiling 192 # GCOV-based kernel profiling
192 # 193 #
193 # CONFIG_GCOV_KERNEL is not set 194 # CONFIG_GCOV_KERNEL is not set
194 CONFIG_HAVE_GENERIC_DMA_COHERENT=y 195 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
195 CONFIG_RT_MUTEXES=y 196 CONFIG_RT_MUTEXES=y
196 CONFIG_BASE_SMALL=0 197 CONFIG_BASE_SMALL=0
197 CONFIG_MODULES=y 198 CONFIG_MODULES=y
198 # CONFIG_MODULE_FORCE_LOAD is not set 199 # CONFIG_MODULE_FORCE_LOAD is not set
199 CONFIG_MODULE_UNLOAD=y 200 CONFIG_MODULE_UNLOAD=y
200 # CONFIG_MODULE_FORCE_UNLOAD is not set 201 # CONFIG_MODULE_FORCE_UNLOAD is not set
201 CONFIG_MODVERSIONS=y 202 CONFIG_MODVERSIONS=y
202 CONFIG_MODULE_SRCVERSION_ALL=y 203 CONFIG_MODULE_SRCVERSION_ALL=y
203 # CONFIG_MODULE_SIG is not set 204 # CONFIG_MODULE_SIG is not set
204 CONFIG_STOP_MACHINE=y 205 CONFIG_STOP_MACHINE=y
205 CONFIG_BLOCK=y 206 CONFIG_BLOCK=y
206 CONFIG_LBDAF=y 207 CONFIG_LBDAF=y
207 # CONFIG_BLK_DEV_BSG is not set 208 # CONFIG_BLK_DEV_BSG is not set
208 # CONFIG_BLK_DEV_BSGLIB is not set 209 # CONFIG_BLK_DEV_BSGLIB is not set
209 # CONFIG_BLK_DEV_INTEGRITY is not set 210 # CONFIG_BLK_DEV_INTEGRITY is not set
210 211
211 # 212 #
212 # Partition Types 213 # Partition Types
213 # 214 #
214 # CONFIG_PARTITION_ADVANCED is not set 215 # CONFIG_PARTITION_ADVANCED is not set
215 CONFIG_MSDOS_PARTITION=y 216 CONFIG_MSDOS_PARTITION=y
216 CONFIG_EFI_PARTITION=y 217 CONFIG_EFI_PARTITION=y
217 218
218 # 219 #
219 # IO Schedulers 220 # IO Schedulers
220 # 221 #
221 CONFIG_IOSCHED_NOOP=y 222 CONFIG_IOSCHED_NOOP=y
222 CONFIG_IOSCHED_DEADLINE=y 223 CONFIG_IOSCHED_DEADLINE=y
223 CONFIG_IOSCHED_CFQ=y 224 CONFIG_IOSCHED_CFQ=y
224 # CONFIG_DEFAULT_DEADLINE is not set 225 # CONFIG_DEFAULT_DEADLINE is not set
225 CONFIG_DEFAULT_CFQ=y 226 CONFIG_DEFAULT_CFQ=y
226 # CONFIG_DEFAULT_NOOP is not set 227 # CONFIG_DEFAULT_NOOP is not set
227 CONFIG_DEFAULT_IOSCHED="cfq" 228 CONFIG_DEFAULT_IOSCHED="cfq"
228 CONFIG_UNINLINE_SPIN_UNLOCK=y 229 CONFIG_UNINLINE_SPIN_UNLOCK=y
229 CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y 230 CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
230 CONFIG_MUTEX_SPIN_ON_OWNER=y 231 CONFIG_MUTEX_SPIN_ON_OWNER=y
231 CONFIG_FREEZER=y 232 CONFIG_FREEZER=y
232 233
233 # 234 #
234 # System Type 235 # System Type
235 # 236 #
236 CONFIG_MMU=y 237 CONFIG_MMU=y
237 CONFIG_ARCH_MULTIPLATFORM=y 238 CONFIG_ARCH_MULTIPLATFORM=y
238 # CONFIG_ARCH_INTEGRATOR is not set 239 # CONFIG_ARCH_INTEGRATOR is not set
239 # CONFIG_ARCH_REALVIEW is not set 240 # CONFIG_ARCH_REALVIEW is not set
240 # CONFIG_ARCH_VERSATILE is not set 241 # CONFIG_ARCH_VERSATILE is not set
241 # CONFIG_ARCH_AT91 is not set 242 # CONFIG_ARCH_AT91 is not set
242 # CONFIG_ARCH_CLPS711X is not set 243 # CONFIG_ARCH_CLPS711X is not set
243 # CONFIG_ARCH_GEMINI is not set 244 # CONFIG_ARCH_GEMINI is not set
244 # CONFIG_ARCH_EBSA110 is not set 245 # CONFIG_ARCH_EBSA110 is not set
245 # CONFIG_ARCH_EP93XX is not set 246 # CONFIG_ARCH_EP93XX is not set
246 # CONFIG_ARCH_FOOTBRIDGE is not set 247 # CONFIG_ARCH_FOOTBRIDGE is not set
247 # CONFIG_ARCH_NETX is not set 248 # CONFIG_ARCH_NETX is not set
248 # CONFIG_ARCH_IOP13XX is not set 249 # CONFIG_ARCH_IOP13XX is not set
249 # CONFIG_ARCH_IOP32X is not set 250 # CONFIG_ARCH_IOP32X is not set
250 # CONFIG_ARCH_IOP33X is not set 251 # CONFIG_ARCH_IOP33X is not set
251 # CONFIG_ARCH_IXP4XX is not set 252 # CONFIG_ARCH_IXP4XX is not set
252 # CONFIG_ARCH_DOVE is not set 253 # CONFIG_ARCH_DOVE is not set
253 # CONFIG_ARCH_KIRKWOOD is not set 254 # CONFIG_ARCH_KIRKWOOD is not set
254 # CONFIG_ARCH_MV78XX0 is not set 255 # CONFIG_ARCH_MV78XX0 is not set
255 # CONFIG_ARCH_ORION5X is not set 256 # CONFIG_ARCH_ORION5X is not set
256 # CONFIG_ARCH_MMP is not set 257 # CONFIG_ARCH_MMP is not set
257 # CONFIG_ARCH_KS8695 is not set 258 # CONFIG_ARCH_KS8695 is not set
258 # CONFIG_ARCH_W90X900 is not set 259 # CONFIG_ARCH_W90X900 is not set
259 # CONFIG_ARCH_LPC32XX is not set 260 # CONFIG_ARCH_LPC32XX is not set
260 # CONFIG_ARCH_PXA is not set 261 # CONFIG_ARCH_PXA is not set
261 # CONFIG_ARCH_MSM is not set 262 # CONFIG_ARCH_MSM is not set
262 # CONFIG_ARCH_SHMOBILE is not set 263 # CONFIG_ARCH_SHMOBILE is not set
263 # CONFIG_ARCH_RPC is not set 264 # CONFIG_ARCH_RPC is not set
264 # CONFIG_ARCH_SA1100 is not set 265 # CONFIG_ARCH_SA1100 is not set
265 # CONFIG_ARCH_S3C24XX is not set 266 # CONFIG_ARCH_S3C24XX is not set
266 # CONFIG_ARCH_S3C64XX is not set 267 # CONFIG_ARCH_S3C64XX is not set
267 # CONFIG_ARCH_S5P64X0 is not set 268 # CONFIG_ARCH_S5P64X0 is not set
268 # CONFIG_ARCH_S5PC100 is not set 269 # CONFIG_ARCH_S5PC100 is not set
269 # CONFIG_ARCH_S5PV210 is not set 270 # CONFIG_ARCH_S5PV210 is not set
270 # CONFIG_ARCH_EXYNOS is not set 271 # CONFIG_ARCH_EXYNOS is not set
271 # CONFIG_ARCH_SHARK is not set 272 # CONFIG_ARCH_SHARK is not set
272 # CONFIG_ARCH_U300 is not set 273 # CONFIG_ARCH_U300 is not set
273 # CONFIG_ARCH_DAVINCI is not set 274 # CONFIG_ARCH_DAVINCI is not set
274 # CONFIG_ARCH_OMAP1 is not set 275 # CONFIG_ARCH_OMAP1 is not set
275 276
276 # 277 #
277 # Multiple platform selection 278 # Multiple platform selection
278 # 279 #
279 280
280 # 281 #
281 # CPU Core family selection 282 # CPU Core family selection
282 # 283 #
283 # CONFIG_ARCH_MULTI_V6 is not set 284 # CONFIG_ARCH_MULTI_V6 is not set
284 CONFIG_ARCH_MULTI_V7=y 285 CONFIG_ARCH_MULTI_V7=y
285 CONFIG_ARCH_MULTI_V6_V7=y 286 CONFIG_ARCH_MULTI_V6_V7=y
286 # CONFIG_ARCH_MULTI_CPU_AUTO is not set 287 # CONFIG_ARCH_MULTI_CPU_AUTO is not set
287 # CONFIG_ARCH_MVEBU is not set 288 # CONFIG_ARCH_MVEBU is not set
288 # CONFIG_ARCH_BCM is not set 289 # CONFIG_ARCH_BCM is not set
289 CONFIG_GPIO_PCA953X=y 290 CONFIG_GPIO_PCA953X=y
290 # CONFIG_KEYBOARD_GPIO_POLLED is not set 291 # CONFIG_KEYBOARD_GPIO_POLLED is not set
291 # CONFIG_ARCH_HIGHBANK is not set 292 # CONFIG_ARCH_HIGHBANK is not set
292 CONFIG_ARCH_MXC=y 293 CONFIG_ARCH_MXC=y
293 294
294 # 295 #
295 # Freescale i.MX support 296 # Freescale i.MX support
296 # 297 #
297 # CONFIG_MXC_IRQ_PRIOR is not set 298 # CONFIG_MXC_IRQ_PRIOR is not set
298 CONFIG_MXC_TZIC=y 299 CONFIG_MXC_TZIC=y
299 CONFIG_MXC_DEBUG_BOARD=y 300 CONFIG_MXC_DEBUG_BOARD=y
300 CONFIG_HAVE_IMX_RNG=y 301 CONFIG_HAVE_IMX_RNG=y
301 CONFIG_HAVE_IMX_ANATOP=y 302 CONFIG_HAVE_IMX_ANATOP=y
302 CONFIG_HAVE_IMX_GPC=y 303 CONFIG_HAVE_IMX_GPC=y
303 CONFIG_HAVE_IMX_MMDC=y 304 CONFIG_HAVE_IMX_MMDC=y
304 CONFIG_HAVE_IMX_SRC=y 305 CONFIG_HAVE_IMX_SRC=y
305 CONFIG_HAVE_IMX_MCC=y 306 CONFIG_HAVE_IMX_MCC=y
306 CONFIG_ARCH_MXC_IOMUX_V3=y 307 CONFIG_ARCH_MXC_IOMUX_V3=y
307 CONFIG_SOC_IMX5=y 308 CONFIG_SOC_IMX5=y
308 CONFIG_SOC_IMX51=y 309 CONFIG_SOC_IMX51=y
309 310
310 # 311 #
311 # i.MX51 machines: 312 # i.MX51 machines:
312 # 313 #
313 CONFIG_MACH_IMX51_DT=y 314 CONFIG_MACH_IMX51_DT=y
314 # CONFIG_MACH_MX51_BABBAGE is not set 315 # CONFIG_MACH_MX51_BABBAGE is not set
315 CONFIG_MACH_EUKREA_CPUIMX51SD=y 316 CONFIG_MACH_EUKREA_CPUIMX51SD=y
316 CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD=y 317 CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD=y
317 318
318 # 319 #
319 # Device tree only 320 # Device tree only
320 # 321 #
321 CONFIG_SOC_IMX53=y 322 CONFIG_SOC_IMX53=y
322 CONFIG_SOC_IMX6Q=y 323 CONFIG_SOC_IMX6Q=y
323 CONFIG_SOC_IMX6SL=y 324 CONFIG_SOC_IMX6SL=y
324 CONFIG_SOC_IMX6SX=y 325 CONFIG_SOC_IMX6SX=y
325 CONFIG_SOC_VF610=y 326 CONFIG_SOC_VF610=y
326 CONFIG_IMX_HAVE_PLATFORM_FEC=y 327 CONFIG_IMX_HAVE_PLATFORM_FEC=y
327 CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y 328 CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
328 CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y 329 CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
329 CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y 330 CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
330 CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y 331 CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
331 CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y 332 CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
332 CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y 333 CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
333 CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y 334 CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
334 CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y 335 CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
335 CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y 336 CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
336 CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y 337 CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
337 # CONFIG_ARCH_OMAP2PLUS is not set 338 # CONFIG_ARCH_OMAP2PLUS is not set
338 # CONFIG_ARCH_SOCFPGA is not set 339 # CONFIG_ARCH_SOCFPGA is not set
339 # CONFIG_PLAT_SPEAR is not set 340 # CONFIG_PLAT_SPEAR is not set
340 # CONFIG_ARCH_SUNXI is not set 341 # CONFIG_ARCH_SUNXI is not set
341 # CONFIG_ARCH_SIRF is not set 342 # CONFIG_ARCH_SIRF is not set
342 # CONFIG_ARCH_TEGRA is not set 343 # CONFIG_ARCH_TEGRA is not set
343 # CONFIG_ARCH_U8500 is not set 344 # CONFIG_ARCH_U8500 is not set
344 # CONFIG_ARCH_VEXPRESS is not set 345 # CONFIG_ARCH_VEXPRESS is not set
345 # CONFIG_ARCH_VIRT is not set 346 # CONFIG_ARCH_VIRT is not set
346 # CONFIG_ARCH_WM8850 is not set 347 # CONFIG_ARCH_WM8850 is not set
347 # CONFIG_ARCH_ZYNQ is not set 348 # CONFIG_ARCH_ZYNQ is not set
348 349
349 # 350 #
350 # Processor Type 351 # Processor Type
351 # 352 #
352 CONFIG_CPU_V7=y 353 CONFIG_CPU_V7=y
353 CONFIG_CPU_32v6K=y 354 CONFIG_CPU_32v6K=y
354 CONFIG_CPU_32v7=y 355 CONFIG_CPU_32v7=y
355 CONFIG_CPU_ABRT_EV7=y 356 CONFIG_CPU_ABRT_EV7=y
356 CONFIG_CPU_PABRT_V7=y 357 CONFIG_CPU_PABRT_V7=y
357 CONFIG_CPU_CACHE_V7=y 358 CONFIG_CPU_CACHE_V7=y
358 CONFIG_CPU_CACHE_VIPT=y 359 CONFIG_CPU_CACHE_VIPT=y
359 CONFIG_CPU_COPY_V6=y 360 CONFIG_CPU_COPY_V6=y
360 CONFIG_CPU_TLB_V7=y 361 CONFIG_CPU_TLB_V7=y
361 CONFIG_CPU_HAS_ASID=y 362 CONFIG_CPU_HAS_ASID=y
362 CONFIG_CPU_CP15=y 363 CONFIG_CPU_CP15=y
363 CONFIG_CPU_CP15_MMU=y 364 CONFIG_CPU_CP15_MMU=y
364 365
365 # 366 #
366 # Processor Features 367 # Processor Features
367 # 368 #
368 # CONFIG_ARM_LPAE is not set 369 # CONFIG_ARM_LPAE is not set
369 # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set 370 # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
370 CONFIG_ARM_THUMB=y 371 CONFIG_ARM_THUMB=y
371 # CONFIG_ARM_THUMBEE is not set 372 # CONFIG_ARM_THUMBEE is not set
372 CONFIG_ARM_VIRT_EXT=y 373 CONFIG_ARM_VIRT_EXT=y
373 # CONFIG_SWP_EMULATE is not set 374 # CONFIG_SWP_EMULATE is not set
374 # CONFIG_CPU_ICACHE_DISABLE is not set 375 # CONFIG_CPU_ICACHE_DISABLE is not set
375 # CONFIG_CPU_DCACHE_DISABLE is not set 376 # CONFIG_CPU_DCACHE_DISABLE is not set
376 # CONFIG_CPU_BPREDICT_DISABLE is not set 377 # CONFIG_CPU_BPREDICT_DISABLE is not set
377 CONFIG_KUSER_HELPERS=y 378 CONFIG_KUSER_HELPERS=y
378 CONFIG_OUTER_CACHE=y 379 CONFIG_OUTER_CACHE=y
379 CONFIG_OUTER_CACHE_SYNC=y 380 CONFIG_OUTER_CACHE_SYNC=y
380 CONFIG_MIGHT_HAVE_CACHE_L2X0=y 381 CONFIG_MIGHT_HAVE_CACHE_L2X0=y
381 CONFIG_CACHE_L2X0=y 382 CONFIG_CACHE_L2X0=y
382 CONFIG_CACHE_PL310=y 383 CONFIG_CACHE_PL310=y
383 CONFIG_ARM_L1_CACHE_SHIFT_6=y 384 CONFIG_ARM_L1_CACHE_SHIFT_6=y
384 CONFIG_ARM_L1_CACHE_SHIFT=6 385 CONFIG_ARM_L1_CACHE_SHIFT=6
385 CONFIG_ARM_DMA_MEM_BUFFERABLE=y 386 CONFIG_ARM_DMA_MEM_BUFFERABLE=y
386 CONFIG_ARM_NR_BANKS=8 387 CONFIG_ARM_NR_BANKS=8
387 CONFIG_MULTI_IRQ_HANDLER=y 388 CONFIG_MULTI_IRQ_HANDLER=y
388 # CONFIG_ARM_ERRATA_430973 is not set 389 # CONFIG_ARM_ERRATA_430973 is not set
389 # CONFIG_PL310_ERRATA_588369 is not set 390 # CONFIG_PL310_ERRATA_588369 is not set
390 # CONFIG_ARM_ERRATA_643719 is not set 391 # CONFIG_ARM_ERRATA_643719 is not set
391 # CONFIG_ARM_ERRATA_720789 is not set 392 # CONFIG_ARM_ERRATA_720789 is not set
392 # CONFIG_PL310_ERRATA_727915 is not set 393 # CONFIG_PL310_ERRATA_727915 is not set
393 CONFIG_ARM_ERRATA_794072=y 394 CONFIG_ARM_ERRATA_794072=y
394 CONFIG_ARM_ERRATA_761320=y 395 CONFIG_ARM_ERRATA_761320=y
395 # CONFIG_PL310_ERRATA_753970 is not set 396 # CONFIG_PL310_ERRATA_753970 is not set
396 CONFIG_ARM_ERRATA_754322=y 397 CONFIG_ARM_ERRATA_754322=y
397 # CONFIG_ARM_ERRATA_754327 is not set 398 # CONFIG_ARM_ERRATA_754327 is not set
398 CONFIG_ARM_ERRATA_764369=y 399 CONFIG_ARM_ERRATA_764369=y
399 CONFIG_PL310_ERRATA_769419=y 400 CONFIG_PL310_ERRATA_769419=y
400 CONFIG_ARM_ERRATA_775420=y 401 CONFIG_ARM_ERRATA_775420=y
401 # CONFIG_ARM_ERRATA_798181 is not set 402 # CONFIG_ARM_ERRATA_798181 is not set
402 403
403 # 404 #
404 # Bus support 405 # Bus support
405 # 406 #
406 # CONFIG_PCI is not set 407 CONFIG_PCI=y
407 # CONFIG_PCI_SYSCALL is not set 408 CONFIG_PCI_DOMAINS=y
409 CONFIG_PCI_SYSCALL=y
408 CONFIG_ARCH_SUPPORTS_MSI=y 410 CONFIG_ARCH_SUPPORTS_MSI=y
411 CONFIG_PCI_MSI=y
412 # CONFIG_PCI_DEBUG is not set
413 CONFIG_PCI_REALLOC_ENABLE_AUTO=y
414 CONFIG_PCI_STUB=y
415 CONFIG_PCI_ATS=y
416 CONFIG_PCI_IOV=y
417 CONFIG_PCI_PRI=y
418 CONFIG_PCI_PASID=y
419
420 #
421 # PCI host controller drivers
422 #
423 CONFIG_PCIE_DW=y
424 CONFIG_PCI_IMX6=y
425 # CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE is not set
426 # CONFIG_EP_MODE_IN_EP_RC_SYS is not set
427 # CONFIG_RC_MODE_IN_EP_RC_SYS is not set
428 CONFIG_PCIEPORTBUS=y
429 CONFIG_PCIEAER=y
430 CONFIG_PCIE_ECRC=y
431 CONFIG_PCIEAER_INJECT=y
432 CONFIG_PCIEASPM=y
433 # CONFIG_PCIEASPM_DEBUG is not set
434 CONFIG_PCIEASPM_DEFAULT=y
435 # CONFIG_PCIEASPM_POWERSAVE is not set
436 # CONFIG_PCIEASPM_PERFORMANCE is not set
437 CONFIG_PCIE_PME=y
409 # CONFIG_PCCARD is not set 438 # CONFIG_PCCARD is not set
410 439
411 # 440 #
412 # Kernel Features 441 # Kernel Features
413 # 442 #
414 CONFIG_HAVE_SMP=y 443 CONFIG_HAVE_SMP=y
415 CONFIG_SMP=y 444 CONFIG_SMP=y
416 CONFIG_SMP_ON_UP=y 445 CONFIG_SMP_ON_UP=y
417 CONFIG_ARM_CPU_TOPOLOGY=y 446 CONFIG_ARM_CPU_TOPOLOGY=y
418 # CONFIG_SCHED_MC is not set 447 # CONFIG_SCHED_MC is not set
419 # CONFIG_SCHED_SMT is not set 448 # CONFIG_SCHED_SMT is not set
420 CONFIG_HAVE_ARM_SCU=y 449 CONFIG_HAVE_ARM_SCU=y
421 # CONFIG_HAVE_ARM_ARCH_TIMER is not set 450 # CONFIG_HAVE_ARM_ARCH_TIMER is not set
422 CONFIG_HAVE_ARM_TWD=y 451 CONFIG_HAVE_ARM_TWD=y
423 # CONFIG_MCPM is not set 452 # CONFIG_MCPM is not set
424 # CONFIG_VMSPLIT_3G is not set 453 # CONFIG_VMSPLIT_3G is not set
425 CONFIG_VMSPLIT_2G=y 454 CONFIG_VMSPLIT_2G=y
426 # CONFIG_VMSPLIT_1G is not set 455 # CONFIG_VMSPLIT_1G is not set
427 CONFIG_PAGE_OFFSET=0x80000000 456 CONFIG_PAGE_OFFSET=0x80000000
428 CONFIG_NR_CPUS=4 457 CONFIG_NR_CPUS=4
429 CONFIG_HOTPLUG_CPU=y 458 CONFIG_HOTPLUG_CPU=y
430 # CONFIG_ARM_PSCI is not set 459 # CONFIG_ARM_PSCI is not set
431 CONFIG_LOCAL_TIMERS=y 460 CONFIG_LOCAL_TIMERS=y
432 CONFIG_ARCH_NR_GPIO=0 461 CONFIG_ARCH_NR_GPIO=0
433 # CONFIG_PREEMPT_NONE is not set 462 # CONFIG_PREEMPT_NONE is not set
434 # CONFIG_PREEMPT_VOLUNTARY is not set 463 # CONFIG_PREEMPT_VOLUNTARY is not set
435 CONFIG_PREEMPT=y 464 CONFIG_PREEMPT=y
436 CONFIG_PREEMPT_COUNT=y 465 CONFIG_PREEMPT_COUNT=y
437 CONFIG_HZ=100 466 CONFIG_HZ=100
438 CONFIG_SCHED_HRTICK=y 467 CONFIG_SCHED_HRTICK=y
439 # CONFIG_THUMB2_KERNEL is not set 468 # CONFIG_THUMB2_KERNEL is not set
440 CONFIG_AEABI=y 469 CONFIG_AEABI=y
441 # CONFIG_OABI_COMPAT is not set 470 # CONFIG_OABI_COMPAT is not set
442 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set 471 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
443 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set 472 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
444 CONFIG_HAVE_ARCH_PFN_VALID=y 473 CONFIG_HAVE_ARCH_PFN_VALID=y
445 CONFIG_HIGHMEM=y 474 CONFIG_HIGHMEM=y
446 # CONFIG_HIGHPTE is not set 475 # CONFIG_HIGHPTE is not set
447 CONFIG_HW_PERF_EVENTS=y 476 CONFIG_HW_PERF_EVENTS=y
448 CONFIG_FLATMEM=y 477 CONFIG_FLATMEM=y
449 CONFIG_FLAT_NODE_MEM_MAP=y 478 CONFIG_FLAT_NODE_MEM_MAP=y
450 CONFIG_HAVE_MEMBLOCK=y 479 CONFIG_HAVE_MEMBLOCK=y
451 CONFIG_MEMORY_ISOLATION=y 480 CONFIG_MEMORY_ISOLATION=y
452 # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set 481 # CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
453 CONFIG_PAGEFLAGS_EXTENDED=y 482 CONFIG_PAGEFLAGS_EXTENDED=y
454 CONFIG_SPLIT_PTLOCK_CPUS=4 483 CONFIG_SPLIT_PTLOCK_CPUS=4
455 CONFIG_COMPACTION=y 484 CONFIG_COMPACTION=y
456 CONFIG_MIGRATION=y 485 CONFIG_MIGRATION=y
457 # CONFIG_PHYS_ADDR_T_64BIT is not set 486 # CONFIG_PHYS_ADDR_T_64BIT is not set
458 CONFIG_ZONE_DMA_FLAG=1 487 CONFIG_ZONE_DMA_FLAG=1
459 CONFIG_BOUNCE=y 488 CONFIG_BOUNCE=y
460 # CONFIG_KSM is not set 489 # CONFIG_KSM is not set
461 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 490 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
462 CONFIG_CROSS_MEMORY_ATTACH=y 491 CONFIG_CROSS_MEMORY_ATTACH=y
463 # CONFIG_CLEANCACHE is not set 492 # CONFIG_CLEANCACHE is not set
464 # CONFIG_FRONTSWAP is not set 493 # CONFIG_FRONTSWAP is not set
465 CONFIG_FORCE_MAX_ZONEORDER=14 494 CONFIG_FORCE_MAX_ZONEORDER=14
466 CONFIG_ALIGNMENT_TRAP=y 495 CONFIG_ALIGNMENT_TRAP=y
467 # CONFIG_UACCESS_WITH_MEMCPY is not set 496 # CONFIG_UACCESS_WITH_MEMCPY is not set
468 # CONFIG_SECCOMP is not set 497 # CONFIG_SECCOMP is not set
469 # CONFIG_CC_STACKPROTECTOR is not set 498 # CONFIG_CC_STACKPROTECTOR is not set
470 # CONFIG_XEN is not set 499 # CONFIG_XEN is not set
471 500
472 # 501 #
473 # Boot options 502 # Boot options
474 # 503 #
475 CONFIG_USE_OF=y 504 CONFIG_USE_OF=y
476 CONFIG_ATAGS=y 505 CONFIG_ATAGS=y
477 # CONFIG_DEPRECATED_PARAM_STRUCT is not set 506 # CONFIG_DEPRECATED_PARAM_STRUCT is not set
478 CONFIG_ZBOOT_ROM_TEXT=0 507 CONFIG_ZBOOT_ROM_TEXT=0
479 CONFIG_ZBOOT_ROM_BSS=0 508 CONFIG_ZBOOT_ROM_BSS=0
480 # CONFIG_ARM_APPENDED_DTB is not set 509 # CONFIG_ARM_APPENDED_DTB is not set
481 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" 510 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
482 CONFIG_CMDLINE_FROM_BOOTLOADER=y 511 CONFIG_CMDLINE_FROM_BOOTLOADER=y
483 # CONFIG_CMDLINE_EXTEND is not set 512 # CONFIG_CMDLINE_EXTEND is not set
484 # CONFIG_CMDLINE_FORCE is not set 513 # CONFIG_CMDLINE_FORCE is not set
485 # CONFIG_KEXEC is not set 514 # CONFIG_KEXEC is not set
486 # CONFIG_CRASH_DUMP is not set 515 # CONFIG_CRASH_DUMP is not set
487 CONFIG_AUTO_ZRELADDR=y 516 CONFIG_AUTO_ZRELADDR=y
488 517
489 # 518 #
490 # CPU Power Management 519 # CPU Power Management
491 # 520 #
492 521
493 # 522 #
494 # CPU Frequency scaling 523 # CPU Frequency scaling
495 # 524 #
496 CONFIG_CPU_FREQ=y 525 CONFIG_CPU_FREQ=y
497 CONFIG_CPU_FREQ_TABLE=y 526 CONFIG_CPU_FREQ_TABLE=y
498 CONFIG_CPU_FREQ_GOV_COMMON=y 527 CONFIG_CPU_FREQ_GOV_COMMON=y
499 CONFIG_CPU_FREQ_STAT=y 528 CONFIG_CPU_FREQ_STAT=y
500 # CONFIG_CPU_FREQ_STAT_DETAILS is not set 529 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
501 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set 530 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
502 # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set 531 # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
503 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set 532 # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
504 # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set 533 # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
505 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set 534 # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
506 CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y 535 CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
507 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y 536 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
508 CONFIG_CPU_FREQ_GOV_POWERSAVE=y 537 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
509 CONFIG_CPU_FREQ_GOV_USERSPACE=y 538 CONFIG_CPU_FREQ_GOV_USERSPACE=y
510 CONFIG_CPU_FREQ_GOV_ONDEMAND=y 539 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
511 CONFIG_CPU_FREQ_GOV_INTERACTIVE=y 540 CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
512 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y 541 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
513 # CONFIG_GENERIC_CPUFREQ_CPU0 is not set 542 # CONFIG_GENERIC_CPUFREQ_CPU0 is not set
514 543
515 # 544 #
516 # ARM CPU frequency scaling drivers 545 # ARM CPU frequency scaling drivers
517 # 546 #
518 # CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set 547 # CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
519 # CONFIG_ARM_EXYNOS4210_CPUFREQ is not set 548 # CONFIG_ARM_EXYNOS4210_CPUFREQ is not set
520 # CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set 549 # CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set
521 # CONFIG_ARM_EXYNOS5250_CPUFREQ is not set 550 # CONFIG_ARM_EXYNOS5250_CPUFREQ is not set
522 # CONFIG_ARM_EXYNOS5440_CPUFREQ is not set 551 # CONFIG_ARM_EXYNOS5440_CPUFREQ is not set
523 CONFIG_ARM_IMX6_CPUFREQ=y 552 CONFIG_ARM_IMX6_CPUFREQ=y
524 # CONFIG_ARM_KIRKWOOD_CPUFREQ is not set 553 # CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
525 CONFIG_CPU_IDLE=y 554 CONFIG_CPU_IDLE=y
526 # CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set 555 # CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
527 CONFIG_CPU_IDLE_GOV_LADDER=y 556 CONFIG_CPU_IDLE_GOV_LADDER=y
528 CONFIG_CPU_IDLE_GOV_MENU=y 557 CONFIG_CPU_IDLE_GOV_MENU=y
529 # CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set 558 # CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
530 559
531 # 560 #
532 # Floating point emulation 561 # Floating point emulation
533 # 562 #
534 563
535 # 564 #
536 # At least one emulation must be selected 565 # At least one emulation must be selected
537 # 566 #
538 CONFIG_VFP=y 567 CONFIG_VFP=y
539 CONFIG_VFPv3=y 568 CONFIG_VFPv3=y
540 CONFIG_NEON=y 569 CONFIG_NEON=y
541 570
542 # 571 #
543 # Userspace binary formats 572 # Userspace binary formats
544 # 573 #
545 CONFIG_BINFMT_ELF=y 574 CONFIG_BINFMT_ELF=y
546 CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y 575 CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
547 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y 576 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
548 CONFIG_BINFMT_SCRIPT=y 577 CONFIG_BINFMT_SCRIPT=y
549 # CONFIG_HAVE_AOUT is not set 578 # CONFIG_HAVE_AOUT is not set
550 CONFIG_BINFMT_MISC=m 579 CONFIG_BINFMT_MISC=m
551 CONFIG_COREDUMP=y 580 CONFIG_COREDUMP=y
552 581
553 # 582 #
554 # Power management options 583 # Power management options
555 # 584 #
556 CONFIG_SUSPEND=y 585 CONFIG_SUSPEND=y
557 CONFIG_SUSPEND_FREEZER=y 586 CONFIG_SUSPEND_FREEZER=y
558 CONFIG_PM_SLEEP=y 587 CONFIG_PM_SLEEP=y
559 CONFIG_PM_SLEEP_SMP=y 588 CONFIG_PM_SLEEP_SMP=y
560 # CONFIG_PM_AUTOSLEEP is not set 589 # CONFIG_PM_AUTOSLEEP is not set
561 # CONFIG_PM_WAKELOCKS is not set 590 # CONFIG_PM_WAKELOCKS is not set
562 CONFIG_PM_RUNTIME=y 591 CONFIG_PM_RUNTIME=y
563 CONFIG_PM=y 592 CONFIG_PM=y
564 CONFIG_PM_DEBUG=y 593 CONFIG_PM_DEBUG=y
565 # CONFIG_PM_ADVANCED_DEBUG is not set 594 # CONFIG_PM_ADVANCED_DEBUG is not set
566 CONFIG_PM_TEST_SUSPEND=y 595 CONFIG_PM_TEST_SUSPEND=y
567 CONFIG_PM_SLEEP_DEBUG=y 596 CONFIG_PM_SLEEP_DEBUG=y
568 CONFIG_APM_EMULATION=y 597 CONFIG_APM_EMULATION=y
569 CONFIG_ARCH_HAS_OPP=y 598 CONFIG_ARCH_HAS_OPP=y
570 CONFIG_PM_OPP=y 599 CONFIG_PM_OPP=y
571 CONFIG_PM_CLK=y 600 CONFIG_PM_CLK=y
572 CONFIG_CPU_PM=y 601 CONFIG_CPU_PM=y
573 CONFIG_ARCH_SUSPEND_POSSIBLE=y 602 CONFIG_ARCH_SUSPEND_POSSIBLE=y
574 CONFIG_ARM_CPU_SUSPEND=y 603 CONFIG_ARM_CPU_SUSPEND=y
575 CONFIG_NET=y 604 CONFIG_NET=y
576 605
577 # 606 #
578 # Networking options 607 # Networking options
579 # 608 #
580 CONFIG_PACKET=y 609 CONFIG_PACKET=y
581 # CONFIG_PACKET_DIAG is not set 610 # CONFIG_PACKET_DIAG is not set
582 CONFIG_UNIX=y 611 CONFIG_UNIX=y
583 # CONFIG_UNIX_DIAG is not set 612 # CONFIG_UNIX_DIAG is not set
584 CONFIG_XFRM=y 613 CONFIG_XFRM=y
585 # CONFIG_XFRM_USER is not set 614 # CONFIG_XFRM_USER is not set
586 # CONFIG_XFRM_SUB_POLICY is not set 615 # CONFIG_XFRM_SUB_POLICY is not set
587 # CONFIG_XFRM_MIGRATE is not set 616 # CONFIG_XFRM_MIGRATE is not set
588 # CONFIG_XFRM_STATISTICS is not set 617 # CONFIG_XFRM_STATISTICS is not set
589 # CONFIG_NET_KEY is not set 618 # CONFIG_NET_KEY is not set
590 CONFIG_INET=y 619 CONFIG_INET=y
591 # CONFIG_IP_MULTICAST is not set 620 # CONFIG_IP_MULTICAST is not set
592 # CONFIG_IP_ADVANCED_ROUTER is not set 621 # CONFIG_IP_ADVANCED_ROUTER is not set
593 CONFIG_IP_PNP=y 622 CONFIG_IP_PNP=y
594 CONFIG_IP_PNP_DHCP=y 623 CONFIG_IP_PNP_DHCP=y
595 # CONFIG_IP_PNP_BOOTP is not set 624 # CONFIG_IP_PNP_BOOTP is not set
596 # CONFIG_IP_PNP_RARP is not set 625 # CONFIG_IP_PNP_RARP is not set
597 # CONFIG_NET_IPIP is not set 626 # CONFIG_NET_IPIP is not set
598 # CONFIG_NET_IPGRE_DEMUX is not set 627 # CONFIG_NET_IPGRE_DEMUX is not set
599 CONFIG_NET_IP_TUNNEL=y 628 CONFIG_NET_IP_TUNNEL=y
600 # CONFIG_ARPD is not set 629 # CONFIG_ARPD is not set
601 # CONFIG_SYN_COOKIES is not set 630 # CONFIG_SYN_COOKIES is not set
602 # CONFIG_INET_AH is not set 631 # CONFIG_INET_AH is not set
603 # CONFIG_INET_ESP is not set 632 # CONFIG_INET_ESP is not set
604 # CONFIG_INET_IPCOMP is not set 633 # CONFIG_INET_IPCOMP is not set
605 # CONFIG_INET_XFRM_TUNNEL is not set 634 # CONFIG_INET_XFRM_TUNNEL is not set
606 CONFIG_INET_TUNNEL=y 635 CONFIG_INET_TUNNEL=y
607 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set 636 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
608 # CONFIG_INET_XFRM_MODE_TUNNEL is not set 637 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
609 # CONFIG_INET_XFRM_MODE_BEET is not set 638 # CONFIG_INET_XFRM_MODE_BEET is not set
610 # CONFIG_INET_LRO is not set 639 # CONFIG_INET_LRO is not set
611 CONFIG_INET_DIAG=y 640 CONFIG_INET_DIAG=y
612 CONFIG_INET_TCP_DIAG=y 641 CONFIG_INET_TCP_DIAG=y
613 # CONFIG_INET_UDP_DIAG is not set 642 # CONFIG_INET_UDP_DIAG is not set
614 # CONFIG_TCP_CONG_ADVANCED is not set 643 # CONFIG_TCP_CONG_ADVANCED is not set
615 CONFIG_TCP_CONG_CUBIC=y 644 CONFIG_TCP_CONG_CUBIC=y
616 CONFIG_DEFAULT_TCP_CONG="cubic" 645 CONFIG_DEFAULT_TCP_CONG="cubic"
617 # CONFIG_TCP_MD5SIG is not set 646 # CONFIG_TCP_MD5SIG is not set
618 CONFIG_IPV6=y 647 CONFIG_IPV6=y
619 # CONFIG_IPV6_PRIVACY is not set 648 # CONFIG_IPV6_PRIVACY is not set
620 # CONFIG_IPV6_ROUTER_PREF is not set 649 # CONFIG_IPV6_ROUTER_PREF is not set
621 # CONFIG_IPV6_OPTIMISTIC_DAD is not set 650 # CONFIG_IPV6_OPTIMISTIC_DAD is not set
622 # CONFIG_INET6_AH is not set 651 # CONFIG_INET6_AH is not set
623 # CONFIG_INET6_ESP is not set 652 # CONFIG_INET6_ESP is not set
624 # CONFIG_INET6_IPCOMP is not set 653 # CONFIG_INET6_IPCOMP is not set
625 # CONFIG_IPV6_MIP6 is not set 654 # CONFIG_IPV6_MIP6 is not set
626 # CONFIG_INET6_XFRM_TUNNEL is not set 655 # CONFIG_INET6_XFRM_TUNNEL is not set
627 # CONFIG_INET6_TUNNEL is not set 656 # CONFIG_INET6_TUNNEL is not set
628 CONFIG_INET6_XFRM_MODE_TRANSPORT=y 657 CONFIG_INET6_XFRM_MODE_TRANSPORT=y
629 CONFIG_INET6_XFRM_MODE_TUNNEL=y 658 CONFIG_INET6_XFRM_MODE_TUNNEL=y
630 CONFIG_INET6_XFRM_MODE_BEET=y 659 CONFIG_INET6_XFRM_MODE_BEET=y
631 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set 660 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
632 CONFIG_IPV6_SIT=y 661 CONFIG_IPV6_SIT=y
633 # CONFIG_IPV6_SIT_6RD is not set 662 # CONFIG_IPV6_SIT_6RD is not set
634 CONFIG_IPV6_NDISC_NODETYPE=y 663 CONFIG_IPV6_NDISC_NODETYPE=y
635 # CONFIG_IPV6_TUNNEL is not set 664 # CONFIG_IPV6_TUNNEL is not set
636 # CONFIG_IPV6_GRE is not set 665 # CONFIG_IPV6_GRE is not set
637 # CONFIG_IPV6_MULTIPLE_TABLES is not set 666 # CONFIG_IPV6_MULTIPLE_TABLES is not set
638 # CONFIG_IPV6_MROUTE is not set 667 # CONFIG_IPV6_MROUTE is not set
639 # CONFIG_NETWORK_SECMARK is not set 668 # CONFIG_NETWORK_SECMARK is not set
640 # CONFIG_NETWORK_PHY_TIMESTAMPING is not set 669 # CONFIG_NETWORK_PHY_TIMESTAMPING is not set
641 # CONFIG_NETFILTER is not set 670 # CONFIG_NETFILTER is not set
642 # CONFIG_IP_DCCP is not set 671 # CONFIG_IP_DCCP is not set
643 # CONFIG_IP_SCTP is not set 672 # CONFIG_IP_SCTP is not set
644 # CONFIG_RDS is not set 673 # CONFIG_RDS is not set
645 # CONFIG_TIPC is not set 674 # CONFIG_TIPC is not set
646 # CONFIG_ATM is not set 675 # CONFIG_ATM is not set
647 # CONFIG_L2TP is not set 676 # CONFIG_L2TP is not set
648 # CONFIG_BRIDGE is not set 677 # CONFIG_BRIDGE is not set
649 CONFIG_HAVE_NET_DSA=y 678 CONFIG_HAVE_NET_DSA=y
650 CONFIG_VLAN_8021Q=y 679 CONFIG_VLAN_8021Q=y
651 # CONFIG_VLAN_8021Q_GVRP is not set 680 # CONFIG_VLAN_8021Q_GVRP is not set
652 # CONFIG_VLAN_8021Q_MVRP is not set 681 # CONFIG_VLAN_8021Q_MVRP is not set
653 # CONFIG_DECNET is not set 682 # CONFIG_DECNET is not set
654 CONFIG_LLC=y 683 CONFIG_LLC=y
655 CONFIG_LLC2=y 684 CONFIG_LLC2=y
656 # CONFIG_IPX is not set 685 # CONFIG_IPX is not set
657 # CONFIG_ATALK is not set 686 # CONFIG_ATALK is not set
658 # CONFIG_X25 is not set 687 # CONFIG_X25 is not set
659 # CONFIG_LAPB is not set 688 # CONFIG_LAPB is not set
660 # CONFIG_PHONET is not set 689 # CONFIG_PHONET is not set
661 # CONFIG_IEEE802154 is not set 690 # CONFIG_IEEE802154 is not set
662 # CONFIG_NET_SCHED is not set 691 # CONFIG_NET_SCHED is not set
663 # CONFIG_DCB is not set 692 # CONFIG_DCB is not set
664 CONFIG_DNS_RESOLVER=y 693 CONFIG_DNS_RESOLVER=y
665 # CONFIG_BATMAN_ADV is not set 694 # CONFIG_BATMAN_ADV is not set
666 # CONFIG_OPENVSWITCH is not set 695 # CONFIG_OPENVSWITCH is not set
667 # CONFIG_VSOCKETS is not set 696 # CONFIG_VSOCKETS is not set
668 # CONFIG_NETLINK_MMAP is not set 697 # CONFIG_NETLINK_MMAP is not set
669 # CONFIG_NETLINK_DIAG is not set 698 # CONFIG_NETLINK_DIAG is not set
670 CONFIG_RPS=y 699 CONFIG_RPS=y
671 CONFIG_RFS_ACCEL=y 700 CONFIG_RFS_ACCEL=y
672 CONFIG_XPS=y 701 CONFIG_XPS=y
673 # CONFIG_NETPRIO_CGROUP is not set 702 # CONFIG_NETPRIO_CGROUP is not set
674 CONFIG_BQL=y 703 CONFIG_BQL=y
675 # CONFIG_BPF_JIT is not set 704 # CONFIG_BPF_JIT is not set
676 705
677 # 706 #
678 # Network testing 707 # Network testing
679 # 708 #
680 # CONFIG_NET_PKTGEN is not set 709 # CONFIG_NET_PKTGEN is not set
681 # CONFIG_HAMRADIO is not set 710 # CONFIG_HAMRADIO is not set
682 CONFIG_CAN=y 711 CONFIG_CAN=y
683 CONFIG_CAN_RAW=y 712 CONFIG_CAN_RAW=y
684 CONFIG_CAN_BCM=y 713 CONFIG_CAN_BCM=y
685 CONFIG_CAN_GW=y 714 CONFIG_CAN_GW=y
686 715
687 # 716 #
688 # CAN Device Drivers 717 # CAN Device Drivers
689 # 718 #
690 # CONFIG_CAN_VCAN is not set 719 # CONFIG_CAN_VCAN is not set
691 # CONFIG_CAN_SLCAN is not set 720 # CONFIG_CAN_SLCAN is not set
692 CONFIG_CAN_DEV=y 721 CONFIG_CAN_DEV=y
693 CONFIG_CAN_CALC_BITTIMING=y 722 CONFIG_CAN_CALC_BITTIMING=y
694 # CONFIG_CAN_LEDS is not set 723 # CONFIG_CAN_LEDS is not set
695 # CONFIG_CAN_AT91 is not set 724 # CONFIG_CAN_AT91 is not set
696 # CONFIG_CAN_MCP251X is not set 725 # CONFIG_CAN_MCP251X is not set
697 CONFIG_HAVE_CAN_FLEXCAN=y 726 CONFIG_HAVE_CAN_FLEXCAN=y
698 CONFIG_CAN_FLEXCAN=y 727 CONFIG_CAN_FLEXCAN=y
728 # CONFIG_PCH_CAN is not set
699 # CONFIG_CAN_GRCAN is not set 729 # CONFIG_CAN_GRCAN is not set
700 CONFIG_CAN_M_CAN=y 730 CONFIG_CAN_M_CAN=y
701 # CONFIG_CAN_SJA1000 is not set 731 # CONFIG_CAN_SJA1000 is not set
702 # CONFIG_CAN_C_CAN is not set 732 # CONFIG_CAN_C_CAN is not set
703 # CONFIG_CAN_CC770 is not set 733 # CONFIG_CAN_CC770 is not set
704 734
705 # 735 #
706 # CAN USB interfaces 736 # CAN USB interfaces
707 # 737 #
708 # CONFIG_CAN_EMS_USB is not set 738 # CONFIG_CAN_EMS_USB is not set
709 # CONFIG_CAN_ESD_USB2 is not set 739 # CONFIG_CAN_ESD_USB2 is not set
710 # CONFIG_CAN_KVASER_USB is not set 740 # CONFIG_CAN_KVASER_USB is not set
711 # CONFIG_CAN_PEAK_USB is not set 741 # CONFIG_CAN_PEAK_USB is not set
712 # CONFIG_CAN_8DEV_USB is not set 742 # CONFIG_CAN_8DEV_USB is not set
713 # CONFIG_CAN_SOFTING is not set 743 # CONFIG_CAN_SOFTING is not set
714 # CONFIG_CAN_DEBUG_DEVICES is not set 744 # CONFIG_CAN_DEBUG_DEVICES is not set
715 # CONFIG_IRDA is not set 745 # CONFIG_IRDA is not set
716 # CONFIG_BT is not set 746 CONFIG_BT=y
747 CONFIG_BT_RFCOMM=y
748 CONFIG_BT_RFCOMM_TTY=y
749 CONFIG_BT_BNEP=y
750 CONFIG_BT_BNEP_MC_FILTER=y
751 CONFIG_BT_BNEP_PROTO_FILTER=y
752 CONFIG_BT_HIDP=y
753
754 #
755 # Bluetooth device drivers
756 #
757 CONFIG_BT_HCIBTUSB=y
758 CONFIG_BT_HCIBTSDIO=y
759 CONFIG_BT_HCIUART=y
760 CONFIG_BT_HCIUART_H4=y
761 CONFIG_BT_HCIUART_BCSP=y
762 CONFIG_BT_HCIUART_ATH3K=y
763 # CONFIG_BT_HCIUART_LL is not set
764 # CONFIG_BT_HCIUART_3WIRE is not set
765 CONFIG_BT_HCIBCM203X=y
766 # CONFIG_BT_HCIBPA10X is not set
767 # CONFIG_BT_HCIBFUSB is not set
768 # CONFIG_BT_HCIVHCI is not set
769 # CONFIG_BT_MRVL is not set
770 CONFIG_BT_ATH3K=y
717 # CONFIG_AF_RXRPC is not set 771 # CONFIG_AF_RXRPC is not set
718 CONFIG_WIRELESS=y 772 CONFIG_WIRELESS=y
719 CONFIG_WEXT_CORE=y 773 CONFIG_WEXT_CORE=y
720 CONFIG_WEXT_PROC=y 774 CONFIG_WEXT_PROC=y
721 CONFIG_CFG80211=y 775 CONFIG_CFG80211=y
722 # CONFIG_NL80211_TESTMODE is not set 776 # CONFIG_NL80211_TESTMODE is not set
723 # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set 777 # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
724 # CONFIG_CFG80211_REG_DEBUG is not set 778 # CONFIG_CFG80211_REG_DEBUG is not set
725 # CONFIG_CFG80211_CERTIFICATION_ONUS is not set 779 # CONFIG_CFG80211_CERTIFICATION_ONUS is not set
726 CONFIG_CFG80211_DEFAULT_PS=y 780 CONFIG_CFG80211_DEFAULT_PS=y
727 # CONFIG_CFG80211_DEBUGFS is not set 781 # CONFIG_CFG80211_DEBUGFS is not set
728 # CONFIG_CFG80211_INTERNAL_REGDB is not set 782 # CONFIG_CFG80211_INTERNAL_REGDB is not set
729 CONFIG_CFG80211_WEXT=y 783 CONFIG_CFG80211_WEXT=y
730 # CONFIG_LIB80211 is not set 784 # CONFIG_LIB80211 is not set
731 CONFIG_MAC80211=y 785 CONFIG_MAC80211=y
732 CONFIG_MAC80211_HAS_RC=y 786 CONFIG_MAC80211_HAS_RC=y
733 # CONFIG_MAC80211_RC_PID is not set 787 # CONFIG_MAC80211_RC_PID is not set
734 CONFIG_MAC80211_RC_MINSTREL=y 788 CONFIG_MAC80211_RC_MINSTREL=y
735 CONFIG_MAC80211_RC_MINSTREL_HT=y 789 CONFIG_MAC80211_RC_MINSTREL_HT=y
736 CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y 790 CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
737 CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" 791 CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
738 # CONFIG_MAC80211_MESH is not set 792 # CONFIG_MAC80211_MESH is not set
739 # CONFIG_MAC80211_LEDS is not set 793 CONFIG_MAC80211_LEDS=y
740 # CONFIG_MAC80211_DEBUGFS is not set 794 # CONFIG_MAC80211_DEBUGFS is not set
741 # CONFIG_MAC80211_MESSAGE_TRACING is not set 795 # CONFIG_MAC80211_MESSAGE_TRACING is not set
742 # CONFIG_MAC80211_DEBUG_MENU is not set 796 # CONFIG_MAC80211_DEBUG_MENU is not set
743 # CONFIG_WIMAX is not set 797 # CONFIG_WIMAX is not set
744 # CONFIG_RFKILL is not set 798 # CONFIG_RFKILL is not set
745 # CONFIG_RFKILL_REGULATOR is not set 799 # CONFIG_RFKILL_REGULATOR is not set
746 # CONFIG_NET_9P is not set 800 # CONFIG_NET_9P is not set
747 # CONFIG_CAIF is not set 801 # CONFIG_CAIF is not set
748 # CONFIG_CEPH_LIB is not set 802 # CONFIG_CEPH_LIB is not set
749 # CONFIG_NFC is not set 803 # CONFIG_NFC is not set
750 CONFIG_HAVE_BPF_JIT=y 804 CONFIG_HAVE_BPF_JIT=y
751 805
752 # 806 #
753 # Device Drivers 807 # Device Drivers
754 # 808 #
755 809
756 # 810 #
757 # Generic Driver Options 811 # Generic Driver Options
758 # 812 #
759 CONFIG_UEVENT_HELPER_PATH="" 813 CONFIG_UEVENT_HELPER_PATH=""
760 CONFIG_DEVTMPFS=y 814 CONFIG_DEVTMPFS=y
761 CONFIG_DEVTMPFS_MOUNT=y 815 CONFIG_DEVTMPFS_MOUNT=y
762 # CONFIG_STANDALONE is not set 816 # CONFIG_STANDALONE is not set
763 CONFIG_PREVENT_FIRMWARE_BUILD=y 817 CONFIG_PREVENT_FIRMWARE_BUILD=y
764 CONFIG_FW_LOADER=y 818 CONFIG_FW_LOADER=y
765 CONFIG_FIRMWARE_IN_KERNEL=y 819 CONFIG_FIRMWARE_IN_KERNEL=y
766 CONFIG_EXTRA_FIRMWARE="" 820 CONFIG_EXTRA_FIRMWARE=""
767 CONFIG_FW_LOADER_USER_HELPER=y 821 CONFIG_FW_LOADER_USER_HELPER=y
768 # CONFIG_DEBUG_DRIVER is not set 822 # CONFIG_DEBUG_DRIVER is not set
769 # CONFIG_DEBUG_DEVRES is not set 823 # CONFIG_DEBUG_DEVRES is not set
770 # CONFIG_SYS_HYPERVISOR is not set 824 # CONFIG_SYS_HYPERVISOR is not set
771 # CONFIG_GENERIC_CPU_DEVICES is not set 825 # CONFIG_GENERIC_CPU_DEVICES is not set
772 CONFIG_SOC_BUS=y 826 CONFIG_SOC_BUS=y
773 CONFIG_REGMAP=y 827 CONFIG_REGMAP=y
774 CONFIG_REGMAP_I2C=y 828 CONFIG_REGMAP_I2C=y
775 CONFIG_REGMAP_SPI=y 829 CONFIG_REGMAP_SPI=y
776 CONFIG_REGMAP_MMIO=y 830 CONFIG_REGMAP_MMIO=y
777 CONFIG_REGMAP_IRQ=y 831 CONFIG_REGMAP_IRQ=y
778 CONFIG_DMA_SHARED_BUFFER=y 832 CONFIG_DMA_SHARED_BUFFER=y
779 CONFIG_CMA=y 833 CONFIG_CMA=y
780 # CONFIG_CMA_DEBUG is not set 834 # CONFIG_CMA_DEBUG is not set
781 835
782 # 836 #
783 # Default contiguous memory area size: 837 # Default contiguous memory area size:
784 # 838 #
785 CONFIG_CMA_SIZE_MBYTES=320 839 CONFIG_CMA_SIZE_MBYTES=320
786 CONFIG_CMA_SIZE_SEL_MBYTES=y 840 CONFIG_CMA_SIZE_SEL_MBYTES=y
787 # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set 841 # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
788 # CONFIG_CMA_SIZE_SEL_MIN is not set 842 # CONFIG_CMA_SIZE_SEL_MIN is not set
789 # CONFIG_CMA_SIZE_SEL_MAX is not set 843 # CONFIG_CMA_SIZE_SEL_MAX is not set
790 CONFIG_CMA_ALIGNMENT=8 844 CONFIG_CMA_ALIGNMENT=8
791 CONFIG_CMA_AREAS=7 845 CONFIG_CMA_AREAS=7
792 846
793 # 847 #
794 # Bus devices 848 # Bus devices
795 # 849 #
796 CONFIG_IMX_WEIM=y 850 CONFIG_IMX_WEIM=y
797 CONFIG_CONNECTOR=y 851 CONFIG_CONNECTOR=y
798 CONFIG_PROC_EVENTS=y 852 CONFIG_PROC_EVENTS=y
799 CONFIG_MTD=y 853 CONFIG_MTD=y
800 # CONFIG_MTD_TESTS is not set 854 # CONFIG_MTD_TESTS is not set
801 # CONFIG_MTD_REDBOOT_PARTS is not set 855 # CONFIG_MTD_REDBOOT_PARTS is not set
802 CONFIG_MTD_CMDLINE_PARTS=y 856 CONFIG_MTD_CMDLINE_PARTS=y
803 # CONFIG_MTD_AFS_PARTS is not set 857 # CONFIG_MTD_AFS_PARTS is not set
804 CONFIG_MTD_OF_PARTS=y 858 CONFIG_MTD_OF_PARTS=y
805 # CONFIG_MTD_AR7_PARTS is not set 859 # CONFIG_MTD_AR7_PARTS is not set
806 860
807 # 861 #
808 # User Modules And Translation Layers 862 # User Modules And Translation Layers
809 # 863 #
810 CONFIG_MTD_BLKDEVS=y 864 CONFIG_MTD_BLKDEVS=y
811 CONFIG_MTD_BLOCK=y 865 CONFIG_MTD_BLOCK=y
812 # CONFIG_FTL is not set 866 # CONFIG_FTL is not set
813 # CONFIG_NFTL is not set 867 # CONFIG_NFTL is not set
814 # CONFIG_INFTL is not set 868 # CONFIG_INFTL is not set
815 # CONFIG_RFD_FTL is not set 869 # CONFIG_RFD_FTL is not set
816 # CONFIG_SSFDC is not set 870 # CONFIG_SSFDC is not set
817 # CONFIG_SM_FTL is not set 871 # CONFIG_SM_FTL is not set
818 # CONFIG_MTD_OOPS is not set 872 # CONFIG_MTD_OOPS is not set
819 # CONFIG_MTD_SWAP is not set 873 # CONFIG_MTD_SWAP is not set
820 874
821 # 875 #
822 # RAM/ROM/Flash chip drivers 876 # RAM/ROM/Flash chip drivers
823 # 877 #
824 CONFIG_MTD_CFI=y 878 CONFIG_MTD_CFI=y
825 CONFIG_MTD_JEDECPROBE=y 879 CONFIG_MTD_JEDECPROBE=y
826 CONFIG_MTD_GEN_PROBE=y 880 CONFIG_MTD_GEN_PROBE=y
827 # CONFIG_MTD_CFI_ADV_OPTIONS is not set 881 # CONFIG_MTD_CFI_ADV_OPTIONS is not set
828 CONFIG_MTD_MAP_BANK_WIDTH_1=y 882 CONFIG_MTD_MAP_BANK_WIDTH_1=y
829 CONFIG_MTD_MAP_BANK_WIDTH_2=y 883 CONFIG_MTD_MAP_BANK_WIDTH_2=y
830 CONFIG_MTD_MAP_BANK_WIDTH_4=y 884 CONFIG_MTD_MAP_BANK_WIDTH_4=y
831 # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set 885 # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
832 # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set 886 # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
833 # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set 887 # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
834 CONFIG_MTD_CFI_I1=y 888 CONFIG_MTD_CFI_I1=y
835 CONFIG_MTD_CFI_I2=y 889 CONFIG_MTD_CFI_I2=y
836 # CONFIG_MTD_CFI_I4 is not set 890 # CONFIG_MTD_CFI_I4 is not set
837 # CONFIG_MTD_CFI_I8 is not set 891 # CONFIG_MTD_CFI_I8 is not set
838 CONFIG_MTD_CFI_INTELEXT=y 892 CONFIG_MTD_CFI_INTELEXT=y
839 CONFIG_MTD_CFI_AMDSTD=y 893 CONFIG_MTD_CFI_AMDSTD=y
840 CONFIG_MTD_CFI_STAA=y 894 CONFIG_MTD_CFI_STAA=y
841 CONFIG_MTD_CFI_UTIL=y 895 CONFIG_MTD_CFI_UTIL=y
842 # CONFIG_MTD_RAM is not set 896 # CONFIG_MTD_RAM is not set
843 # CONFIG_MTD_ROM is not set 897 # CONFIG_MTD_ROM is not set
844 # CONFIG_MTD_ABSENT is not set 898 # CONFIG_MTD_ABSENT is not set
845 899
846 # 900 #
847 # Mapping drivers for chip access 901 # Mapping drivers for chip access
848 # 902 #
849 # CONFIG_MTD_COMPLEX_MAPPINGS is not set 903 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
850 # CONFIG_MTD_PHYSMAP is not set 904 # CONFIG_MTD_PHYSMAP is not set
851 CONFIG_MTD_PHYSMAP_OF=y 905 CONFIG_MTD_PHYSMAP_OF=y
852 # CONFIG_MTD_IMPA7 is not set 906 # CONFIG_MTD_IMPA7 is not set
907 # CONFIG_MTD_INTEL_VR_NOR is not set
853 # CONFIG_MTD_PLATRAM is not set 908 # CONFIG_MTD_PLATRAM is not set
854 909
855 # 910 #
856 # Self-contained MTD device drivers 911 # Self-contained MTD device drivers
857 # 912 #
913 # CONFIG_MTD_PMC551 is not set
858 CONFIG_MTD_DATAFLASH=y 914 CONFIG_MTD_DATAFLASH=y
859 # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set 915 # CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
860 # CONFIG_MTD_DATAFLASH_OTP is not set 916 # CONFIG_MTD_DATAFLASH_OTP is not set
861 CONFIG_MTD_M25P80=y 917 CONFIG_MTD_M25P80=y
862 CONFIG_MTD_SST25L=y 918 CONFIG_MTD_SST25L=y
863 # CONFIG_MTD_SLRAM is not set 919 # CONFIG_MTD_SLRAM is not set
864 # CONFIG_MTD_PHRAM is not set 920 # CONFIG_MTD_PHRAM is not set
865 # CONFIG_MTD_MTDRAM is not set 921 # CONFIG_MTD_MTDRAM is not set
866 # CONFIG_MTD_BLOCK2MTD is not set 922 # CONFIG_MTD_BLOCK2MTD is not set
867 923
868 # 924 #
869 # Disk-On-Chip Device Drivers 925 # Disk-On-Chip Device Drivers
870 # 926 #
871 # CONFIG_MTD_DOCG3 is not set 927 # CONFIG_MTD_DOCG3 is not set
872 CONFIG_MTD_NAND_ECC=y 928 CONFIG_MTD_NAND_ECC=y
873 # CONFIG_MTD_NAND_ECC_SMC is not set 929 # CONFIG_MTD_NAND_ECC_SMC is not set
874 CONFIG_MTD_NAND=y 930 CONFIG_MTD_NAND=y
875 # CONFIG_MTD_NAND_ECC_BCH is not set 931 # CONFIG_MTD_NAND_ECC_BCH is not set
876 # CONFIG_MTD_SM_COMMON is not set 932 # CONFIG_MTD_SM_COMMON is not set
877 # CONFIG_MTD_NAND_DENALI is not set 933 # CONFIG_MTD_NAND_DENALI is not set
878 # CONFIG_MTD_NAND_GPIO is not set 934 # CONFIG_MTD_NAND_GPIO is not set
879 CONFIG_MTD_NAND_IDS=y 935 CONFIG_MTD_NAND_IDS=y
936 # CONFIG_MTD_NAND_RICOH is not set
880 # CONFIG_MTD_NAND_DISKONCHIP is not set 937 # CONFIG_MTD_NAND_DISKONCHIP is not set
881 # CONFIG_MTD_NAND_DOCG4 is not set 938 # CONFIG_MTD_NAND_DOCG4 is not set
939 # CONFIG_MTD_NAND_CAFE is not set
882 # CONFIG_MTD_NAND_NANDSIM is not set 940 # CONFIG_MTD_NAND_NANDSIM is not set
883 CONFIG_MTD_NAND_GPMI_NAND=y 941 CONFIG_MTD_NAND_GPMI_NAND=y
884 # CONFIG_MTD_NAND_PLATFORM is not set 942 # CONFIG_MTD_NAND_PLATFORM is not set
885 # CONFIG_MTD_ALAUDA is not set 943 # CONFIG_MTD_ALAUDA is not set
886 CONFIG_MTD_NAND_MXC=y 944 CONFIG_MTD_NAND_MXC=y
887 # CONFIG_MTD_ONENAND is not set 945 # CONFIG_MTD_ONENAND is not set
888 946
889 # 947 #
890 # LPDDR flash memory drivers 948 # LPDDR flash memory drivers
891 # 949 #
892 # CONFIG_MTD_LPDDR is not set 950 # CONFIG_MTD_LPDDR is not set
893 CONFIG_MTD_SPI_NOR_BASE=y 951 CONFIG_MTD_SPI_NOR_BASE=y
894 CONFIG_SPI_FSL_QUADSPI=y 952 CONFIG_SPI_FSL_QUADSPI=y
895 CONFIG_MTD_UBI=y 953 CONFIG_MTD_UBI=y
896 CONFIG_MTD_UBI_WL_THRESHOLD=4096 954 CONFIG_MTD_UBI_WL_THRESHOLD=4096
897 CONFIG_MTD_UBI_BEB_LIMIT=20 955 CONFIG_MTD_UBI_BEB_LIMIT=20
898 # CONFIG_MTD_UBI_FASTMAP is not set 956 # CONFIG_MTD_UBI_FASTMAP is not set
899 # CONFIG_MTD_UBI_GLUEBI is not set 957 # CONFIG_MTD_UBI_GLUEBI is not set
900 CONFIG_DTC=y 958 CONFIG_DTC=y
901 CONFIG_OF=y 959 CONFIG_OF=y
902 960
903 # 961 #
904 # Device Tree and Open Firmware support 962 # Device Tree and Open Firmware support
905 # 963 #
906 # CONFIG_PROC_DEVICETREE is not set 964 # CONFIG_PROC_DEVICETREE is not set
907 # CONFIG_OF_SELFTEST is not set 965 # CONFIG_OF_SELFTEST is not set
908 CONFIG_OF_FLATTREE=y 966 CONFIG_OF_FLATTREE=y
909 CONFIG_OF_EARLY_FLATTREE=y 967 CONFIG_OF_EARLY_FLATTREE=y
910 CONFIG_OF_ADDRESS=y 968 CONFIG_OF_ADDRESS=y
911 CONFIG_OF_IRQ=y 969 CONFIG_OF_IRQ=y
912 CONFIG_OF_DEVICE=y 970 CONFIG_OF_DEVICE=y
913 CONFIG_OF_I2C=y 971 CONFIG_OF_I2C=y
914 CONFIG_OF_NET=y 972 CONFIG_OF_NET=y
915 CONFIG_OF_MDIO=y 973 CONFIG_OF_MDIO=y
974 CONFIG_OF_PCI=y
975 CONFIG_OF_PCI_IRQ=y
916 CONFIG_OF_MTD=y 976 CONFIG_OF_MTD=y
917 # CONFIG_PARPORT is not set 977 # CONFIG_PARPORT is not set
918 CONFIG_BLK_DEV=y 978 CONFIG_BLK_DEV=y
979 # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
980 # CONFIG_BLK_CPQ_CISS_DA is not set
981 # CONFIG_BLK_DEV_DAC960 is not set
982 # CONFIG_BLK_DEV_UMEM is not set
919 # CONFIG_BLK_DEV_COW_COMMON is not set 983 # CONFIG_BLK_DEV_COW_COMMON is not set
920 CONFIG_BLK_DEV_LOOP=y 984 CONFIG_BLK_DEV_LOOP=y
921 CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 985 CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
922 # CONFIG_BLK_DEV_CRYPTOLOOP is not set 986 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
923 # CONFIG_BLK_DEV_DRBD is not set 987 # CONFIG_BLK_DEV_DRBD is not set
924 # CONFIG_BLK_DEV_NBD is not set 988 # CONFIG_BLK_DEV_NBD is not set
989 # CONFIG_BLK_DEV_NVME is not set
990 # CONFIG_BLK_DEV_SX8 is not set
925 CONFIG_BLK_DEV_RAM=y 991 CONFIG_BLK_DEV_RAM=y
926 CONFIG_BLK_DEV_RAM_COUNT=16 992 CONFIG_BLK_DEV_RAM_COUNT=16
927 CONFIG_BLK_DEV_RAM_SIZE=65536 993 CONFIG_BLK_DEV_RAM_SIZE=65536
928 # CONFIG_BLK_DEV_XIP is not set 994 # CONFIG_BLK_DEV_XIP is not set
929 # CONFIG_CDROM_PKTCDVD is not set 995 # CONFIG_CDROM_PKTCDVD is not set
930 # CONFIG_ATA_OVER_ETH is not set 996 # CONFIG_ATA_OVER_ETH is not set
931 # CONFIG_MG_DISK is not set 997 # CONFIG_MG_DISK is not set
932 # CONFIG_BLK_DEV_RBD is not set 998 # CONFIG_BLK_DEV_RBD is not set
999 # CONFIG_BLK_DEV_RSXX is not set
933 1000
934 # 1001 #
935 # Misc devices 1002 # Misc devices
936 # 1003 #
937 # CONFIG_SENSORS_LIS3LV02D is not set 1004 # CONFIG_SENSORS_LIS3LV02D is not set
938 # CONFIG_AD525X_DPOT is not set 1005 # CONFIG_AD525X_DPOT is not set
939 # CONFIG_ATMEL_PWM is not set 1006 # CONFIG_ATMEL_PWM is not set
940 # CONFIG_DUMMY_IRQ is not set 1007 # CONFIG_DUMMY_IRQ is not set
1008 # CONFIG_PHANTOM is not set
1009 # CONFIG_INTEL_MID_PTI is not set
1010 # CONFIG_SGI_IOC4 is not set
1011 # CONFIG_TIFM_CORE is not set
941 # CONFIG_ICS932S401 is not set 1012 # CONFIG_ICS932S401 is not set
942 # CONFIG_ATMEL_SSC is not set 1013 # CONFIG_ATMEL_SSC is not set
943 # CONFIG_ENCLOSURE_SERVICES is not set 1014 # CONFIG_ENCLOSURE_SERVICES is not set
1015 # CONFIG_HP_ILO is not set
944 # CONFIG_APDS9802ALS is not set 1016 # CONFIG_APDS9802ALS is not set
945 # CONFIG_ISL29003 is not set 1017 # CONFIG_ISL29003 is not set
946 # CONFIG_ISL29020 is not set 1018 # CONFIG_ISL29020 is not set
947 # CONFIG_SENSORS_TSL2550 is not set 1019 # CONFIG_SENSORS_TSL2550 is not set
948 # CONFIG_SENSORS_BH1780 is not set 1020 # CONFIG_SENSORS_BH1780 is not set
949 # CONFIG_SENSORS_BH1770 is not set 1021 # CONFIG_SENSORS_BH1770 is not set
950 # CONFIG_SENSORS_APDS990X is not set 1022 # CONFIG_SENSORS_APDS990X is not set
951 # CONFIG_HMC6352 is not set 1023 # CONFIG_HMC6352 is not set
952 # CONFIG_DS1682 is not set 1024 # CONFIG_DS1682 is not set
953 # CONFIG_TI_DAC7512 is not set 1025 # CONFIG_TI_DAC7512 is not set
954 # CONFIG_BMP085_I2C is not set 1026 # CONFIG_BMP085_I2C is not set
955 # CONFIG_BMP085_SPI is not set 1027 # CONFIG_BMP085_SPI is not set
1028 # CONFIG_PCH_PHUB is not set
956 # CONFIG_USB_SWITCH_FSA9480 is not set 1029 # CONFIG_USB_SWITCH_FSA9480 is not set
957 # CONFIG_LATTICE_ECP3_CONFIG is not set 1030 # CONFIG_LATTICE_ECP3_CONFIG is not set
958 CONFIG_SRAM=y 1031 CONFIG_SRAM=y
959 # CONFIG_C2PORT is not set 1032 # CONFIG_C2PORT is not set
960 1033
961 # 1034 #
962 # EEPROM support 1035 # EEPROM support
963 # 1036 #
964 CONFIG_EEPROM_AT24=y 1037 CONFIG_EEPROM_AT24=y
965 # CONFIG_EEPROM_AT25 is not set 1038 # CONFIG_EEPROM_AT25 is not set
966 # CONFIG_EEPROM_LEGACY is not set 1039 # CONFIG_EEPROM_LEGACY is not set
967 # CONFIG_EEPROM_MAX6875 is not set 1040 # CONFIG_EEPROM_MAX6875 is not set
968 # CONFIG_EEPROM_93CX6 is not set 1041 # CONFIG_EEPROM_93CX6 is not set
969 # CONFIG_EEPROM_93XX46 is not set 1042 # CONFIG_EEPROM_93XX46 is not set
1043 # CONFIG_CB710_CORE is not set
970 1044
971 # 1045 #
972 # Texas Instruments shared transport line discipline 1046 # Texas Instruments shared transport line discipline
973 # 1047 #
974 # CONFIG_TI_ST is not set 1048 # CONFIG_TI_ST is not set
975 # CONFIG_SENSORS_LIS3_SPI is not set 1049 # CONFIG_SENSORS_LIS3_SPI is not set
976 # CONFIG_SENSORS_LIS3_I2C is not set 1050 # CONFIG_SENSORS_LIS3_I2C is not set
977 1051
978 # 1052 #
979 # Altera FPGA firmware download module 1053 # Altera FPGA firmware download module
980 # 1054 #
981 # CONFIG_ALTERA_STAPL is not set 1055 # CONFIG_ALTERA_STAPL is not set
1056 CONFIG_HAVE_IDE=y
1057 # CONFIG_IDE is not set
982 1058
983 # 1059 #
984 # SCSI device support 1060 # SCSI device support
985 # 1061 #
986 CONFIG_SCSI_MOD=y 1062 CONFIG_SCSI_MOD=y
987 # CONFIG_RAID_ATTRS is not set 1063 # CONFIG_RAID_ATTRS is not set
988 CONFIG_SCSI=y 1064 CONFIG_SCSI=y
989 CONFIG_SCSI_DMA=y 1065 CONFIG_SCSI_DMA=y
990 # CONFIG_SCSI_TGT is not set 1066 # CONFIG_SCSI_TGT is not set
991 # CONFIG_SCSI_NETLINK is not set 1067 # CONFIG_SCSI_NETLINK is not set
992 # CONFIG_SCSI_PROC_FS is not set 1068 # CONFIG_SCSI_PROC_FS is not set
993 1069
994 # 1070 #
995 # SCSI support type (disk, tape, CD-ROM) 1071 # SCSI support type (disk, tape, CD-ROM)
996 # 1072 #
997 CONFIG_BLK_DEV_SD=y 1073 CONFIG_BLK_DEV_SD=y
998 # CONFIG_CHR_DEV_ST is not set 1074 # CONFIG_CHR_DEV_ST is not set
999 # CONFIG_CHR_DEV_OSST is not set 1075 # CONFIG_CHR_DEV_OSST is not set
1000 # CONFIG_BLK_DEV_SR is not set 1076 # CONFIG_BLK_DEV_SR is not set
1001 # CONFIG_CHR_DEV_SG is not set 1077 # CONFIG_CHR_DEV_SG is not set
1002 # CONFIG_CHR_DEV_SCH is not set 1078 # CONFIG_CHR_DEV_SCH is not set
1003 CONFIG_SCSI_MULTI_LUN=y 1079 CONFIG_SCSI_MULTI_LUN=y
1004 CONFIG_SCSI_CONSTANTS=y 1080 CONFIG_SCSI_CONSTANTS=y
1005 CONFIG_SCSI_LOGGING=y 1081 CONFIG_SCSI_LOGGING=y
1006 CONFIG_SCSI_SCAN_ASYNC=y 1082 CONFIG_SCSI_SCAN_ASYNC=y
1007 1083
1008 # 1084 #
1009 # SCSI Transports 1085 # SCSI Transports
1010 # 1086 #
1011 # CONFIG_SCSI_SPI_ATTRS is not set 1087 # CONFIG_SCSI_SPI_ATTRS is not set
1012 # CONFIG_SCSI_FC_ATTRS is not set 1088 # CONFIG_SCSI_FC_ATTRS is not set
1013 # CONFIG_SCSI_ISCSI_ATTRS is not set 1089 # CONFIG_SCSI_ISCSI_ATTRS is not set
1014 # CONFIG_SCSI_SAS_ATTRS is not set 1090 # CONFIG_SCSI_SAS_ATTRS is not set
1015 # CONFIG_SCSI_SAS_LIBSAS is not set 1091 # CONFIG_SCSI_SAS_LIBSAS is not set
1016 # CONFIG_SCSI_SRP_ATTRS is not set 1092 # CONFIG_SCSI_SRP_ATTRS is not set
1017 # CONFIG_SCSI_LOWLEVEL is not set 1093 # CONFIG_SCSI_LOWLEVEL is not set
1018 # CONFIG_SCSI_DH is not set 1094 # CONFIG_SCSI_DH is not set
1019 # CONFIG_SCSI_OSD_INITIATOR is not set 1095 # CONFIG_SCSI_OSD_INITIATOR is not set
1020 CONFIG_ATA=y 1096 CONFIG_ATA=y
1021 # CONFIG_ATA_NONSTANDARD is not set 1097 # CONFIG_ATA_NONSTANDARD is not set
1022 CONFIG_ATA_VERBOSE_ERROR=y 1098 CONFIG_ATA_VERBOSE_ERROR=y
1023 CONFIG_SATA_PMP=y 1099 CONFIG_SATA_PMP=y
1024 1100
1025 # 1101 #
1026 # Controllers with non-SFF native interface 1102 # Controllers with non-SFF native interface
1027 # 1103 #
1104 # CONFIG_SATA_AHCI is not set
1028 CONFIG_SATA_AHCI_PLATFORM=y 1105 CONFIG_SATA_AHCI_PLATFORM=y
1029 CONFIG_AHCI_IMX=y 1106 CONFIG_AHCI_IMX=y
1107 # CONFIG_SATA_INIC162X is not set
1108 # CONFIG_SATA_ACARD_AHCI is not set
1109 # CONFIG_SATA_SIL24 is not set
1030 CONFIG_ATA_SFF=y 1110 CONFIG_ATA_SFF=y
1031 1111
1032 # 1112 #
1033 # SFF controllers with custom DMA interface 1113 # SFF controllers with custom DMA interface
1034 # 1114 #
1115 # CONFIG_PDC_ADMA is not set
1116 # CONFIG_SATA_QSTOR is not set
1117 # CONFIG_SATA_SX4 is not set
1035 CONFIG_ATA_BMDMA=y 1118 CONFIG_ATA_BMDMA=y
1036 1119
1037 # 1120 #
1038 # SATA SFF controllers with BMDMA 1121 # SATA SFF controllers with BMDMA
1039 # 1122 #
1123 # CONFIG_ATA_PIIX is not set
1040 # CONFIG_SATA_HIGHBANK is not set 1124 # CONFIG_SATA_HIGHBANK is not set
1041 # CONFIG_SATA_MV is not set 1125 # CONFIG_SATA_MV is not set
1126 # CONFIG_SATA_NV is not set
1127 # CONFIG_SATA_PROMISE is not set
1128 # CONFIG_SATA_SIL is not set
1129 # CONFIG_SATA_SIS is not set
1130 # CONFIG_SATA_SVW is not set
1131 # CONFIG_SATA_ULI is not set
1132 # CONFIG_SATA_VIA is not set
1133 # CONFIG_SATA_VITESSE is not set
1042 1134
1043 # 1135 #
1044 # PATA SFF controllers with BMDMA 1136 # PATA SFF controllers with BMDMA
1045 # 1137 #
1138 # CONFIG_PATA_ALI is not set
1139 # CONFIG_PATA_AMD is not set
1046 # CONFIG_PATA_ARASAN_CF is not set 1140 # CONFIG_PATA_ARASAN_CF is not set
1141 # CONFIG_PATA_ARTOP is not set
1142 # CONFIG_PATA_ATIIXP is not set
1143 # CONFIG_PATA_ATP867X is not set
1144 # CONFIG_PATA_CMD64X is not set
1145 # CONFIG_PATA_CS5520 is not set
1146 # CONFIG_PATA_CS5530 is not set
1147 # CONFIG_PATA_CS5536 is not set
1148 # CONFIG_PATA_CYPRESS is not set
1149 # CONFIG_PATA_EFAR is not set
1150 # CONFIG_PATA_HPT366 is not set
1151 # CONFIG_PATA_HPT37X is not set
1152 # CONFIG_PATA_HPT3X2N is not set
1153 # CONFIG_PATA_HPT3X3 is not set
1047 CONFIG_PATA_IMX=y 1154 CONFIG_PATA_IMX=y
1155 # CONFIG_PATA_IT8213 is not set
1156 # CONFIG_PATA_IT821X is not set
1157 # CONFIG_PATA_JMICRON is not set
1158 # CONFIG_PATA_MARVELL is not set
1159 # CONFIG_PATA_NETCELL is not set
1160 # CONFIG_PATA_NINJA32 is not set
1161 # CONFIG_PATA_NS87415 is not set
1162 # CONFIG_PATA_OLDPIIX is not set
1163 # CONFIG_PATA_OPTIDMA is not set
1164 # CONFIG_PATA_PDC2027X is not set
1165 # CONFIG_PATA_PDC_OLD is not set
1166 # CONFIG_PATA_RADISYS is not set
1167 # CONFIG_PATA_RDC is not set
1168 # CONFIG_PATA_SC1200 is not set
1169 # CONFIG_PATA_SCH is not set
1170 # CONFIG_PATA_SERVERWORKS is not set
1171 # CONFIG_PATA_SIL680 is not set
1172 # CONFIG_PATA_SIS is not set
1173 # CONFIG_PATA_TOSHIBA is not set
1174 # CONFIG_PATA_TRIFLEX is not set
1175 # CONFIG_PATA_VIA is not set
1176 # CONFIG_PATA_WINBOND is not set
1048 1177
1049 # 1178 #
1050 # PIO-only SFF controllers 1179 # PIO-only SFF controllers
1051 # 1180 #
1181 # CONFIG_PATA_CMD640_PCI is not set
1182 # CONFIG_PATA_MPIIX is not set
1183 # CONFIG_PATA_NS87410 is not set
1184 # CONFIG_PATA_OPTI is not set
1052 # CONFIG_PATA_PLATFORM is not set 1185 # CONFIG_PATA_PLATFORM is not set
1186 # CONFIG_PATA_RZ1000 is not set
1053 1187
1054 # 1188 #
1055 # Generic fallback / legacy drivers 1189 # Generic fallback / legacy drivers
1056 # 1190 #
1191 # CONFIG_ATA_GENERIC is not set
1192 # CONFIG_PATA_LEGACY is not set
1057 # CONFIG_MD is not set 1193 # CONFIG_MD is not set
1058 # CONFIG_TARGET_CORE is not set 1194 # CONFIG_TARGET_CORE is not set
1195 # CONFIG_FUSION is not set
1196
1197 #
1198 # IEEE 1394 (FireWire) support
1199 #
1200 # CONFIG_FIREWIRE is not set
1201 # CONFIG_FIREWIRE_NOSY is not set
1202 # CONFIG_I2O is not set
1059 CONFIG_NETDEVICES=y 1203 CONFIG_NETDEVICES=y
1060 CONFIG_NET_CORE=y 1204 CONFIG_NET_CORE=y
1061 # CONFIG_BONDING is not set 1205 # CONFIG_BONDING is not set
1062 # CONFIG_DUMMY is not set 1206 # CONFIG_DUMMY is not set
1063 # CONFIG_EQUALIZER is not set 1207 # CONFIG_EQUALIZER is not set
1208 # CONFIG_NET_FC is not set
1064 CONFIG_MII=y 1209 CONFIG_MII=y
1065 # CONFIG_NET_TEAM is not set 1210 # CONFIG_NET_TEAM is not set
1066 # CONFIG_MACVLAN is not set 1211 # CONFIG_MACVLAN is not set
1067 # CONFIG_VXLAN is not set 1212 # CONFIG_VXLAN is not set
1068 # CONFIG_NETCONSOLE is not set 1213 # CONFIG_NETCONSOLE is not set
1069 # CONFIG_NETPOLL is not set 1214 # CONFIG_NETPOLL is not set
1070 # CONFIG_NET_POLL_CONTROLLER is not set 1215 # CONFIG_NET_POLL_CONTROLLER is not set
1071 # CONFIG_TUN is not set 1216 # CONFIG_TUN is not set
1072 # CONFIG_VETH is not set 1217 # CONFIG_VETH is not set
1218 # CONFIG_ARCNET is not set
1073 1219
1074 # 1220 #
1075 # CAIF transport drivers 1221 # CAIF transport drivers
1076 # 1222 #
1077 1223
1078 # 1224 #
1079 # Distributed Switch Architecture drivers 1225 # Distributed Switch Architecture drivers
1080 # 1226 #
1081 # CONFIG_NET_DSA_MV88E6XXX is not set 1227 # CONFIG_NET_DSA_MV88E6XXX is not set
1082 # CONFIG_NET_DSA_MV88E6060 is not set 1228 # CONFIG_NET_DSA_MV88E6060 is not set
1083 # CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set 1229 # CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
1084 # CONFIG_NET_DSA_MV88E6131 is not set 1230 # CONFIG_NET_DSA_MV88E6131 is not set
1085 # CONFIG_NET_DSA_MV88E6123_61_65 is not set 1231 # CONFIG_NET_DSA_MV88E6123_61_65 is not set
1086 CONFIG_ETHERNET=y 1232 CONFIG_ETHERNET=y
1233 CONFIG_NET_VENDOR_3COM=y
1234 # CONFIG_VORTEX is not set
1235 # CONFIG_TYPHOON is not set
1236 CONFIG_NET_VENDOR_ADAPTEC=y
1237 # CONFIG_ADAPTEC_STARFIRE is not set
1238 CONFIG_NET_VENDOR_ALTEON=y
1239 # CONFIG_ACENIC is not set
1240 CONFIG_NET_VENDOR_AMD=y
1241 # CONFIG_AMD8111_ETH is not set
1242 # CONFIG_PCNET32 is not set
1243 CONFIG_NET_VENDOR_ATHEROS=y
1244 # CONFIG_ATL2 is not set
1245 # CONFIG_ATL1 is not set
1246 # CONFIG_ATL1E is not set
1247 # CONFIG_ATL1C is not set
1248 # CONFIG_ALX is not set
1087 CONFIG_NET_CADENCE=y 1249 CONFIG_NET_CADENCE=y
1088 # CONFIG_ARM_AT91_ETHER is not set 1250 # CONFIG_ARM_AT91_ETHER is not set
1089 # CONFIG_MACB is not set 1251 # CONFIG_MACB is not set
1090 # CONFIG_NET_VENDOR_BROADCOM is not set 1252 # CONFIG_NET_VENDOR_BROADCOM is not set
1253 CONFIG_NET_VENDOR_BROCADE=y
1254 # CONFIG_BNA is not set
1091 # CONFIG_NET_CALXEDA_XGMAC is not set 1255 # CONFIG_NET_CALXEDA_XGMAC is not set
1256 CONFIG_NET_VENDOR_CHELSIO=y
1257 # CONFIG_CHELSIO_T1 is not set
1258 # CONFIG_CHELSIO_T3 is not set
1259 # CONFIG_CHELSIO_T4 is not set
1260 # CONFIG_CHELSIO_T4VF is not set
1092 # CONFIG_NET_VENDOR_CIRRUS is not set 1261 # CONFIG_NET_VENDOR_CIRRUS is not set
1262 CONFIG_NET_VENDOR_CISCO=y
1263 # CONFIG_ENIC is not set
1093 # CONFIG_DM9000 is not set 1264 # CONFIG_DM9000 is not set
1094 # CONFIG_DNET is not set 1265 # CONFIG_DNET is not set
1266 CONFIG_NET_VENDOR_DEC=y
1267 # CONFIG_NET_TULIP is not set
1268 CONFIG_NET_VENDOR_DLINK=y
1269 # CONFIG_DL2K is not set
1270 # CONFIG_SUNDANCE is not set
1271 CONFIG_NET_VENDOR_EMULEX=y
1272 # CONFIG_BE2NET is not set
1273 CONFIG_NET_VENDOR_EXAR=y
1274 # CONFIG_S2IO is not set
1275 # CONFIG_VXGE is not set
1095 # CONFIG_NET_VENDOR_FARADAY is not set 1276 # CONFIG_NET_VENDOR_FARADAY is not set
1096 CONFIG_NET_VENDOR_FREESCALE=y 1277 CONFIG_NET_VENDOR_FREESCALE=y
1097 CONFIG_FEC=y 1278 CONFIG_FEC=y
1279 CONFIG_NET_VENDOR_HP=y
1280 # CONFIG_HP100 is not set
1098 # CONFIG_NET_VENDOR_INTEL is not set 1281 # CONFIG_NET_VENDOR_INTEL is not set
1282 # CONFIG_IP1000 is not set
1283 # CONFIG_JME is not set
1099 # CONFIG_NET_VENDOR_MARVELL is not set 1284 # CONFIG_NET_VENDOR_MARVELL is not set
1285 CONFIG_NET_VENDOR_MELLANOX=y
1286 # CONFIG_MLX4_EN is not set
1287 # CONFIG_MLX4_CORE is not set
1100 # CONFIG_NET_VENDOR_MICREL is not set 1288 # CONFIG_NET_VENDOR_MICREL is not set
1101 # CONFIG_NET_VENDOR_MICROCHIP is not set 1289 # CONFIG_NET_VENDOR_MICROCHIP is not set
1290 CONFIG_NET_VENDOR_MYRI=y
1291 # CONFIG_MYRI10GE is not set
1292 # CONFIG_FEALNX is not set
1102 # CONFIG_NET_VENDOR_NATSEMI is not set 1293 # CONFIG_NET_VENDOR_NATSEMI is not set
1294 CONFIG_NET_VENDOR_NVIDIA=y
1295 # CONFIG_FORCEDETH is not set
1296 CONFIG_NET_VENDOR_OKI=y
1297 # CONFIG_PCH_GBE is not set
1103 # CONFIG_ETHOC is not set 1298 # CONFIG_ETHOC is not set
1299 CONFIG_NET_PACKET_ENGINE=y
1300 # CONFIG_HAMACHI is not set
1301 # CONFIG_YELLOWFIN is not set
1302 CONFIG_NET_VENDOR_QLOGIC=y
1303 # CONFIG_QLA3XXX is not set
1304 # CONFIG_QLCNIC is not set
1305 # CONFIG_QLGE is not set
1306 # CONFIG_NETXEN_NIC is not set
1307 CONFIG_NET_VENDOR_REALTEK=y
1308 # CONFIG_8139CP is not set
1309 CONFIG_8139TOO=y
1310 CONFIG_8139TOO_PIO=y
1311 # CONFIG_8139TOO_TUNE_TWISTER is not set
1312 # CONFIG_8139TOO_8129 is not set
1313 # CONFIG_8139_OLD_RX_RESET is not set
1314 CONFIG_R8169=y
1315 CONFIG_NET_VENDOR_RDC=y
1316 # CONFIG_R6040 is not set
1104 # CONFIG_NET_VENDOR_SEEQ is not set 1317 # CONFIG_NET_VENDOR_SEEQ is not set
1318 CONFIG_NET_VENDOR_SILAN=y
1319 # CONFIG_SC92031 is not set
1320 CONFIG_NET_VENDOR_SIS=y
1321 # CONFIG_SIS900 is not set
1322 # CONFIG_SIS190 is not set
1323 # CONFIG_SFC is not set
1105 # CONFIG_NET_VENDOR_SMSC is not set 1324 # CONFIG_NET_VENDOR_SMSC is not set
1106 # CONFIG_NET_VENDOR_STMICRO is not set 1325 # CONFIG_NET_VENDOR_STMICRO is not set
1326 CONFIG_NET_VENDOR_SUN=y
1327 # CONFIG_HAPPYMEAL is not set
1328 # CONFIG_SUNGEM is not set
1329 # CONFIG_CASSINI is not set
1330 # CONFIG_NIU is not set
1331 CONFIG_NET_VENDOR_TEHUTI=y
1332 # CONFIG_TEHUTI is not set
1333 CONFIG_NET_VENDOR_TI=y
1334 # CONFIG_TLAN is not set
1335 CONFIG_NET_VENDOR_VIA=y
1336 # CONFIG_VIA_RHINE is not set
1337 # CONFIG_VIA_VELOCITY is not set
1107 # CONFIG_NET_VENDOR_WIZNET is not set 1338 # CONFIG_NET_VENDOR_WIZNET is not set
1339 # CONFIG_FDDI is not set
1340 # CONFIG_HIPPI is not set
1108 CONFIG_PHYLIB=y 1341 CONFIG_PHYLIB=y
1109 1342
1110 # 1343 #
1111 # MII PHY device drivers 1344 # MII PHY device drivers
1112 # 1345 #
1113 CONFIG_AT803X_PHY=y 1346 CONFIG_AT803X_PHY=y
1114 # CONFIG_AMD_PHY is not set 1347 # CONFIG_AMD_PHY is not set
1115 # CONFIG_MARVELL_PHY is not set 1348 # CONFIG_MARVELL_PHY is not set
1116 # CONFIG_DAVICOM_PHY is not set 1349 # CONFIG_DAVICOM_PHY is not set
1117 # CONFIG_QSEMI_PHY is not set 1350 # CONFIG_QSEMI_PHY is not set
1118 # CONFIG_LXT_PHY is not set 1351 # CONFIG_LXT_PHY is not set
1119 # CONFIG_CICADA_PHY is not set 1352 # CONFIG_CICADA_PHY is not set
1120 # CONFIG_VITESSE_PHY is not set 1353 # CONFIG_VITESSE_PHY is not set
1121 # CONFIG_SMSC_PHY is not set 1354 # CONFIG_SMSC_PHY is not set
1122 # CONFIG_BROADCOM_PHY is not set 1355 # CONFIG_BROADCOM_PHY is not set
1123 # CONFIG_BCM87XX_PHY is not set 1356 # CONFIG_BCM87XX_PHY is not set
1124 # CONFIG_ICPLUS_PHY is not set 1357 # CONFIG_ICPLUS_PHY is not set
1125 # CONFIG_REALTEK_PHY is not set 1358 # CONFIG_REALTEK_PHY is not set
1126 # CONFIG_NATIONAL_PHY is not set 1359 # CONFIG_NATIONAL_PHY is not set
1127 # CONFIG_STE10XP is not set 1360 # CONFIG_STE10XP is not set
1128 # CONFIG_LSI_ET1011C_PHY is not set 1361 # CONFIG_LSI_ET1011C_PHY is not set
1129 # CONFIG_MICREL_PHY is not set 1362 # CONFIG_MICREL_PHY is not set
1130 # CONFIG_FIXED_PHY is not set 1363 # CONFIG_FIXED_PHY is not set
1131 # CONFIG_MDIO_BITBANG is not set 1364 # CONFIG_MDIO_BITBANG is not set
1132 # CONFIG_MDIO_BUS_MUX_GPIO is not set 1365 # CONFIG_MDIO_BUS_MUX_GPIO is not set
1133 # CONFIG_MDIO_BUS_MUX_MMIOREG is not set 1366 # CONFIG_MDIO_BUS_MUX_MMIOREG is not set
1134 # CONFIG_MICREL_KS8995MA is not set 1367 # CONFIG_MICREL_KS8995MA is not set
1135 # CONFIG_PPP is not set 1368 # CONFIG_PPP is not set
1136 # CONFIG_SLIP is not set 1369 # CONFIG_SLIP is not set
1137 1370
1138 # 1371 #
1139 # USB Network Adapters 1372 # USB Network Adapters
1140 # 1373 #
1141 # CONFIG_USB_CATC is not set 1374 # CONFIG_USB_CATC is not set
1142 # CONFIG_USB_KAWETH is not set 1375 # CONFIG_USB_KAWETH is not set
1143 CONFIG_USB_PEGASUS=m 1376 CONFIG_USB_PEGASUS=m
1144 CONFIG_USB_RTL8150=m 1377 CONFIG_USB_RTL8150=m
1145 CONFIG_USB_RTL8152=m 1378 CONFIG_USB_RTL8152=m
1146 CONFIG_USB_USBNET=m 1379 CONFIG_USB_USBNET=m
1147 CONFIG_USB_NET_AX8817X=m 1380 CONFIG_USB_NET_AX8817X=m
1148 CONFIG_USB_NET_AX88179_178A=m 1381 CONFIG_USB_NET_AX88179_178A=m
1149 CONFIG_USB_NET_CDCETHER=m 1382 CONFIG_USB_NET_CDCETHER=m
1150 CONFIG_USB_NET_CDC_EEM=m 1383 CONFIG_USB_NET_CDC_EEM=m
1151 CONFIG_USB_NET_CDC_NCM=m 1384 CONFIG_USB_NET_CDC_NCM=m
1152 # CONFIG_USB_NET_CDC_MBIM is not set 1385 # CONFIG_USB_NET_CDC_MBIM is not set
1153 # CONFIG_USB_NET_DM9601 is not set 1386 # CONFIG_USB_NET_DM9601 is not set
1154 # CONFIG_USB_NET_SMSC75XX is not set 1387 # CONFIG_USB_NET_SMSC75XX is not set
1155 # CONFIG_USB_NET_SMSC95XX is not set 1388 # CONFIG_USB_NET_SMSC95XX is not set
1156 # CONFIG_USB_NET_GL620A is not set 1389 # CONFIG_USB_NET_GL620A is not set
1157 CONFIG_USB_NET_NET1080=m 1390 CONFIG_USB_NET_NET1080=m
1158 # CONFIG_USB_NET_PLUSB is not set 1391 # CONFIG_USB_NET_PLUSB is not set
1159 # CONFIG_USB_NET_MCS7830 is not set 1392 # CONFIG_USB_NET_MCS7830 is not set
1160 # CONFIG_USB_NET_RNDIS_HOST is not set 1393 # CONFIG_USB_NET_RNDIS_HOST is not set
1161 CONFIG_USB_NET_CDC_SUBSET=m 1394 CONFIG_USB_NET_CDC_SUBSET=m
1162 # CONFIG_USB_ALI_M5632 is not set 1395 # CONFIG_USB_ALI_M5632 is not set
1163 # CONFIG_USB_AN2720 is not set 1396 # CONFIG_USB_AN2720 is not set
1164 CONFIG_USB_BELKIN=y 1397 CONFIG_USB_BELKIN=y
1165 CONFIG_USB_ARMLINUX=y 1398 CONFIG_USB_ARMLINUX=y
1166 # CONFIG_USB_EPSON2888 is not set 1399 # CONFIG_USB_EPSON2888 is not set
1167 # CONFIG_USB_KC2190 is not set 1400 # CONFIG_USB_KC2190 is not set
1168 CONFIG_USB_NET_ZAURUS=m 1401 CONFIG_USB_NET_ZAURUS=m
1169 # CONFIG_USB_NET_CX82310_ETH is not set 1402 # CONFIG_USB_NET_CX82310_ETH is not set
1170 # CONFIG_USB_NET_KALMIA is not set 1403 # CONFIG_USB_NET_KALMIA is not set
1171 # CONFIG_USB_NET_QMI_WWAN is not set 1404 # CONFIG_USB_NET_QMI_WWAN is not set
1172 # CONFIG_USB_NET_INT51X1 is not set 1405 # CONFIG_USB_NET_INT51X1 is not set
1173 # CONFIG_USB_IPHETH is not set 1406 # CONFIG_USB_IPHETH is not set
1174 # CONFIG_USB_SIERRA_NET is not set 1407 # CONFIG_USB_SIERRA_NET is not set
1175 # CONFIG_USB_VL600 is not set 1408 # CONFIG_USB_VL600 is not set
1176 CONFIG_WLAN=y 1409 CONFIG_WLAN=y
1177 # CONFIG_LIBERTAS_THINFIRM is not set 1410 # CONFIG_LIBERTAS_THINFIRM is not set
1411 # CONFIG_ATMEL is not set
1178 # CONFIG_AT76C50X_USB is not set 1412 # CONFIG_AT76C50X_USB is not set
1413 # CONFIG_PRISM54 is not set
1179 # CONFIG_USB_ZD1201 is not set 1414 # CONFIG_USB_ZD1201 is not set
1180 # CONFIG_USB_NET_RNDIS_WLAN is not set 1415 # CONFIG_USB_NET_RNDIS_WLAN is not set
1416 # CONFIG_RTL8180 is not set
1181 # CONFIG_RTL8187 is not set 1417 # CONFIG_RTL8187 is not set
1418 # CONFIG_ADM8211 is not set
1182 # CONFIG_MAC80211_HWSIM is not set 1419 # CONFIG_MAC80211_HWSIM is not set
1420 # CONFIG_MWL8K is not set
1421 CONFIG_ATH_COMMON=m
1183 CONFIG_ATH_CARDS=y 1422 CONFIG_ATH_CARDS=y
1184 # CONFIG_ATH_DEBUG is not set 1423 # CONFIG_ATH_DEBUG is not set
1185 # CONFIG_ATH9K is not set 1424 # CONFIG_ATH5K is not set
1425 # CONFIG_ATH5K_PCI is not set
1426 CONFIG_ATH9K_HW=m
1427 CONFIG_ATH9K_COMMON=m
1428 # CONFIG_ATH9K_BTCOEX_SUPPORT is not set
1429 CONFIG_ATH9K=m
1430 CONFIG_ATH9K_PCI=y
1431 # CONFIG_ATH9K_AHB is not set
1432 # CONFIG_ATH9K_DEBUGFS is not set
1433 CONFIG_ATH9K_LEGACY_RATE_CONTROL=y
1186 # CONFIG_ATH9K_HTC is not set 1434 # CONFIG_ATH9K_HTC is not set
1187 # CONFIG_CARL9170 is not set 1435 # CONFIG_CARL9170 is not set
1188 CONFIG_ATH6KL=m 1436 # CONFIG_ATH6KL is not set
1189 CONFIG_ATH6KL_SDIO=m
1190 # CONFIG_ATH6KL_USB is not set
1191 # CONFIG_ATH6KL_DEBUG is not set
1192 # CONFIG_AR5523 is not set 1437 # CONFIG_AR5523 is not set
1438 # CONFIG_WIL6210 is not set
1193 # CONFIG_B43 is not set 1439 # CONFIG_B43 is not set
1194 # CONFIG_B43LEGACY is not set 1440 # CONFIG_B43LEGACY is not set
1195 # CONFIG_BRCMFMAC is not set 1441 # CONFIG_BRCMFMAC is not set
1196 # CONFIG_HOSTAP is not set 1442 # CONFIG_HOSTAP is not set
1443 # CONFIG_IPW2100 is not set
1444 # CONFIG_IPW2200 is not set
1445 # CONFIG_IWLWIFI is not set
1446 # CONFIG_IWL4965 is not set
1447 # CONFIG_IWL3945 is not set
1197 # CONFIG_LIBERTAS is not set 1448 # CONFIG_LIBERTAS is not set
1449 # CONFIG_HERMES is not set
1198 # CONFIG_P54_COMMON is not set 1450 # CONFIG_P54_COMMON is not set
1199 # CONFIG_RT2X00 is not set 1451 # CONFIG_RT2X00 is not set
1200 # CONFIG_RTLWIFI is not set 1452 # CONFIG_RTLWIFI is not set
1201 # CONFIG_WL_TI is not set 1453 # CONFIG_WL_TI is not set
1202 # CONFIG_ZD1211RW is not set 1454 # CONFIG_ZD1211RW is not set
1203 # CONFIG_MWIFIEX is not set 1455 # CONFIG_MWIFIEX is not set
1204 1456
1205 # 1457 #
1206 # Enable WiMAX (Networking options) to see the WiMAX drivers 1458 # Enable WiMAX (Networking options) to see the WiMAX drivers
1207 # 1459 #
1208 # CONFIG_WAN is not set 1460 # CONFIG_WAN is not set
1461 # CONFIG_VMXNET3 is not set
1209 # CONFIG_ISDN is not set 1462 # CONFIG_ISDN is not set
1210 1463
1211 # 1464 #
1212 # Input device support 1465 # Input device support
1213 # 1466 #
1214 CONFIG_INPUT=y 1467 CONFIG_INPUT=y
1215 # CONFIG_INPUT_FF_MEMLESS is not set 1468 # CONFIG_INPUT_FF_MEMLESS is not set
1216 CONFIG_INPUT_POLLDEV=y 1469 CONFIG_INPUT_POLLDEV=y
1217 # CONFIG_INPUT_SPARSEKMAP is not set 1470 # CONFIG_INPUT_SPARSEKMAP is not set
1218 CONFIG_INPUT_MATRIXKMAP=y 1471 CONFIG_INPUT_MATRIXKMAP=y
1219 1472
1220 # 1473 #
1221 # Userland interfaces 1474 # Userland interfaces
1222 # 1475 #
1223 CONFIG_INPUT_MOUSEDEV=y 1476 CONFIG_INPUT_MOUSEDEV=y
1224 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set 1477 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1225 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 1478 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1226 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 1479 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1227 # CONFIG_INPUT_JOYDEV is not set 1480 # CONFIG_INPUT_JOYDEV is not set
1228 CONFIG_INPUT_EVDEV=y 1481 CONFIG_INPUT_EVDEV=y
1229 CONFIG_INPUT_EVBUG=m 1482 CONFIG_INPUT_EVBUG=m
1230 # CONFIG_INPUT_APMPOWER is not set 1483 # CONFIG_INPUT_APMPOWER is not set
1231 1484
1232 # 1485 #
1233 # Input Device Drivers 1486 # Input Device Drivers
1234 # 1487 #
1235 CONFIG_INPUT_KEYBOARD=y 1488 CONFIG_INPUT_KEYBOARD=y
1236 # CONFIG_KEYBOARD_ADP5588 is not set 1489 # CONFIG_KEYBOARD_ADP5588 is not set
1237 # CONFIG_KEYBOARD_ADP5589 is not set 1490 # CONFIG_KEYBOARD_ADP5589 is not set
1238 CONFIG_KEYBOARD_ATKBD=y 1491 CONFIG_KEYBOARD_ATKBD=y
1239 # CONFIG_KEYBOARD_QT1070 is not set 1492 # CONFIG_KEYBOARD_QT1070 is not set
1240 # CONFIG_KEYBOARD_QT2160 is not set 1493 # CONFIG_KEYBOARD_QT2160 is not set
1241 # CONFIG_KEYBOARD_LKKBD is not set 1494 # CONFIG_KEYBOARD_LKKBD is not set
1242 CONFIG_KEYBOARD_GPIO=y 1495 CONFIG_KEYBOARD_GPIO=y
1243 # CONFIG_KEYBOARD_TCA6416 is not set 1496 # CONFIG_KEYBOARD_TCA6416 is not set
1244 # CONFIG_KEYBOARD_TCA8418 is not set 1497 # CONFIG_KEYBOARD_TCA8418 is not set
1245 # CONFIG_KEYBOARD_MATRIX is not set 1498 # CONFIG_KEYBOARD_MATRIX is not set
1246 # CONFIG_KEYBOARD_LM8323 is not set 1499 # CONFIG_KEYBOARD_LM8323 is not set
1247 # CONFIG_KEYBOARD_LM8333 is not set 1500 # CONFIG_KEYBOARD_LM8333 is not set
1248 # CONFIG_KEYBOARD_MAX7359 is not set 1501 # CONFIG_KEYBOARD_MAX7359 is not set
1249 # CONFIG_KEYBOARD_MCS is not set 1502 # CONFIG_KEYBOARD_MCS is not set
1250 # CONFIG_KEYBOARD_MPR121 is not set 1503 # CONFIG_KEYBOARD_MPR121 is not set
1251 CONFIG_KEYBOARD_SNVS_PWRKEY=y 1504 CONFIG_KEYBOARD_SNVS_PWRKEY=y
1252 CONFIG_KEYBOARD_IMX=y 1505 CONFIG_KEYBOARD_IMX=y
1253 # CONFIG_KEYBOARD_NEWTON is not set 1506 # CONFIG_KEYBOARD_NEWTON is not set
1254 # CONFIG_KEYBOARD_OPENCORES is not set 1507 # CONFIG_KEYBOARD_OPENCORES is not set
1255 # CONFIG_KEYBOARD_SAMSUNG is not set 1508 # CONFIG_KEYBOARD_SAMSUNG is not set
1256 # CONFIG_KEYBOARD_STOWAWAY is not set 1509 # CONFIG_KEYBOARD_STOWAWAY is not set
1257 # CONFIG_KEYBOARD_SUNKBD is not set 1510 # CONFIG_KEYBOARD_SUNKBD is not set
1258 # CONFIG_KEYBOARD_XTKBD is not set 1511 # CONFIG_KEYBOARD_XTKBD is not set
1259 CONFIG_INPUT_MOUSE=y 1512 CONFIG_INPUT_MOUSE=y
1260 CONFIG_MOUSE_PS2=m 1513 CONFIG_MOUSE_PS2=m
1261 CONFIG_MOUSE_PS2_ALPS=y 1514 CONFIG_MOUSE_PS2_ALPS=y
1262 CONFIG_MOUSE_PS2_LOGIPS2PP=y 1515 CONFIG_MOUSE_PS2_LOGIPS2PP=y
1263 CONFIG_MOUSE_PS2_SYNAPTICS=y 1516 CONFIG_MOUSE_PS2_SYNAPTICS=y
1264 CONFIG_MOUSE_PS2_CYPRESS=y 1517 CONFIG_MOUSE_PS2_CYPRESS=y
1265 CONFIG_MOUSE_PS2_TRACKPOINT=y 1518 CONFIG_MOUSE_PS2_TRACKPOINT=y
1266 CONFIG_MOUSE_PS2_ELANTECH=y 1519 CONFIG_MOUSE_PS2_ELANTECH=y
1267 # CONFIG_MOUSE_PS2_SENTELIC is not set 1520 # CONFIG_MOUSE_PS2_SENTELIC is not set
1268 # CONFIG_MOUSE_PS2_TOUCHKIT is not set 1521 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
1269 # CONFIG_MOUSE_SERIAL is not set 1522 # CONFIG_MOUSE_SERIAL is not set
1270 # CONFIG_MOUSE_APPLETOUCH is not set 1523 # CONFIG_MOUSE_APPLETOUCH is not set
1271 # CONFIG_MOUSE_BCM5974 is not set 1524 # CONFIG_MOUSE_BCM5974 is not set
1272 # CONFIG_MOUSE_CYAPA is not set 1525 # CONFIG_MOUSE_CYAPA is not set
1273 # CONFIG_MOUSE_VSXXXAA is not set 1526 # CONFIG_MOUSE_VSXXXAA is not set
1274 # CONFIG_MOUSE_GPIO is not set 1527 # CONFIG_MOUSE_GPIO is not set
1275 # CONFIG_MOUSE_SYNAPTICS_I2C is not set 1528 # CONFIG_MOUSE_SYNAPTICS_I2C is not set
1276 # CONFIG_MOUSE_SYNAPTICS_USB is not set 1529 # CONFIG_MOUSE_SYNAPTICS_USB is not set
1277 # CONFIG_INPUT_JOYSTICK is not set 1530 # CONFIG_INPUT_JOYSTICK is not set
1278 # CONFIG_INPUT_TABLET is not set 1531 # CONFIG_INPUT_TABLET is not set
1279 CONFIG_INPUT_TOUCHSCREEN=y 1532 CONFIG_INPUT_TOUCHSCREEN=y
1280 # CONFIG_TOUCHSCREEN_ADS7846 is not set 1533 # CONFIG_TOUCHSCREEN_ADS7846 is not set
1281 # CONFIG_TOUCHSCREEN_AD7877 is not set 1534 # CONFIG_TOUCHSCREEN_AD7877 is not set
1282 # CONFIG_TOUCHSCREEN_AD7879 is not set 1535 # CONFIG_TOUCHSCREEN_AD7879 is not set
1283 # CONFIG_TOUCHSCREEN_ATMEL_MXT is not set 1536 # CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
1284 # CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set 1537 # CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
1285 # CONFIG_TOUCHSCREEN_BU21013 is not set 1538 # CONFIG_TOUCHSCREEN_BU21013 is not set
1286 # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set 1539 # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
1287 # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set 1540 # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
1288 # CONFIG_TOUCHSCREEN_DA9052 is not set 1541 # CONFIG_TOUCHSCREEN_DA9052 is not set
1289 # CONFIG_TOUCHSCREEN_DYNAPRO is not set 1542 # CONFIG_TOUCHSCREEN_DYNAPRO is not set
1290 # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set 1543 # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
1291 # CONFIG_TOUCHSCREEN_EETI is not set 1544 # CONFIG_TOUCHSCREEN_EETI is not set
1292 # CONFIG_TOUCHSCREEN_EGALAX is not set 1545 # CONFIG_TOUCHSCREEN_EGALAX is not set
1293 # CONFIG_TOUCHSCREEN_ELAN is not set 1546 # CONFIG_TOUCHSCREEN_ELAN is not set
1294 # CONFIG_TOUCHSCREEN_FUJITSU is not set 1547 # CONFIG_TOUCHSCREEN_FUJITSU is not set
1295 # CONFIG_TOUCHSCREEN_ILI210X is not set 1548 # CONFIG_TOUCHSCREEN_ILI210X is not set
1296 # CONFIG_TOUCHSCREEN_GUNZE is not set 1549 # CONFIG_TOUCHSCREEN_GUNZE is not set
1297 # CONFIG_TOUCHSCREEN_ELO is not set 1550 # CONFIG_TOUCHSCREEN_ELO is not set
1298 # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set 1551 # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
1299 # CONFIG_TOUCHSCREEN_WACOM_I2C is not set 1552 # CONFIG_TOUCHSCREEN_WACOM_I2C is not set
1300 # CONFIG_TOUCHSCREEN_MAX11801 is not set 1553 # CONFIG_TOUCHSCREEN_MAX11801 is not set
1301 # CONFIG_TOUCHSCREEN_MCS5000 is not set 1554 # CONFIG_TOUCHSCREEN_MCS5000 is not set
1302 # CONFIG_TOUCHSCREEN_MMS114 is not set 1555 # CONFIG_TOUCHSCREEN_MMS114 is not set
1303 # CONFIG_TOUCHSCREEN_MTOUCH is not set 1556 # CONFIG_TOUCHSCREEN_MTOUCH is not set
1304 # CONFIG_TOUCHSCREEN_INEXIO is not set 1557 # CONFIG_TOUCHSCREEN_INEXIO is not set
1305 # CONFIG_TOUCHSCREEN_MK712 is not set 1558 # CONFIG_TOUCHSCREEN_MK712 is not set
1306 # CONFIG_TOUCHSCREEN_PENMOUNT is not set 1559 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
1307 # CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set 1560 # CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
1308 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set 1561 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
1309 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set 1562 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
1310 # CONFIG_TOUCHSCREEN_PIXCIR is not set 1563 # CONFIG_TOUCHSCREEN_PIXCIR is not set
1311 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set 1564 # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
1312 # CONFIG_TOUCHSCREEN_MC13783 is not set 1565 # CONFIG_TOUCHSCREEN_MC13783 is not set
1313 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set 1566 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
1314 # CONFIG_TOUCHSCREEN_TSC_SERIO is not set 1567 # CONFIG_TOUCHSCREEN_TSC_SERIO is not set
1315 # CONFIG_TOUCHSCREEN_TSC2005 is not set 1568 # CONFIG_TOUCHSCREEN_TSC2005 is not set
1316 # CONFIG_TOUCHSCREEN_TSC2007 is not set 1569 # CONFIG_TOUCHSCREEN_TSC2007 is not set
1317 # CONFIG_TOUCHSCREEN_W90X900 is not set 1570 # CONFIG_TOUCHSCREEN_W90X900 is not set
1318 # CONFIG_TOUCHSCREEN_ST1232 is not set 1571 # CONFIG_TOUCHSCREEN_ST1232 is not set
1319 # CONFIG_TOUCHSCREEN_TPS6507X is not set 1572 # CONFIG_TOUCHSCREEN_TPS6507X is not set
1320 CONFIG_INPUT_MISC=y 1573 CONFIG_INPUT_MISC=y
1321 # CONFIG_INPUT_AD714X is not set 1574 # CONFIG_INPUT_AD714X is not set
1322 # CONFIG_INPUT_BMA150 is not set 1575 # CONFIG_INPUT_BMA150 is not set
1323 # CONFIG_INPUT_MC13783_PWRBUTTON is not set 1576 # CONFIG_INPUT_MC13783_PWRBUTTON is not set
1324 CONFIG_INPUT_MMA8450=y 1577 CONFIG_INPUT_MMA8450=y
1325 # CONFIG_INPUT_MPU3050 is not set 1578 # CONFIG_INPUT_MPU3050 is not set
1326 # CONFIG_INPUT_GP2A is not set 1579 # CONFIG_INPUT_GP2A is not set
1327 # CONFIG_INPUT_GPIO_TILT_POLLED is not set 1580 # CONFIG_INPUT_GPIO_TILT_POLLED is not set
1328 # CONFIG_INPUT_ATI_REMOTE2 is not set 1581 # CONFIG_INPUT_ATI_REMOTE2 is not set
1329 # CONFIG_INPUT_KEYSPAN_REMOTE is not set 1582 # CONFIG_INPUT_KEYSPAN_REMOTE is not set
1330 # CONFIG_INPUT_KXTJ9 is not set 1583 # CONFIG_INPUT_KXTJ9 is not set
1331 # CONFIG_INPUT_POWERMATE is not set 1584 # CONFIG_INPUT_POWERMATE is not set
1332 # CONFIG_INPUT_YEALINK is not set 1585 # CONFIG_INPUT_YEALINK is not set
1333 # CONFIG_INPUT_CM109 is not set 1586 # CONFIG_INPUT_CM109 is not set
1334 # CONFIG_INPUT_UINPUT is not set 1587 # CONFIG_INPUT_UINPUT is not set
1335 # CONFIG_INPUT_PCF8574 is not set 1588 # CONFIG_INPUT_PCF8574 is not set
1336 # CONFIG_INPUT_PWM_BEEPER is not set 1589 # CONFIG_INPUT_PWM_BEEPER is not set
1337 # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set 1590 # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
1338 # CONFIG_INPUT_DA9052_ONKEY is not set 1591 # CONFIG_INPUT_DA9052_ONKEY is not set
1339 # CONFIG_INPUT_ADXL34X is not set 1592 # CONFIG_INPUT_ADXL34X is not set
1340 # CONFIG_INPUT_IMS_PCU is not set 1593 # CONFIG_INPUT_IMS_PCU is not set
1341 # CONFIG_INPUT_CMA3000 is not set 1594 # CONFIG_INPUT_CMA3000 is not set
1342 CONFIG_INPUT_ISL29023=y 1595 CONFIG_INPUT_ISL29023=y
1343 1596
1344 # 1597 #
1345 # Hardware I/O ports 1598 # Hardware I/O ports
1346 # 1599 #
1347 CONFIG_SERIO=y 1600 CONFIG_SERIO=y
1348 CONFIG_SERIO_SERPORT=m 1601 CONFIG_SERIO_SERPORT=m
1602 # CONFIG_SERIO_PCIPS2 is not set
1349 CONFIG_SERIO_LIBPS2=y 1603 CONFIG_SERIO_LIBPS2=y
1350 # CONFIG_SERIO_RAW is not set 1604 # CONFIG_SERIO_RAW is not set
1351 # CONFIG_SERIO_ALTERA_PS2 is not set 1605 # CONFIG_SERIO_ALTERA_PS2 is not set
1352 # CONFIG_SERIO_PS2MULT is not set 1606 # CONFIG_SERIO_PS2MULT is not set
1353 # CONFIG_SERIO_ARC_PS2 is not set 1607 # CONFIG_SERIO_ARC_PS2 is not set
1354 # CONFIG_SERIO_APBPS2 is not set 1608 # CONFIG_SERIO_APBPS2 is not set
1355 # CONFIG_GAMEPORT is not set 1609 # CONFIG_GAMEPORT is not set
1356 1610
1357 # 1611 #
1358 # Character devices 1612 # Character devices
1359 # 1613 #
1360 CONFIG_TTY=y 1614 CONFIG_TTY=y
1361 CONFIG_VT=y 1615 CONFIG_VT=y
1362 CONFIG_CONSOLE_TRANSLATIONS=y 1616 CONFIG_CONSOLE_TRANSLATIONS=y
1363 CONFIG_VT_CONSOLE=y 1617 CONFIG_VT_CONSOLE=y
1364 CONFIG_VT_CONSOLE_SLEEP=y 1618 CONFIG_VT_CONSOLE_SLEEP=y
1365 CONFIG_HW_CONSOLE=y 1619 CONFIG_HW_CONSOLE=y
1366 CONFIG_VT_HW_CONSOLE_BINDING=y 1620 CONFIG_VT_HW_CONSOLE_BINDING=y
1367 CONFIG_UNIX98_PTYS=y 1621 CONFIG_UNIX98_PTYS=y
1368 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 1622 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1369 # CONFIG_LEGACY_PTYS is not set 1623 # CONFIG_LEGACY_PTYS is not set
1370 # CONFIG_SERIAL_NONSTANDARD is not set 1624 # CONFIG_SERIAL_NONSTANDARD is not set
1625 # CONFIG_NOZOMI is not set
1371 # CONFIG_N_GSM is not set 1626 # CONFIG_N_GSM is not set
1372 # CONFIG_TRACE_SINK is not set 1627 # CONFIG_TRACE_SINK is not set
1373 # CONFIG_DEVKMEM is not set 1628 # CONFIG_DEVKMEM is not set
1374 1629
1375 # 1630 #
1376 # Serial drivers 1631 # Serial drivers
1377 # 1632 #
1378 # CONFIG_SERIAL_8250 is not set 1633 # CONFIG_SERIAL_8250 is not set
1379 1634
1380 # 1635 #
1381 # Non-8250 serial port support 1636 # Non-8250 serial port support
1382 # 1637 #
1383 # CONFIG_SERIAL_MAX3100 is not set 1638 # CONFIG_SERIAL_MAX3100 is not set
1384 # CONFIG_SERIAL_MAX310X is not set 1639 # CONFIG_SERIAL_MAX310X is not set
1640 # CONFIG_SERIAL_MFD_HSU is not set
1385 CONFIG_SERIAL_IMX=y 1641 CONFIG_SERIAL_IMX=y
1386 CONFIG_SERIAL_IMX_CONSOLE=y 1642 CONFIG_SERIAL_IMX_CONSOLE=y
1387 CONFIG_SERIAL_CORE=y 1643 CONFIG_SERIAL_CORE=y
1388 CONFIG_SERIAL_CORE_CONSOLE=y 1644 CONFIG_SERIAL_CORE_CONSOLE=y
1645 # CONFIG_SERIAL_JSM is not set
1389 # CONFIG_SERIAL_SCCNXP is not set 1646 # CONFIG_SERIAL_SCCNXP is not set
1390 # CONFIG_SERIAL_TIMBERDALE is not set 1647 # CONFIG_SERIAL_TIMBERDALE is not set
1391 # CONFIG_SERIAL_ALTERA_JTAGUART is not set 1648 # CONFIG_SERIAL_ALTERA_JTAGUART is not set
1392 # CONFIG_SERIAL_ALTERA_UART is not set 1649 # CONFIG_SERIAL_ALTERA_UART is not set
1393 # CONFIG_SERIAL_IFX6X60 is not set 1650 # CONFIG_SERIAL_IFX6X60 is not set
1651 # CONFIG_SERIAL_PCH_UART is not set
1394 # CONFIG_SERIAL_XILINX_PS_UART is not set 1652 # CONFIG_SERIAL_XILINX_PS_UART is not set
1395 # CONFIG_SERIAL_ARC is not set 1653 # CONFIG_SERIAL_ARC is not set
1654 # CONFIG_SERIAL_RP2 is not set
1396 CONFIG_SERIAL_FSL_LPUART=y 1655 CONFIG_SERIAL_FSL_LPUART=y
1397 CONFIG_SERIAL_FSL_LPUART_CONSOLE=y 1656 CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
1398 # CONFIG_TTY_PRINTK is not set 1657 # CONFIG_TTY_PRINTK is not set
1399 CONFIG_FSL_OTP=y 1658 CONFIG_FSL_OTP=y
1400 # CONFIG_HVC_DCC is not set 1659 # CONFIG_HVC_DCC is not set
1401 # CONFIG_IPMI_HANDLER is not set 1660 # CONFIG_IPMI_HANDLER is not set
1402 CONFIG_HW_RANDOM=y 1661 CONFIG_HW_RANDOM=y
1403 # CONFIG_HW_RANDOM_TIMERIOMEM is not set 1662 # CONFIG_HW_RANDOM_TIMERIOMEM is not set
1404 # CONFIG_HW_RANDOM_ATMEL is not set 1663 # CONFIG_HW_RANDOM_ATMEL is not set
1405 # CONFIG_HW_RANDOM_IMX_RNG is not set 1664 # CONFIG_HW_RANDOM_IMX_RNG is not set
1406 # CONFIG_HW_RANDOM_EXYNOS is not set 1665 # CONFIG_HW_RANDOM_EXYNOS is not set
1407 # CONFIG_R3964 is not set 1666 # CONFIG_R3964 is not set
1667 # CONFIG_APPLICOM is not set
1408 # CONFIG_RAW_DRIVER is not set 1668 # CONFIG_RAW_DRIVER is not set
1409 # CONFIG_TCG_TPM is not set 1669 # CONFIG_TCG_TPM is not set
1670 CONFIG_DEVPORT=y
1410 CONFIG_MXS_VIIM=y 1671 CONFIG_MXS_VIIM=y
1411 # CONFIG_XILLYBUS is not set 1672 # CONFIG_XILLYBUS is not set
1412 CONFIG_IMX_SEMA4=y 1673 CONFIG_IMX_SEMA4=y
1413 CONFIG_IMX_MCC_TEST=y 1674 CONFIG_IMX_MCC_TEST=y
1414 CONFIG_I2C=y 1675 CONFIG_I2C=y
1415 CONFIG_I2C_BOARDINFO=y 1676 CONFIG_I2C_BOARDINFO=y
1416 # CONFIG_I2C_COMPAT is not set 1677 # CONFIG_I2C_COMPAT is not set
1417 CONFIG_I2C_CHARDEV=y 1678 CONFIG_I2C_CHARDEV=y
1418 CONFIG_I2C_MUX=y 1679 CONFIG_I2C_MUX=y
1419 1680
1420 # 1681 #
1421 # Multiplexer I2C Chip support 1682 # Multiplexer I2C Chip support
1422 # 1683 #
1423 # CONFIG_I2C_ARB_GPIO_CHALLENGE is not set 1684 # CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
1424 # CONFIG_I2C_MUX_GPIO is not set 1685 # CONFIG_I2C_MUX_GPIO is not set
1425 # CONFIG_I2C_MUX_PCA9541 is not set 1686 # CONFIG_I2C_MUX_PCA9541 is not set
1426 CONFIG_I2C_MUX_PCA954x=y 1687 CONFIG_I2C_MUX_PCA954x=y
1427 # CONFIG_I2C_MUX_PINCTRL is not set 1688 # CONFIG_I2C_MUX_PINCTRL is not set
1428 # CONFIG_I2C_HELPER_AUTO is not set 1689 # CONFIG_I2C_HELPER_AUTO is not set
1429 # CONFIG_I2C_SMBUS is not set 1690 CONFIG_I2C_SMBUS=y
1430 1691
1431 # 1692 #
1432 # I2C Algorithms 1693 # I2C Algorithms
1433 # 1694 #
1434 CONFIG_I2C_ALGOBIT=y 1695 CONFIG_I2C_ALGOBIT=y
1435 CONFIG_I2C_ALGOPCF=m 1696 CONFIG_I2C_ALGOPCF=m
1436 CONFIG_I2C_ALGOPCA=m 1697 CONFIG_I2C_ALGOPCA=m
1437 1698
1438 # 1699 #
1439 # I2C Hardware Bus support 1700 # I2C Hardware Bus support
1440 # 1701 #
1441 1702
1442 # 1703 #
1704 # PC SMBus host controller drivers
1705 #
1706 # CONFIG_I2C_ALI1535 is not set
1707 # CONFIG_I2C_ALI1563 is not set
1708 # CONFIG_I2C_ALI15X3 is not set
1709 # CONFIG_I2C_AMD756 is not set
1710 # CONFIG_I2C_AMD8111 is not set
1711 # CONFIG_I2C_I801 is not set
1712 # CONFIG_I2C_ISCH is not set
1713 # CONFIG_I2C_PIIX4 is not set
1714 # CONFIG_I2C_NFORCE2 is not set
1715 # CONFIG_I2C_SIS5595 is not set
1716 # CONFIG_I2C_SIS630 is not set
1717 # CONFIG_I2C_SIS96X is not set
1718 # CONFIG_I2C_VIA is not set
1719 # CONFIG_I2C_VIAPRO is not set
1720
1721 #
1443 # I2C system bus drivers (mostly embedded / system-on-chip) 1722 # I2C system bus drivers (mostly embedded / system-on-chip)
1444 # 1723 #
1445 # CONFIG_I2C_CBUS_GPIO is not set 1724 # CONFIG_I2C_CBUS_GPIO is not set
1446 # CONFIG_I2C_DESIGNWARE_PLATFORM is not set 1725 # CONFIG_I2C_DESIGNWARE_PLATFORM is not set
1726 # CONFIG_I2C_DESIGNWARE_PCI is not set
1727 # CONFIG_I2C_EG20T is not set
1447 # CONFIG_I2C_GPIO is not set 1728 # CONFIG_I2C_GPIO is not set
1448 CONFIG_I2C_IMX=y 1729 CONFIG_I2C_IMX=y
1730 # CONFIG_I2C_INTEL_MID is not set
1449 # CONFIG_I2C_OCORES is not set 1731 # CONFIG_I2C_OCORES is not set
1450 # CONFIG_I2C_PCA_PLATFORM is not set 1732 # CONFIG_I2C_PCA_PLATFORM is not set
1451 # CONFIG_I2C_PXA_PCI is not set 1733 # CONFIG_I2C_PXA_PCI is not set
1452 # CONFIG_I2C_SIMTEC is not set 1734 # CONFIG_I2C_SIMTEC is not set
1453 # CONFIG_I2C_XILINX is not set 1735 # CONFIG_I2C_XILINX is not set
1454 1736
1455 # 1737 #
1456 # External I2C/SMBus adapter drivers 1738 # External I2C/SMBus adapter drivers
1457 # 1739 #
1458 # CONFIG_I2C_DIOLAN_U2C is not set 1740 # CONFIG_I2C_DIOLAN_U2C is not set
1459 # CONFIG_I2C_PARPORT_LIGHT is not set 1741 # CONFIG_I2C_PARPORT_LIGHT is not set
1460 # CONFIG_I2C_TAOS_EVM is not set 1742 # CONFIG_I2C_TAOS_EVM is not set
1461 # CONFIG_I2C_TINY_USB is not set 1743 # CONFIG_I2C_TINY_USB is not set
1462 1744
1463 # 1745 #
1464 # Other I2C/SMBus bus drivers 1746 # Other I2C/SMBus bus drivers
1465 # 1747 #
1466 # CONFIG_I2C_STUB is not set 1748 # CONFIG_I2C_STUB is not set
1467 # CONFIG_I2C_DEBUG_CORE is not set 1749 # CONFIG_I2C_DEBUG_CORE is not set
1468 # CONFIG_I2C_DEBUG_ALGO is not set 1750 # CONFIG_I2C_DEBUG_ALGO is not set
1469 # CONFIG_I2C_DEBUG_BUS is not set 1751 # CONFIG_I2C_DEBUG_BUS is not set
1470 CONFIG_SPI=y 1752 CONFIG_SPI=y
1471 # CONFIG_SPI_DEBUG is not set 1753 # CONFIG_SPI_DEBUG is not set
1472 CONFIG_SPI_MASTER=y 1754 CONFIG_SPI_MASTER=y
1473 1755
1474 # 1756 #
1475 # SPI Master Controller Drivers 1757 # SPI Master Controller Drivers
1476 # 1758 #
1477 # CONFIG_SPI_ALTERA is not set 1759 # CONFIG_SPI_ALTERA is not set
1478 CONFIG_SPI_BITBANG=y 1760 CONFIG_SPI_BITBANG=y
1479 # CONFIG_SPI_GPIO is not set 1761 # CONFIG_SPI_GPIO is not set
1480 CONFIG_SPI_IMX=y 1762 CONFIG_SPI_IMX=y
1481 # CONFIG_SPI_FSL_SPI is not set 1763 # CONFIG_SPI_FSL_SPI is not set
1482 # CONFIG_SPI_OC_TINY is not set 1764 # CONFIG_SPI_OC_TINY is not set
1765 # CONFIG_SPI_PXA2XX is not set
1483 # CONFIG_SPI_PXA2XX_PCI is not set 1766 # CONFIG_SPI_PXA2XX_PCI is not set
1484 # CONFIG_SPI_SC18IS602 is not set 1767 # CONFIG_SPI_SC18IS602 is not set
1768 # CONFIG_SPI_TOPCLIFF_PCH is not set
1485 # CONFIG_SPI_XCOMM is not set 1769 # CONFIG_SPI_XCOMM is not set
1486 # CONFIG_SPI_XILINX is not set 1770 # CONFIG_SPI_XILINX is not set
1487 # CONFIG_SPI_DESIGNWARE is not set 1771 # CONFIG_SPI_DESIGNWARE is not set
1488 1772
1489 # 1773 #
1490 # SPI Protocol Masters 1774 # SPI Protocol Masters
1491 # 1775 #
1492 CONFIG_SPI_SPIDEV=y 1776 CONFIG_SPI_SPIDEV=y
1493 # CONFIG_SPI_TLE62X0 is not set 1777 # CONFIG_SPI_TLE62X0 is not set
1494 1778
1495 # 1779 #
1496 # Qualcomm MSM SSBI bus support 1780 # Qualcomm MSM SSBI bus support
1497 # 1781 #
1498 # CONFIG_SSBI is not set 1782 # CONFIG_SSBI is not set
1499 # CONFIG_HSI is not set 1783 # CONFIG_HSI is not set
1500 1784
1501 # 1785 #
1502 # PPS support 1786 # PPS support
1503 # 1787 #
1504 CONFIG_PPS=y 1788 CONFIG_PPS=y
1505 # CONFIG_PPS_DEBUG is not set 1789 # CONFIG_PPS_DEBUG is not set
1506 1790
1507 # 1791 #
1508 # PPS clients support 1792 # PPS clients support
1509 # 1793 #
1510 # CONFIG_PPS_CLIENT_KTIMER is not set 1794 # CONFIG_PPS_CLIENT_KTIMER is not set
1511 # CONFIG_PPS_CLIENT_LDISC is not set 1795 # CONFIG_PPS_CLIENT_LDISC is not set
1512 # CONFIG_PPS_CLIENT_GPIO is not set 1796 # CONFIG_PPS_CLIENT_GPIO is not set
1513 1797
1514 # 1798 #
1515 # PPS generators support 1799 # PPS generators support
1516 # 1800 #
1517 1801
1518 # 1802 #
1519 # PTP clock support 1803 # PTP clock support
1520 # 1804 #
1521 CONFIG_PTP_1588_CLOCK=y 1805 CONFIG_PTP_1588_CLOCK=y
1522 1806
1523 # 1807 #
1524 # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. 1808 # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
1525 # 1809 #
1526 # CONFIG_PTP_1588_CLOCK_PCH is not set 1810 # CONFIG_PTP_1588_CLOCK_PCH is not set
1527 CONFIG_PINCTRL=y 1811 CONFIG_PINCTRL=y
1528 1812
1529 # 1813 #
1530 # Pin controllers 1814 # Pin controllers
1531 # 1815 #
1532 CONFIG_PINMUX=y 1816 CONFIG_PINMUX=y
1533 CONFIG_PINCONF=y 1817 CONFIG_PINCONF=y
1534 # CONFIG_DEBUG_PINCTRL is not set 1818 # CONFIG_DEBUG_PINCTRL is not set
1535 CONFIG_PINCTRL_IMX=y 1819 CONFIG_PINCTRL_IMX=y
1536 CONFIG_PINCTRL_IMX51=y 1820 CONFIG_PINCTRL_IMX51=y
1537 CONFIG_PINCTRL_IMX53=y 1821 CONFIG_PINCTRL_IMX53=y
1538 CONFIG_PINCTRL_IMX6Q=y 1822 CONFIG_PINCTRL_IMX6Q=y
1539 CONFIG_PINCTRL_IMX6SL=y 1823 CONFIG_PINCTRL_IMX6SL=y
1540 CONFIG_PINCTRL_IMX6SX=y 1824 CONFIG_PINCTRL_IMX6SX=y
1541 CONFIG_PINCTRL_VF610=y 1825 CONFIG_PINCTRL_VF610=y
1542 # CONFIG_PINCTRL_SINGLE is not set 1826 # CONFIG_PINCTRL_SINGLE is not set
1543 # CONFIG_PINCTRL_EXYNOS is not set 1827 # CONFIG_PINCTRL_EXYNOS is not set
1544 # CONFIG_PINCTRL_EXYNOS5440 is not set 1828 # CONFIG_PINCTRL_EXYNOS5440 is not set
1545 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y 1829 CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
1546 CONFIG_ARCH_REQUIRE_GPIOLIB=y 1830 CONFIG_ARCH_REQUIRE_GPIOLIB=y
1547 CONFIG_GPIO_DEVRES=y 1831 CONFIG_GPIO_DEVRES=y
1548 CONFIG_GPIOLIB=y 1832 CONFIG_GPIOLIB=y
1549 CONFIG_OF_GPIO=y 1833 CONFIG_OF_GPIO=y
1550 # CONFIG_DEBUG_GPIO is not set 1834 # CONFIG_DEBUG_GPIO is not set
1551 CONFIG_GPIO_SYSFS=y 1835 CONFIG_GPIO_SYSFS=y
1552 CONFIG_GPIO_GENERIC=y 1836 CONFIG_GPIO_GENERIC=y
1553 # CONFIG_GPIO_DA9052 is not set 1837 # CONFIG_GPIO_DA9052 is not set
1554 1838
1555 # 1839 #
1556 # Memory mapped GPIO drivers: 1840 # Memory mapped GPIO drivers:
1557 # 1841 #
1558 # CONFIG_GPIO_GENERIC_PLATFORM is not set 1842 # CONFIG_GPIO_GENERIC_PLATFORM is not set
1559 # CONFIG_GPIO_EM is not set 1843 # CONFIG_GPIO_EM is not set
1560 CONFIG_GPIO_MXC=y 1844 CONFIG_GPIO_MXC=y
1561 # CONFIG_GPIO_RCAR is not set 1845 # CONFIG_GPIO_RCAR is not set
1562 # CONFIG_GPIO_TS5500 is not set 1846 # CONFIG_GPIO_TS5500 is not set
1847 # CONFIG_GPIO_VX855 is not set
1563 # CONFIG_GPIO_GRGPIO is not set 1848 # CONFIG_GPIO_GRGPIO is not set
1564 1849
1565 # 1850 #
1566 # I2C GPIO expanders: 1851 # I2C GPIO expanders:
1567 # 1852 #
1568 # CONFIG_GPIO_MAX7300 is not set 1853 # CONFIG_GPIO_MAX7300 is not set
1569 CONFIG_GPIO_MAX732X=y 1854 CONFIG_GPIO_MAX732X=y
1570 # CONFIG_GPIO_MAX732X_IRQ is not set 1855 # CONFIG_GPIO_MAX732X_IRQ is not set
1571 # CONFIG_GPIO_PCA953X_IRQ is not set 1856 # CONFIG_GPIO_PCA953X_IRQ is not set
1572 # CONFIG_GPIO_PCF857X is not set 1857 # CONFIG_GPIO_PCF857X is not set
1573 # CONFIG_GPIO_SX150X is not set 1858 # CONFIG_GPIO_SX150X is not set
1574 # CONFIG_GPIO_ADP5588 is not set 1859 # CONFIG_GPIO_ADP5588 is not set
1575 # CONFIG_GPIO_ADNP is not set 1860 # CONFIG_GPIO_ADNP is not set
1576 1861
1577 # 1862 #
1578 # PCI GPIO expanders: 1863 # PCI GPIO expanders:
1579 # 1864 #
1865 # CONFIG_GPIO_BT8XX is not set
1866 # CONFIG_GPIO_AMD8111 is not set
1867 # CONFIG_GPIO_ML_IOH is not set
1868 # CONFIG_GPIO_RDC321X is not set
1580 1869
1581 # 1870 #
1582 # SPI GPIO expanders: 1871 # SPI GPIO expanders:
1583 # 1872 #
1584 # CONFIG_GPIO_MAX7301 is not set 1873 # CONFIG_GPIO_MAX7301 is not set
1585 # CONFIG_GPIO_MCP23S08 is not set 1874 # CONFIG_GPIO_MCP23S08 is not set
1586 # CONFIG_GPIO_MC33880 is not set 1875 # CONFIG_GPIO_MC33880 is not set
1587 # CONFIG_GPIO_74X164 is not set 1876 # CONFIG_GPIO_74X164 is not set
1588 1877
1589 # 1878 #
1590 # AC97 GPIO expanders: 1879 # AC97 GPIO expanders:
1591 # 1880 #
1592 1881
1593 # 1882 #
1594 # MODULbus GPIO expanders: 1883 # MODULbus GPIO expanders:
1595 # 1884 #
1596 1885
1597 # 1886 #
1598 # USB GPIO expanders: 1887 # USB GPIO expanders:
1599 # 1888 #
1600 # CONFIG_W1 is not set 1889 # CONFIG_W1 is not set
1601 CONFIG_POWER_SUPPLY=y 1890 CONFIG_POWER_SUPPLY=y
1602 # CONFIG_POWER_SUPPLY_DEBUG is not set 1891 # CONFIG_POWER_SUPPLY_DEBUG is not set
1603 # CONFIG_PDA_POWER is not set 1892 # CONFIG_PDA_POWER is not set
1604 # CONFIG_APM_POWER is not set 1893 # CONFIG_APM_POWER is not set
1605 # CONFIG_GENERIC_ADC_BATTERY is not set 1894 # CONFIG_GENERIC_ADC_BATTERY is not set
1606 # CONFIG_TEST_POWER is not set 1895 # CONFIG_TEST_POWER is not set
1607 # CONFIG_BATTERY_DS2780 is not set 1896 # CONFIG_BATTERY_DS2780 is not set
1608 # CONFIG_BATTERY_DS2781 is not set 1897 # CONFIG_BATTERY_DS2781 is not set
1609 # CONFIG_BATTERY_DS2782 is not set 1898 # CONFIG_BATTERY_DS2782 is not set
1610 # CONFIG_BATTERY_SBS is not set 1899 # CONFIG_BATTERY_SBS is not set
1611 # CONFIG_BATTERY_BQ27x00 is not set 1900 # CONFIG_BATTERY_BQ27x00 is not set
1612 # CONFIG_BATTERY_DA9052 is not set 1901 # CONFIG_BATTERY_DA9052 is not set
1613 # CONFIG_BATTERY_MAX17040 is not set 1902 # CONFIG_BATTERY_MAX17040 is not set
1614 # CONFIG_BATTERY_MAX17042 is not set 1903 # CONFIG_BATTERY_MAX17042 is not set
1615 # CONFIG_CHARGER_ISP1704 is not set 1904 # CONFIG_CHARGER_ISP1704 is not set
1616 # CONFIG_CHARGER_MAX8903 is not set 1905 # CONFIG_CHARGER_MAX8903 is not set
1617 # CONFIG_CHARGER_LP8727 is not set 1906 # CONFIG_CHARGER_LP8727 is not set
1618 # CONFIG_CHARGER_GPIO is not set 1907 # CONFIG_CHARGER_GPIO is not set
1619 # CONFIG_CHARGER_MANAGER is not set 1908 # CONFIG_CHARGER_MANAGER is not set
1620 # CONFIG_CHARGER_BQ2415X is not set 1909 # CONFIG_CHARGER_BQ2415X is not set
1910 CONFIG_CHARGER_BQ2477X=y
1621 # CONFIG_CHARGER_SMB347 is not set 1911 # CONFIG_CHARGER_SMB347 is not set
1622 # CONFIG_BATTERY_GOLDFISH is not set 1912 # CONFIG_BATTERY_GOLDFISH is not set
1623 CONFIG_IMX6_USB_CHARGER=y 1913 CONFIG_IMX6_USB_CHARGER=y
1624 # CONFIG_POWER_RESET is not set 1914 # CONFIG_POWER_RESET is not set
1625 # CONFIG_POWER_RESET_RESTART is not set 1915 # CONFIG_POWER_RESET_RESTART is not set
1626 # CONFIG_POWER_AVS is not set 1916 # CONFIG_POWER_AVS is not set
1627 CONFIG_HWMON=y 1917 CONFIG_HWMON=y
1628 # CONFIG_HWMON_VID is not set 1918 # CONFIG_HWMON_VID is not set
1629 # CONFIG_HWMON_DEBUG_CHIP is not set 1919 # CONFIG_HWMON_DEBUG_CHIP is not set
1630 1920
1631 # 1921 #
1632 # Native drivers 1922 # Native drivers
1633 # 1923 #
1634 # CONFIG_SENSORS_AD7314 is not set 1924 # CONFIG_SENSORS_AD7314 is not set
1635 # CONFIG_SENSORS_AD7414 is not set 1925 # CONFIG_SENSORS_AD7414 is not set
1636 # CONFIG_SENSORS_AD7418 is not set 1926 # CONFIG_SENSORS_AD7418 is not set
1637 # CONFIG_SENSORS_ADCXX is not set 1927 # CONFIG_SENSORS_ADCXX is not set
1638 # CONFIG_SENSORS_ADM1021 is not set 1928 # CONFIG_SENSORS_ADM1021 is not set
1639 # CONFIG_SENSORS_ADM1025 is not set 1929 # CONFIG_SENSORS_ADM1025 is not set
1640 # CONFIG_SENSORS_ADM1026 is not set 1930 # CONFIG_SENSORS_ADM1026 is not set
1641 # CONFIG_SENSORS_ADM1029 is not set 1931 # CONFIG_SENSORS_ADM1029 is not set
1642 # CONFIG_SENSORS_ADM1031 is not set 1932 # CONFIG_SENSORS_ADM1031 is not set
1643 # CONFIG_SENSORS_ADM9240 is not set 1933 # CONFIG_SENSORS_ADM9240 is not set
1644 # CONFIG_SENSORS_ADT7310 is not set 1934 # CONFIG_SENSORS_ADT7310 is not set
1645 # CONFIG_SENSORS_ADT7410 is not set 1935 # CONFIG_SENSORS_ADT7410 is not set
1646 # CONFIG_SENSORS_ADT7411 is not set 1936 # CONFIG_SENSORS_ADT7411 is not set
1647 # CONFIG_SENSORS_ADT7462 is not set 1937 # CONFIG_SENSORS_ADT7462 is not set
1648 # CONFIG_SENSORS_ADT7470 is not set 1938 # CONFIG_SENSORS_ADT7470 is not set
1649 # CONFIG_SENSORS_ADT7475 is not set 1939 # CONFIG_SENSORS_ADT7475 is not set
1650 # CONFIG_SENSORS_ASC7621 is not set 1940 # CONFIG_SENSORS_ASC7621 is not set
1651 # CONFIG_SENSORS_ATXP1 is not set 1941 # CONFIG_SENSORS_ATXP1 is not set
1652 # CONFIG_SENSORS_DS620 is not set 1942 # CONFIG_SENSORS_DS620 is not set
1653 # CONFIG_SENSORS_DS1621 is not set 1943 # CONFIG_SENSORS_DS1621 is not set
1654 # CONFIG_SENSORS_DA9052_ADC is not set 1944 # CONFIG_SENSORS_DA9052_ADC is not set
1945 # CONFIG_SENSORS_I5K_AMB is not set
1655 # CONFIG_SENSORS_F71805F is not set 1946 # CONFIG_SENSORS_F71805F is not set
1656 # CONFIG_SENSORS_F71882FG is not set 1947 # CONFIG_SENSORS_F71882FG is not set
1657 # CONFIG_SENSORS_F75375S is not set 1948 # CONFIG_SENSORS_F75375S is not set
1658 # CONFIG_SENSORS_G760A is not set 1949 # CONFIG_SENSORS_G760A is not set
1659 # CONFIG_SENSORS_GL518SM is not set 1950 # CONFIG_SENSORS_GL518SM is not set
1660 # CONFIG_SENSORS_GL520SM is not set 1951 # CONFIG_SENSORS_GL520SM is not set
1661 # CONFIG_SENSORS_GPIO_FAN is not set 1952 # CONFIG_SENSORS_GPIO_FAN is not set
1662 # CONFIG_SENSORS_HIH6130 is not set 1953 # CONFIG_SENSORS_HIH6130 is not set
1663 # CONFIG_SENSORS_IIO_HWMON is not set 1954 # CONFIG_SENSORS_IIO_HWMON is not set
1664 # CONFIG_SENSORS_IT87 is not set 1955 # CONFIG_SENSORS_IT87 is not set
1665 # CONFIG_SENSORS_JC42 is not set 1956 # CONFIG_SENSORS_JC42 is not set
1666 # CONFIG_SENSORS_LINEAGE is not set 1957 # CONFIG_SENSORS_LINEAGE is not set
1667 # CONFIG_SENSORS_LM63 is not set 1958 # CONFIG_SENSORS_LM63 is not set
1668 # CONFIG_SENSORS_LM70 is not set 1959 # CONFIG_SENSORS_LM70 is not set
1669 # CONFIG_SENSORS_LM73 is not set 1960 # CONFIG_SENSORS_LM73 is not set
1670 # CONFIG_SENSORS_LM75 is not set 1961 # CONFIG_SENSORS_LM75 is not set
1671 # CONFIG_SENSORS_LM77 is not set 1962 # CONFIG_SENSORS_LM77 is not set
1672 # CONFIG_SENSORS_LM78 is not set 1963 # CONFIG_SENSORS_LM78 is not set
1673 # CONFIG_SENSORS_LM80 is not set 1964 # CONFIG_SENSORS_LM80 is not set
1674 # CONFIG_SENSORS_LM83 is not set 1965 # CONFIG_SENSORS_LM83 is not set
1675 # CONFIG_SENSORS_LM85 is not set 1966 # CONFIG_SENSORS_LM85 is not set
1676 # CONFIG_SENSORS_LM87 is not set 1967 # CONFIG_SENSORS_LM87 is not set
1677 # CONFIG_SENSORS_LM90 is not set 1968 # CONFIG_SENSORS_LM90 is not set
1678 # CONFIG_SENSORS_LM92 is not set 1969 # CONFIG_SENSORS_LM92 is not set
1679 # CONFIG_SENSORS_LM93 is not set 1970 # CONFIG_SENSORS_LM93 is not set
1680 # CONFIG_SENSORS_LTC4151 is not set 1971 # CONFIG_SENSORS_LTC4151 is not set
1681 # CONFIG_SENSORS_LTC4215 is not set 1972 # CONFIG_SENSORS_LTC4215 is not set
1682 # CONFIG_SENSORS_LTC4245 is not set 1973 # CONFIG_SENSORS_LTC4245 is not set
1683 # CONFIG_SENSORS_LTC4261 is not set 1974 # CONFIG_SENSORS_LTC4261 is not set
1684 # CONFIG_SENSORS_LM95234 is not set 1975 # CONFIG_SENSORS_LM95234 is not set
1685 # CONFIG_SENSORS_LM95241 is not set 1976 # CONFIG_SENSORS_LM95241 is not set
1686 # CONFIG_SENSORS_LM95245 is not set 1977 # CONFIG_SENSORS_LM95245 is not set
1687 # CONFIG_SENSORS_MAX1111 is not set 1978 # CONFIG_SENSORS_MAX1111 is not set
1688 # CONFIG_SENSORS_MAX16065 is not set 1979 # CONFIG_SENSORS_MAX16065 is not set
1689 # CONFIG_SENSORS_MAX1619 is not set 1980 # CONFIG_SENSORS_MAX1619 is not set
1690 # CONFIG_SENSORS_MAX1668 is not set 1981 # CONFIG_SENSORS_MAX1668 is not set
1691 CONFIG_SENSORS_MAX17135=y 1982 CONFIG_SENSORS_MAX17135=y
1692 # CONFIG_SENSORS_MAX197 is not set 1983 # CONFIG_SENSORS_MAX197 is not set
1693 # CONFIG_SENSORS_MAX6639 is not set 1984 # CONFIG_SENSORS_MAX6639 is not set
1694 # CONFIG_SENSORS_MAX6642 is not set 1985 # CONFIG_SENSORS_MAX6642 is not set
1695 # CONFIG_SENSORS_MAX6650 is not set 1986 # CONFIG_SENSORS_MAX6650 is not set
1696 # CONFIG_SENSORS_MAX6697 is not set 1987 # CONFIG_SENSORS_MAX6697 is not set
1697 # CONFIG_SENSORS_MCP3021 is not set 1988 # CONFIG_SENSORS_MCP3021 is not set
1698 # CONFIG_SENSORS_NCT6775 is not set 1989 # CONFIG_SENSORS_NCT6775 is not set
1699 # CONFIG_SENSORS_NTC_THERMISTOR is not set 1990 # CONFIG_SENSORS_NTC_THERMISTOR is not set
1700 # CONFIG_SENSORS_PC87360 is not set 1991 # CONFIG_SENSORS_PC87360 is not set
1701 # CONFIG_SENSORS_PC87427 is not set 1992 # CONFIG_SENSORS_PC87427 is not set
1702 # CONFIG_SENSORS_PCF8591 is not set 1993 # CONFIG_SENSORS_PCF8591 is not set
1703 # CONFIG_PMBUS is not set 1994 # CONFIG_PMBUS is not set
1704 # CONFIG_SENSORS_SHT15 is not set 1995 # CONFIG_SENSORS_SHT15 is not set
1705 # CONFIG_SENSORS_SHT21 is not set 1996 # CONFIG_SENSORS_SHT21 is not set
1997 # CONFIG_SENSORS_SIS5595 is not set
1706 # CONFIG_SENSORS_SMM665 is not set 1998 # CONFIG_SENSORS_SMM665 is not set
1707 # CONFIG_SENSORS_DME1737 is not set 1999 # CONFIG_SENSORS_DME1737 is not set
1708 # CONFIG_SENSORS_EMC1403 is not set 2000 # CONFIG_SENSORS_EMC1403 is not set
1709 # CONFIG_SENSORS_EMC2103 is not set 2001 # CONFIG_SENSORS_EMC2103 is not set
1710 # CONFIG_SENSORS_EMC6W201 is not set 2002 # CONFIG_SENSORS_EMC6W201 is not set
1711 # CONFIG_SENSORS_SMSC47M1 is not set 2003 # CONFIG_SENSORS_SMSC47M1 is not set
1712 # CONFIG_SENSORS_SMSC47M192 is not set 2004 # CONFIG_SENSORS_SMSC47M192 is not set
1713 # CONFIG_SENSORS_SMSC47B397 is not set 2005 # CONFIG_SENSORS_SMSC47B397 is not set
1714 # CONFIG_SENSORS_SCH56XX_COMMON is not set 2006 # CONFIG_SENSORS_SCH56XX_COMMON is not set
1715 # CONFIG_SENSORS_SCH5627 is not set 2007 # CONFIG_SENSORS_SCH5627 is not set
1716 # CONFIG_SENSORS_SCH5636 is not set 2008 # CONFIG_SENSORS_SCH5636 is not set
1717 # CONFIG_SENSORS_ADS1015 is not set 2009 # CONFIG_SENSORS_ADS1015 is not set
1718 # CONFIG_SENSORS_ADS7828 is not set 2010 # CONFIG_SENSORS_ADS7828 is not set
1719 # CONFIG_SENSORS_ADS7871 is not set 2011 # CONFIG_SENSORS_ADS7871 is not set
1720 # CONFIG_SENSORS_AMC6821 is not set 2012 # CONFIG_SENSORS_AMC6821 is not set
1721 # CONFIG_SENSORS_INA209 is not set 2013 # CONFIG_SENSORS_INA209 is not set
1722 # CONFIG_SENSORS_INA2XX is not set 2014 # CONFIG_SENSORS_INA2XX is not set
1723 # CONFIG_SENSORS_THMC50 is not set 2015 # CONFIG_SENSORS_THMC50 is not set
1724 # CONFIG_SENSORS_TMP102 is not set 2016 # CONFIG_SENSORS_TMP102 is not set
1725 # CONFIG_SENSORS_TMP401 is not set 2017 # CONFIG_SENSORS_TMP401 is not set
1726 # CONFIG_SENSORS_TMP421 is not set 2018 # CONFIG_SENSORS_TMP421 is not set
2019 # CONFIG_SENSORS_VIA686A is not set
1727 # CONFIG_SENSORS_VT1211 is not set 2020 # CONFIG_SENSORS_VT1211 is not set
2021 # CONFIG_SENSORS_VT8231 is not set
1728 # CONFIG_SENSORS_W83781D is not set 2022 # CONFIG_SENSORS_W83781D is not set
1729 # CONFIG_SENSORS_W83791D is not set 2023 # CONFIG_SENSORS_W83791D is not set
1730 # CONFIG_SENSORS_W83792D is not set 2024 # CONFIG_SENSORS_W83792D is not set
1731 # CONFIG_SENSORS_W83793 is not set 2025 # CONFIG_SENSORS_W83793 is not set
1732 # CONFIG_SENSORS_W83795 is not set 2026 # CONFIG_SENSORS_W83795 is not set
1733 # CONFIG_SENSORS_W83L785TS is not set 2027 # CONFIG_SENSORS_W83L785TS is not set
1734 # CONFIG_SENSORS_W83L786NG is not set 2028 # CONFIG_SENSORS_W83L786NG is not set
1735 # CONFIG_SENSORS_W83627HF is not set 2029 # CONFIG_SENSORS_W83627HF is not set
1736 # CONFIG_SENSORS_W83627EHF is not set 2030 # CONFIG_SENSORS_W83627EHF is not set
1737 # CONFIG_SENSORS_MC13783_ADC is not set 2031 # CONFIG_SENSORS_MC13783_ADC is not set
1738 CONFIG_SENSORS_MAG3110=y 2032 CONFIG_SENSORS_MAG3110=y
1739 CONFIG_MXC_MMA8451=y 2033 CONFIG_MXC_MMA8451=y
1740 # CONFIG_MXC_MMA8x5x is not set 2034 # CONFIG_MXC_MMA8x5x is not set
1741 CONFIG_THERMAL=y 2035 CONFIG_THERMAL=y
1742 CONFIG_THERMAL_HWMON=y 2036 CONFIG_THERMAL_HWMON=y
1743 CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y 2037 CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
1744 # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set 2038 # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
1745 # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set 2039 # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
1746 # CONFIG_THERMAL_GOV_FAIR_SHARE is not set 2040 # CONFIG_THERMAL_GOV_FAIR_SHARE is not set
1747 CONFIG_THERMAL_GOV_STEP_WISE=y 2041 CONFIG_THERMAL_GOV_STEP_WISE=y
1748 # CONFIG_THERMAL_GOV_USER_SPACE is not set 2042 # CONFIG_THERMAL_GOV_USER_SPACE is not set
1749 CONFIG_CPU_THERMAL=y 2043 CONFIG_CPU_THERMAL=y
1750 # CONFIG_THERMAL_EMULATION is not set 2044 # CONFIG_THERMAL_EMULATION is not set
1751 CONFIG_IMX_THERMAL=y 2045 CONFIG_IMX_THERMAL=y
1752 CONFIG_DEVICE_THERMAL=y 2046 CONFIG_DEVICE_THERMAL=y
1753 CONFIG_WATCHDOG=y 2047 CONFIG_WATCHDOG=y
1754 # CONFIG_WATCHDOG_CORE is not set 2048 # CONFIG_WATCHDOG_CORE is not set
1755 # CONFIG_WATCHDOG_NOWAYOUT is not set 2049 # CONFIG_WATCHDOG_NOWAYOUT is not set
1756 2050
1757 # 2051 #
1758 # Watchdog Device Drivers 2052 # Watchdog Device Drivers
1759 # 2053 #
1760 # CONFIG_SOFT_WATCHDOG is not set 2054 # CONFIG_SOFT_WATCHDOG is not set
1761 # CONFIG_DA9052_WATCHDOG is not set 2055 # CONFIG_DA9052_WATCHDOG is not set
1762 # CONFIG_DW_WATCHDOG is not set 2056 # CONFIG_DW_WATCHDOG is not set
1763 # CONFIG_MPCORE_WATCHDOG is not set 2057 # CONFIG_MPCORE_WATCHDOG is not set
1764 # CONFIG_MAX63XX_WATCHDOG is not set 2058 # CONFIG_MAX63XX_WATCHDOG is not set
1765 CONFIG_IMX2_WDT=y 2059 CONFIG_IMX2_WDT=y
2060 # CONFIG_ALIM7101_WDT is not set
2061 # CONFIG_I6300ESB_WDT is not set
1766 2062
1767 # 2063 #
2064 # PCI-based Watchdog Cards
2065 #
2066 # CONFIG_PCIPCWATCHDOG is not set
2067 # CONFIG_WDTPCI is not set
2068
2069 #
1768 # USB-based Watchdog Cards 2070 # USB-based Watchdog Cards
1769 # 2071 #
1770 # CONFIG_USBPCWATCHDOG is not set 2072 # CONFIG_USBPCWATCHDOG is not set
1771 CONFIG_SSB_POSSIBLE=y 2073 CONFIG_SSB_POSSIBLE=y
1772 2074
1773 # 2075 #
1774 # Sonics Silicon Backplane 2076 # Sonics Silicon Backplane
1775 # 2077 #
1776 # CONFIG_SSB is not set 2078 # CONFIG_SSB is not set
1777 CONFIG_BCMA_POSSIBLE=y 2079 CONFIG_BCMA_POSSIBLE=y
1778 2080
1779 # 2081 #
1780 # Broadcom specific AMBA 2082 # Broadcom specific AMBA
1781 # 2083 #
1782 # CONFIG_BCMA is not set 2084 # CONFIG_BCMA is not set
1783 2085
1784 # 2086 #
1785 # Multifunction device drivers 2087 # Multifunction device drivers
1786 # 2088 #
1787 CONFIG_MFD_CORE=y 2089 CONFIG_MFD_CORE=y
1788 # CONFIG_MFD_AS3711 is not set 2090 # CONFIG_MFD_AS3711 is not set
1789 # CONFIG_PMIC_ADP5520 is not set 2091 # CONFIG_PMIC_ADP5520 is not set
1790 # CONFIG_MFD_AAT2870_CORE is not set 2092 # CONFIG_MFD_AAT2870_CORE is not set
1791 # CONFIG_MFD_CROS_EC is not set 2093 # CONFIG_MFD_CROS_EC is not set
1792 # CONFIG_MFD_ASIC3 is not set 2094 # CONFIG_MFD_ASIC3 is not set
1793 # CONFIG_PMIC_DA903X is not set 2095 # CONFIG_PMIC_DA903X is not set
1794 CONFIG_PMIC_DA9052=y 2096 CONFIG_PMIC_DA9052=y
1795 # CONFIG_MFD_DA9052_SPI is not set 2097 # CONFIG_MFD_DA9052_SPI is not set
1796 CONFIG_MFD_DA9052_I2C=y 2098 CONFIG_MFD_DA9052_I2C=y
1797 # CONFIG_MFD_DA9055 is not set 2099 # CONFIG_MFD_DA9055 is not set
1798 CONFIG_MFD_MXC_HDMI=y 2100 CONFIG_MFD_MXC_HDMI=y
1799 CONFIG_MFD_MC13783=y 2101 CONFIG_MFD_MC13783=y
1800 CONFIG_MFD_MC13XXX=y 2102 CONFIG_MFD_MC13XXX=y
1801 CONFIG_MFD_MC13XXX_SPI=y 2103 CONFIG_MFD_MC13XXX_SPI=y
1802 CONFIG_MFD_MC13XXX_I2C=y 2104 CONFIG_MFD_MC13XXX_I2C=y
1803 # CONFIG_HTC_EGPIO is not set 2105 # CONFIG_HTC_EGPIO is not set
1804 # CONFIG_HTC_PASIC3 is not set 2106 # CONFIG_HTC_PASIC3 is not set
1805 # CONFIG_HTC_I2CPLD is not set 2107 # CONFIG_HTC_I2CPLD is not set
2108 # CONFIG_LPC_ICH is not set
2109 # CONFIG_LPC_SCH is not set
2110 # CONFIG_MFD_JANZ_CMODIO is not set
1806 # CONFIG_MFD_88PM800 is not set 2111 # CONFIG_MFD_88PM800 is not set
1807 # CONFIG_MFD_88PM805 is not set 2112 # CONFIG_MFD_88PM805 is not set
1808 # CONFIG_MFD_88PM860X is not set 2113 # CONFIG_MFD_88PM860X is not set
1809 CONFIG_MFD_MAX17135=y 2114 CONFIG_MFD_MAX17135=y
1810 # CONFIG_MFD_MAX77686 is not set 2115 # CONFIG_MFD_MAX77686 is not set
1811 # CONFIG_MFD_MAX77693 is not set 2116 # CONFIG_MFD_MAX77693 is not set
1812 # CONFIG_MFD_MAX8907 is not set 2117 # CONFIG_MFD_MAX8907 is not set
1813 # CONFIG_MFD_MAX8925 is not set 2118 # CONFIG_MFD_MAX8925 is not set
1814 # CONFIG_MFD_MAX8997 is not set 2119 # CONFIG_MFD_MAX8997 is not set
1815 # CONFIG_MFD_MAX8998 is not set 2120 # CONFIG_MFD_MAX8998 is not set
1816 # CONFIG_EZX_PCAP is not set 2121 # CONFIG_EZX_PCAP is not set
1817 # CONFIG_MFD_VIPERBOARD is not set 2122 # CONFIG_MFD_VIPERBOARD is not set
1818 # CONFIG_MFD_RETU is not set 2123 # CONFIG_MFD_RETU is not set
1819 # CONFIG_MFD_PCF50633 is not set 2124 # CONFIG_MFD_PCF50633 is not set
2125 # CONFIG_MFD_RDC321X is not set
2126 # CONFIG_MFD_RTSX_PCI is not set
1820 # CONFIG_MFD_RC5T583 is not set 2127 # CONFIG_MFD_RC5T583 is not set
1821 # CONFIG_MFD_SEC_CORE is not set 2128 # CONFIG_MFD_SEC_CORE is not set
1822 CONFIG_MFD_SI476X_CORE=y 2129 CONFIG_MFD_SI476X_CORE=y
1823 # CONFIG_MFD_SM501 is not set 2130 # CONFIG_MFD_SM501 is not set
1824 # CONFIG_MFD_SMSC is not set 2131 # CONFIG_MFD_SMSC is not set
1825 # CONFIG_ABX500_CORE is not set 2132 # CONFIG_ABX500_CORE is not set
1826 # CONFIG_MFD_STMPE is not set 2133 # CONFIG_MFD_STMPE is not set
1827 CONFIG_MFD_SYSCON=y 2134 CONFIG_MFD_SYSCON=y
1828 # CONFIG_MFD_TI_AM335X_TSCADC is not set 2135 # CONFIG_MFD_TI_AM335X_TSCADC is not set
1829 # CONFIG_MFD_LP8788 is not set 2136 # CONFIG_MFD_LP8788 is not set
1830 # CONFIG_MFD_PALMAS is not set 2137 # CONFIG_MFD_PALMAS is not set
1831 # CONFIG_TPS6105X is not set 2138 # CONFIG_TPS6105X is not set
1832 # CONFIG_TPS65010 is not set 2139 # CONFIG_TPS65010 is not set
1833 # CONFIG_TPS6507X is not set 2140 # CONFIG_TPS6507X is not set
1834 # CONFIG_MFD_TPS65090 is not set 2141 # CONFIG_MFD_TPS65090 is not set
1835 # CONFIG_MFD_TPS65217 is not set 2142 # CONFIG_MFD_TPS65217 is not set
1836 # CONFIG_MFD_TPS6586X is not set 2143 # CONFIG_MFD_TPS6586X is not set
1837 # CONFIG_MFD_TPS65910 is not set 2144 # CONFIG_MFD_TPS65910 is not set
1838 # CONFIG_MFD_TPS65912 is not set 2145 # CONFIG_MFD_TPS65912 is not set
1839 # CONFIG_MFD_TPS65912_I2C is not set 2146 # CONFIG_MFD_TPS65912_I2C is not set
1840 # CONFIG_MFD_TPS65912_SPI is not set 2147 # CONFIG_MFD_TPS65912_SPI is not set
1841 # CONFIG_MFD_TPS80031 is not set 2148 # CONFIG_MFD_TPS80031 is not set
1842 # CONFIG_TWL4030_CORE is not set 2149 # CONFIG_TWL4030_CORE is not set
1843 # CONFIG_TWL6040_CORE is not set 2150 # CONFIG_TWL6040_CORE is not set
1844 # CONFIG_MFD_WL1273_CORE is not set 2151 # CONFIG_MFD_WL1273_CORE is not set
1845 # CONFIG_MFD_LM3533 is not set 2152 # CONFIG_MFD_LM3533 is not set
2153 # CONFIG_MFD_TIMBERDALE is not set
1846 # CONFIG_MFD_TC3589X is not set 2154 # CONFIG_MFD_TC3589X is not set
1847 # CONFIG_MFD_TMIO is not set 2155 # CONFIG_MFD_TMIO is not set
1848 # CONFIG_MFD_T7L66XB is not set 2156 # CONFIG_MFD_T7L66XB is not set
1849 # CONFIG_MFD_TC6387XB is not set 2157 # CONFIG_MFD_TC6387XB is not set
1850 # CONFIG_MFD_TC6393XB is not set 2158 # CONFIG_MFD_TC6393XB is not set
2159 # CONFIG_MFD_VX855 is not set
1851 # CONFIG_MFD_ARIZONA_I2C is not set 2160 # CONFIG_MFD_ARIZONA_I2C is not set
1852 # CONFIG_MFD_ARIZONA_SPI is not set 2161 # CONFIG_MFD_ARIZONA_SPI is not set
1853 # CONFIG_MFD_WM8400 is not set 2162 # CONFIG_MFD_WM8400 is not set
1854 # CONFIG_MFD_WM831X_I2C is not set 2163 # CONFIG_MFD_WM831X_I2C is not set
1855 # CONFIG_MFD_WM831X_SPI is not set 2164 # CONFIG_MFD_WM831X_SPI is not set
1856 # CONFIG_MFD_WM8350_I2C is not set 2165 # CONFIG_MFD_WM8350_I2C is not set
1857 # CONFIG_MFD_WM8994 is not set 2166 # CONFIG_MFD_WM8994 is not set
1858 CONFIG_REGULATOR=y 2167 CONFIG_REGULATOR=y
1859 # CONFIG_REGULATOR_DEBUG is not set 2168 # CONFIG_REGULATOR_DEBUG is not set
1860 # CONFIG_REGULATOR_DUMMY is not set 2169 # CONFIG_REGULATOR_DUMMY is not set
1861 CONFIG_REGULATOR_FIXED_VOLTAGE=y 2170 CONFIG_REGULATOR_FIXED_VOLTAGE=y
1862 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set 2171 # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
1863 # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set 2172 # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
1864 # CONFIG_REGULATOR_GPIO is not set 2173 # CONFIG_REGULATOR_GPIO is not set
1865 # CONFIG_REGULATOR_AD5398 is not set 2174 # CONFIG_REGULATOR_AD5398 is not set
1866 CONFIG_REGULATOR_DA9052=y 2175 CONFIG_REGULATOR_DA9052=y
1867 # CONFIG_REGULATOR_FAN53555 is not set 2176 # CONFIG_REGULATOR_FAN53555 is not set
1868 CONFIG_REGULATOR_ANATOP=y 2177 CONFIG_REGULATOR_ANATOP=y
1869 CONFIG_REGULATOR_MC13XXX_CORE=y 2178 CONFIG_REGULATOR_MC13XXX_CORE=y
1870 CONFIG_REGULATOR_MC13783=y 2179 CONFIG_REGULATOR_MC13783=y
1871 CONFIG_REGULATOR_MC13892=y 2180 CONFIG_REGULATOR_MC13892=y
1872 # CONFIG_REGULATOR_ISL6271A is not set 2181 # CONFIG_REGULATOR_ISL6271A is not set
1873 # CONFIG_REGULATOR_MAX1586 is not set 2182 # CONFIG_REGULATOR_MAX1586 is not set
1874 CONFIG_REGULATOR_MAX17135=y 2183 CONFIG_REGULATOR_MAX17135=y
1875 # CONFIG_REGULATOR_MAX8649 is not set 2184 # CONFIG_REGULATOR_MAX8649 is not set
1876 # CONFIG_REGULATOR_MAX8660 is not set 2185 # CONFIG_REGULATOR_MAX8660 is not set
1877 # CONFIG_REGULATOR_MAX8952 is not set 2186 # CONFIG_REGULATOR_MAX8952 is not set
1878 # CONFIG_REGULATOR_MAX8973 is not set 2187 # CONFIG_REGULATOR_MAX8973 is not set
1879 # CONFIG_REGULATOR_LP3971 is not set 2188 # CONFIG_REGULATOR_LP3971 is not set
1880 # CONFIG_REGULATOR_LP3972 is not set 2189 # CONFIG_REGULATOR_LP3972 is not set
1881 # CONFIG_REGULATOR_LP872X is not set 2190 # CONFIG_REGULATOR_LP872X is not set
1882 # CONFIG_REGULATOR_LP8755 is not set 2191 # CONFIG_REGULATOR_LP8755 is not set
1883 CONFIG_REGULATOR_PFUZE100=y 2192 CONFIG_REGULATOR_PFUZE100=y
1884 # CONFIG_REGULATOR_TPS51632 is not set 2193 # CONFIG_REGULATOR_TPS51632 is not set
1885 # CONFIG_REGULATOR_TPS62360 is not set 2194 # CONFIG_REGULATOR_TPS62360 is not set
1886 # CONFIG_REGULATOR_TPS65023 is not set 2195 # CONFIG_REGULATOR_TPS65023 is not set
1887 # CONFIG_REGULATOR_TPS6507X is not set 2196 # CONFIG_REGULATOR_TPS6507X is not set
1888 # CONFIG_REGULATOR_TPS6524X is not set 2197 # CONFIG_REGULATOR_TPS6524X is not set
1889 CONFIG_MEDIA_SUPPORT=y 2198 CONFIG_MEDIA_SUPPORT=y
1890 2199
1891 # 2200 #
1892 # Multimedia core support 2201 # Multimedia core support
1893 # 2202 #
1894 CONFIG_MEDIA_CAMERA_SUPPORT=y 2203 CONFIG_MEDIA_CAMERA_SUPPORT=y
1895 # CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set 2204 # CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
1896 # CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set 2205 # CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
1897 CONFIG_MEDIA_RADIO_SUPPORT=y 2206 CONFIG_MEDIA_RADIO_SUPPORT=y
1898 # CONFIG_MEDIA_RC_SUPPORT is not set 2207 # CONFIG_MEDIA_RC_SUPPORT is not set
1899 # CONFIG_MEDIA_CONTROLLER is not set 2208 # CONFIG_MEDIA_CONTROLLER is not set
1900 CONFIG_VIDEO_DEV=y 2209 CONFIG_VIDEO_DEV=y
1901 CONFIG_VIDEO_V4L2=y 2210 CONFIG_VIDEO_V4L2=y
1902 # CONFIG_VIDEO_ADV_DEBUG is not set 2211 # CONFIG_VIDEO_ADV_DEBUG is not set
1903 # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set 2212 # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
1904 CONFIG_VIDEOBUF_GEN=y 2213 CONFIG_VIDEOBUF_GEN=y
1905 CONFIG_VIDEOBUF_DMA_CONTIG=y 2214 CONFIG_VIDEOBUF_DMA_CONTIG=y
1906 CONFIG_VIDEOBUF2_CORE=y 2215 CONFIG_VIDEOBUF2_CORE=y
1907 CONFIG_VIDEOBUF2_MEMOPS=y 2216 CONFIG_VIDEOBUF2_MEMOPS=y
1908 CONFIG_VIDEOBUF2_DMA_CONTIG=y 2217 CONFIG_VIDEOBUF2_DMA_CONTIG=y
1909 CONFIG_VIDEOBUF2_VMALLOC=m 2218 CONFIG_VIDEOBUF2_VMALLOC=m
1910 CONFIG_VIDEO_V4L2_INT_DEVICE=y 2219 CONFIG_VIDEO_V4L2_INT_DEVICE=y
1911 # CONFIG_TTPCI_EEPROM is not set 2220 # CONFIG_TTPCI_EEPROM is not set
1912 2221
1913 # 2222 #
1914 # Media drivers 2223 # Media drivers
1915 # 2224 #
1916 CONFIG_MEDIA_USB_SUPPORT=y 2225 CONFIG_MEDIA_USB_SUPPORT=y
1917 2226
1918 # 2227 #
1919 # Webcam devices 2228 # Webcam devices
1920 # 2229 #
1921 CONFIG_USB_VIDEO_CLASS=m 2230 CONFIG_USB_VIDEO_CLASS=m
1922 CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y 2231 CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
1923 CONFIG_USB_GSPCA=m 2232 CONFIG_USB_GSPCA=m
1924 # CONFIG_USB_M5602 is not set 2233 # CONFIG_USB_M5602 is not set
1925 # CONFIG_USB_STV06XX is not set 2234 # CONFIG_USB_STV06XX is not set
1926 # CONFIG_USB_GL860 is not set 2235 # CONFIG_USB_GL860 is not set
1927 # CONFIG_USB_GSPCA_BENQ is not set 2236 # CONFIG_USB_GSPCA_BENQ is not set
1928 # CONFIG_USB_GSPCA_CONEX is not set 2237 # CONFIG_USB_GSPCA_CONEX is not set
1929 # CONFIG_USB_GSPCA_CPIA1 is not set 2238 # CONFIG_USB_GSPCA_CPIA1 is not set
1930 # CONFIG_USB_GSPCA_ETOMS is not set 2239 # CONFIG_USB_GSPCA_ETOMS is not set
1931 # CONFIG_USB_GSPCA_FINEPIX is not set 2240 # CONFIG_USB_GSPCA_FINEPIX is not set
1932 # CONFIG_USB_GSPCA_JEILINJ is not set 2241 # CONFIG_USB_GSPCA_JEILINJ is not set
1933 # CONFIG_USB_GSPCA_JL2005BCD is not set 2242 # CONFIG_USB_GSPCA_JL2005BCD is not set
1934 # CONFIG_USB_GSPCA_KINECT is not set 2243 # CONFIG_USB_GSPCA_KINECT is not set
1935 # CONFIG_USB_GSPCA_KONICA is not set 2244 # CONFIG_USB_GSPCA_KONICA is not set
1936 # CONFIG_USB_GSPCA_MARS is not set 2245 # CONFIG_USB_GSPCA_MARS is not set
1937 # CONFIG_USB_GSPCA_MR97310A is not set 2246 # CONFIG_USB_GSPCA_MR97310A is not set
1938 # CONFIG_USB_GSPCA_NW80X is not set 2247 # CONFIG_USB_GSPCA_NW80X is not set
1939 # CONFIG_USB_GSPCA_OV519 is not set 2248 # CONFIG_USB_GSPCA_OV519 is not set
1940 # CONFIG_USB_GSPCA_OV534 is not set 2249 # CONFIG_USB_GSPCA_OV534 is not set
1941 # CONFIG_USB_GSPCA_OV534_9 is not set 2250 # CONFIG_USB_GSPCA_OV534_9 is not set
1942 # CONFIG_USB_GSPCA_PAC207 is not set 2251 # CONFIG_USB_GSPCA_PAC207 is not set
1943 # CONFIG_USB_GSPCA_PAC7302 is not set 2252 # CONFIG_USB_GSPCA_PAC7302 is not set
1944 # CONFIG_USB_GSPCA_PAC7311 is not set 2253 # CONFIG_USB_GSPCA_PAC7311 is not set
1945 # CONFIG_USB_GSPCA_SE401 is not set 2254 # CONFIG_USB_GSPCA_SE401 is not set
1946 # CONFIG_USB_GSPCA_SN9C2028 is not set 2255 # CONFIG_USB_GSPCA_SN9C2028 is not set
1947 # CONFIG_USB_GSPCA_SN9C20X is not set 2256 # CONFIG_USB_GSPCA_SN9C20X is not set
1948 # CONFIG_USB_GSPCA_SONIXB is not set 2257 # CONFIG_USB_GSPCA_SONIXB is not set
1949 # CONFIG_USB_GSPCA_SONIXJ is not set 2258 # CONFIG_USB_GSPCA_SONIXJ is not set
1950 # CONFIG_USB_GSPCA_SPCA500 is not set 2259 # CONFIG_USB_GSPCA_SPCA500 is not set
1951 # CONFIG_USB_GSPCA_SPCA501 is not set 2260 # CONFIG_USB_GSPCA_SPCA501 is not set
1952 # CONFIG_USB_GSPCA_SPCA505 is not set 2261 # CONFIG_USB_GSPCA_SPCA505 is not set
1953 # CONFIG_USB_GSPCA_SPCA506 is not set 2262 # CONFIG_USB_GSPCA_SPCA506 is not set
1954 # CONFIG_USB_GSPCA_SPCA508 is not set 2263 # CONFIG_USB_GSPCA_SPCA508 is not set
1955 # CONFIG_USB_GSPCA_SPCA561 is not set 2264 # CONFIG_USB_GSPCA_SPCA561 is not set
1956 # CONFIG_USB_GSPCA_SPCA1528 is not set 2265 # CONFIG_USB_GSPCA_SPCA1528 is not set
1957 # CONFIG_USB_GSPCA_SQ905 is not set 2266 # CONFIG_USB_GSPCA_SQ905 is not set
1958 # CONFIG_USB_GSPCA_SQ905C is not set 2267 # CONFIG_USB_GSPCA_SQ905C is not set
1959 # CONFIG_USB_GSPCA_SQ930X is not set 2268 # CONFIG_USB_GSPCA_SQ930X is not set
1960 # CONFIG_USB_GSPCA_STK014 is not set 2269 # CONFIG_USB_GSPCA_STK014 is not set
1961 # CONFIG_USB_GSPCA_STV0680 is not set 2270 # CONFIG_USB_GSPCA_STV0680 is not set
1962 # CONFIG_USB_GSPCA_SUNPLUS is not set 2271 # CONFIG_USB_GSPCA_SUNPLUS is not set
1963 # CONFIG_USB_GSPCA_T613 is not set 2272 # CONFIG_USB_GSPCA_T613 is not set
1964 # CONFIG_USB_GSPCA_TOPRO is not set 2273 # CONFIG_USB_GSPCA_TOPRO is not set
1965 # CONFIG_USB_GSPCA_TV8532 is not set 2274 # CONFIG_USB_GSPCA_TV8532 is not set
1966 # CONFIG_USB_GSPCA_VC032X is not set 2275 # CONFIG_USB_GSPCA_VC032X is not set
1967 # CONFIG_USB_GSPCA_VICAM is not set 2276 # CONFIG_USB_GSPCA_VICAM is not set
1968 # CONFIG_USB_GSPCA_XIRLINK_CIT is not set 2277 # CONFIG_USB_GSPCA_XIRLINK_CIT is not set
1969 # CONFIG_USB_GSPCA_ZC3XX is not set 2278 # CONFIG_USB_GSPCA_ZC3XX is not set
1970 # CONFIG_USB_PWC is not set 2279 # CONFIG_USB_PWC is not set
1971 # CONFIG_VIDEO_CPIA2 is not set 2280 # CONFIG_VIDEO_CPIA2 is not set
1972 # CONFIG_USB_ZR364XX is not set 2281 # CONFIG_USB_ZR364XX is not set
1973 # CONFIG_USB_STKWEBCAM is not set 2282 # CONFIG_USB_STKWEBCAM is not set
1974 # CONFIG_USB_S2255 is not set 2283 # CONFIG_USB_S2255 is not set
1975 # CONFIG_USB_SN9C102 is not set 2284 # CONFIG_USB_SN9C102 is not set
1976 2285
1977 # 2286 #
1978 # Webcam, TV (analog/digital) USB devices 2287 # Webcam, TV (analog/digital) USB devices
1979 # 2288 #
1980 # CONFIG_VIDEO_EM28XX is not set 2289 # CONFIG_VIDEO_EM28XX is not set
2290 # CONFIG_MEDIA_PCI_SUPPORT is not set
1981 CONFIG_V4L_PLATFORM_DRIVERS=y 2291 CONFIG_V4L_PLATFORM_DRIVERS=y
2292 # CONFIG_VIDEO_CAFE_CCIC is not set
1982 # CONFIG_VIDEO_TIMBERDALE is not set 2293 # CONFIG_VIDEO_TIMBERDALE is not set
1983 CONFIG_VIDEO_MXC_OUTPUT=y 2294 CONFIG_VIDEO_MXC_OUTPUT=y
1984 CONFIG_VIDEO_MXC_CAPTURE=m 2295 CONFIG_VIDEO_MXC_CAPTURE=m
1985 2296
1986 # 2297 #
1987 # MXC Camera/V4L2 PRP Features support 2298 # MXC Camera/V4L2 PRP Features support
1988 # 2299 #
1989 CONFIG_VIDEO_MXC_IPU_CAMERA=y 2300 CONFIG_VIDEO_MXC_IPU_CAMERA=y
1990 CONFIG_VIDEO_MXC_CSI_CAMERA=m 2301 CONFIG_VIDEO_MXC_CSI_CAMERA=m
1991 CONFIG_MXC_CAMERA_OV5640=m 2302 CONFIG_MXC_CAMERA_OV5640=m
1992 CONFIG_MXC_CAMERA_OV5642=m 2303 CONFIG_MXC_CAMERA_OV5642=m
1993 CONFIG_MXC_CAMERA_OV5640_MIPI=m 2304 CONFIG_MXC_CAMERA_OV5640_MIPI=m
1994 CONFIG_MXC_TVIN_ADV7180=m 2305 CONFIG_MXC_TVIN_ADV7180=m
1995 CONFIG_MXC_VADC=m 2306 CONFIG_MXC_VADC=m
1996 CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m 2307 CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
1997 CONFIG_MXC_IPU_PRP_ENC=m 2308 CONFIG_MXC_IPU_PRP_ENC=m
1998 CONFIG_MXC_IPU_CSI_ENC=m 2309 CONFIG_MXC_IPU_CSI_ENC=m
1999 CONFIG_VIDEO_MXC_IPU_OUTPUT=y 2310 CONFIG_VIDEO_MXC_IPU_OUTPUT=y
2000 CONFIG_VIDEO_MXC_PXP_V4L2=y 2311 CONFIG_VIDEO_MXC_PXP_V4L2=y
2001 CONFIG_SOC_CAMERA=y 2312 CONFIG_SOC_CAMERA=y
2002 # CONFIG_SOC_CAMERA_PLATFORM is not set 2313 # CONFIG_SOC_CAMERA_PLATFORM is not set
2003 CONFIG_MX3_VIDEO=y 2314 CONFIG_MX3_VIDEO=y
2004 CONFIG_VIDEO_MX3=y 2315 CONFIG_VIDEO_MX3=y
2005 # CONFIG_VIDEO_SH_MOBILE_CSI2 is not set 2316 # CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
2006 # CONFIG_VIDEO_SH_MOBILE_CEU is not set 2317 # CONFIG_VIDEO_SH_MOBILE_CEU is not set
2007 # CONFIG_V4L_MEM2MEM_DRIVERS is not set 2318 # CONFIG_V4L_MEM2MEM_DRIVERS is not set
2008 # CONFIG_V4L_TEST_DRIVERS is not set 2319 # CONFIG_V4L_TEST_DRIVERS is not set
2009 2320
2010 # 2321 #
2011 # Supported MMC/SDIO adapters 2322 # Supported MMC/SDIO adapters
2012 # 2323 #
2013 CONFIG_RADIO_ADAPTERS=y 2324 CONFIG_RADIO_ADAPTERS=y
2014 # CONFIG_RADIO_SI470X is not set 2325 # CONFIG_RADIO_SI470X is not set
2015 CONFIG_RADIO_SI476X=y 2326 CONFIG_RADIO_SI476X=y
2016 # CONFIG_USB_MR800 is not set 2327 # CONFIG_USB_MR800 is not set
2017 # CONFIG_USB_DSBR is not set 2328 # CONFIG_USB_DSBR is not set
2329 # CONFIG_RADIO_MAXIRADIO is not set
2018 # CONFIG_RADIO_SHARK is not set 2330 # CONFIG_RADIO_SHARK is not set
2019 # CONFIG_RADIO_SHARK2 is not set 2331 # CONFIG_RADIO_SHARK2 is not set
2020 # CONFIG_I2C_SI4713 is not set 2332 # CONFIG_I2C_SI4713 is not set
2021 # CONFIG_RADIO_SI4713 is not set 2333 # CONFIG_RADIO_SI4713 is not set
2022 # CONFIG_USB_KEENE is not set 2334 # CONFIG_USB_KEENE is not set
2023 # CONFIG_USB_MA901 is not set 2335 # CONFIG_USB_MA901 is not set
2024 # CONFIG_RADIO_TEA5764 is not set 2336 # CONFIG_RADIO_TEA5764 is not set
2025 # CONFIG_RADIO_SAA7706H is not set 2337 # CONFIG_RADIO_SAA7706H is not set
2026 # CONFIG_RADIO_TEF6862 is not set 2338 # CONFIG_RADIO_TEF6862 is not set
2027 # CONFIG_RADIO_WL1273 is not set 2339 # CONFIG_RADIO_WL1273 is not set
2028 2340
2029 # 2341 #
2030 # Texas Instruments WL128x FM driver (ST based) 2342 # Texas Instruments WL128x FM driver (ST based)
2031 # 2343 #
2032 # CONFIG_CYPRESS_FIRMWARE is not set 2344 # CONFIG_CYPRESS_FIRMWARE is not set
2033 2345
2034 # 2346 #
2035 # Media ancillary drivers (tuners, sensors, i2c, frontends) 2347 # Media ancillary drivers (tuners, sensors, i2c, frontends)
2036 # 2348 #
2037 CONFIG_MEDIA_SUBDRV_AUTOSELECT=y 2349 CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
2038 CONFIG_MEDIA_ATTACH=y 2350 CONFIG_MEDIA_ATTACH=y
2039 2351
2040 # 2352 #
2041 # Audio decoders, processors and mixers 2353 # Audio decoders, processors and mixers
2042 # 2354 #
2043 2355
2044 # 2356 #
2045 # RDS decoders 2357 # RDS decoders
2046 # 2358 #
2047 2359
2048 # 2360 #
2049 # Video decoders 2361 # Video decoders
2050 # 2362 #
2051 2363
2052 # 2364 #
2053 # Video and audio decoders 2365 # Video and audio decoders
2054 # 2366 #
2055 2367
2056 # 2368 #
2057 # Video encoders 2369 # Video encoders
2058 # 2370 #
2059 2371
2060 # 2372 #
2061 # Camera sensor devices 2373 # Camera sensor devices
2062 # 2374 #
2063 2375
2064 # 2376 #
2065 # Flash devices 2377 # Flash devices
2066 # 2378 #
2067 2379
2068 # 2380 #
2069 # Video improvement chips 2381 # Video improvement chips
2070 # 2382 #
2071 2383
2072 # 2384 #
2073 # Miscelaneous helper chips 2385 # Miscelaneous helper chips
2074 # 2386 #
2075 2387
2076 # 2388 #
2077 # Sensors used on soc_camera driver 2389 # Sensors used on soc_camera driver
2078 # 2390 #
2079 2391
2080 # 2392 #
2081 # soc_camera sensor drivers 2393 # soc_camera sensor drivers
2082 # 2394 #
2083 # CONFIG_SOC_CAMERA_IMX074 is not set 2395 # CONFIG_SOC_CAMERA_IMX074 is not set
2084 # CONFIG_SOC_CAMERA_MT9M001 is not set 2396 # CONFIG_SOC_CAMERA_MT9M001 is not set
2085 # CONFIG_SOC_CAMERA_MT9M111 is not set 2397 # CONFIG_SOC_CAMERA_MT9M111 is not set
2086 # CONFIG_SOC_CAMERA_MT9T031 is not set 2398 # CONFIG_SOC_CAMERA_MT9T031 is not set
2087 # CONFIG_SOC_CAMERA_MT9T112 is not set 2399 # CONFIG_SOC_CAMERA_MT9T112 is not set
2088 # CONFIG_SOC_CAMERA_MT9V022 is not set 2400 # CONFIG_SOC_CAMERA_MT9V022 is not set
2089 CONFIG_SOC_CAMERA_OV2640=y 2401 CONFIG_SOC_CAMERA_OV2640=y
2090 # CONFIG_SOC_CAMERA_OV5642 is not set 2402 # CONFIG_SOC_CAMERA_OV5642 is not set
2091 # CONFIG_SOC_CAMERA_OV6650 is not set 2403 # CONFIG_SOC_CAMERA_OV6650 is not set
2092 # CONFIG_SOC_CAMERA_OV772X is not set 2404 # CONFIG_SOC_CAMERA_OV772X is not set
2093 # CONFIG_SOC_CAMERA_OV9640 is not set 2405 # CONFIG_SOC_CAMERA_OV9640 is not set
2094 # CONFIG_SOC_CAMERA_OV9740 is not set 2406 # CONFIG_SOC_CAMERA_OV9740 is not set
2095 # CONFIG_SOC_CAMERA_RJ54N1 is not set 2407 # CONFIG_SOC_CAMERA_RJ54N1 is not set
2096 # CONFIG_SOC_CAMERA_TW9910 is not set 2408 # CONFIG_SOC_CAMERA_TW9910 is not set
2097 CONFIG_MEDIA_TUNER=y 2409 CONFIG_MEDIA_TUNER=y
2098 CONFIG_MEDIA_TUNER_SIMPLE=y 2410 CONFIG_MEDIA_TUNER_SIMPLE=y
2099 CONFIG_MEDIA_TUNER_TDA8290=y 2411 CONFIG_MEDIA_TUNER_TDA8290=y
2100 CONFIG_MEDIA_TUNER_TDA827X=y 2412 CONFIG_MEDIA_TUNER_TDA827X=y
2101 CONFIG_MEDIA_TUNER_TDA18271=y 2413 CONFIG_MEDIA_TUNER_TDA18271=y
2102 CONFIG_MEDIA_TUNER_TDA9887=y 2414 CONFIG_MEDIA_TUNER_TDA9887=y
2103 CONFIG_MEDIA_TUNER_TEA5761=y 2415 CONFIG_MEDIA_TUNER_TEA5761=y
2104 CONFIG_MEDIA_TUNER_TEA5767=y 2416 CONFIG_MEDIA_TUNER_TEA5767=y
2105 CONFIG_MEDIA_TUNER_MT20XX=y 2417 CONFIG_MEDIA_TUNER_MT20XX=y
2106 CONFIG_MEDIA_TUNER_XC2028=y 2418 CONFIG_MEDIA_TUNER_XC2028=y
2107 CONFIG_MEDIA_TUNER_XC5000=y 2419 CONFIG_MEDIA_TUNER_XC5000=y
2108 CONFIG_MEDIA_TUNER_XC4000=y 2420 CONFIG_MEDIA_TUNER_XC4000=y
2109 CONFIG_MEDIA_TUNER_MC44S803=y 2421 CONFIG_MEDIA_TUNER_MC44S803=y
2110 2422
2111 # 2423 #
2112 # Tools to develop new frontends 2424 # Tools to develop new frontends
2113 # 2425 #
2114 # CONFIG_DVB_DUMMY_FE is not set 2426 # CONFIG_DVB_DUMMY_FE is not set
2115 2427
2116 # 2428 #
2117 # Graphics support 2429 # Graphics support
2118 # 2430 #
2431 CONFIG_VGA_ARB=y
2432 CONFIG_VGA_ARB_MAX_GPUS=16
2119 CONFIG_DRM=y 2433 CONFIG_DRM=y
2434 # CONFIG_DRM_TDFX is not set
2435 # CONFIG_DRM_R128 is not set
2436 # CONFIG_DRM_RADEON is not set
2437 # CONFIG_DRM_NOUVEAU is not set
2438 # CONFIG_DRM_MGA is not set
2439 # CONFIG_DRM_VIA is not set
2440 # CONFIG_DRM_SAVAGE is not set
2120 CONFIG_DRM_VIVANTE=y 2441 CONFIG_DRM_VIVANTE=y
2121 # CONFIG_DRM_EXYNOS is not set 2442 # CONFIG_DRM_EXYNOS is not set
2443 # CONFIG_DRM_VMWGFX is not set
2122 # CONFIG_DRM_UDL is not set 2444 # CONFIG_DRM_UDL is not set
2445 # CONFIG_DRM_AST is not set
2446 # CONFIG_DRM_MGAG200 is not set
2447 # CONFIG_DRM_CIRRUS_QEMU is not set
2123 # CONFIG_DRM_TILCDC is not set 2448 # CONFIG_DRM_TILCDC is not set
2449 # CONFIG_DRM_QXL is not set
2124 # CONFIG_TEGRA_HOST1X is not set 2450 # CONFIG_TEGRA_HOST1X is not set
2125 # CONFIG_VGASTATE is not set 2451 # CONFIG_VGASTATE is not set
2126 # CONFIG_VIDEO_OUTPUT_CONTROL is not set 2452 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
2127 CONFIG_VIDEOMODE_HELPERS=y 2453 CONFIG_VIDEOMODE_HELPERS=y
2128 CONFIG_HDMI=y 2454 CONFIG_HDMI=y
2129 CONFIG_FB=y 2455 CONFIG_FB=y
2130 # CONFIG_FIRMWARE_EDID is not set 2456 # CONFIG_FIRMWARE_EDID is not set
2131 # CONFIG_FB_DDC is not set 2457 # CONFIG_FB_DDC is not set
2132 # CONFIG_FB_BOOT_VESA_SUPPORT is not set 2458 # CONFIG_FB_BOOT_VESA_SUPPORT is not set
2133 CONFIG_FB_CFB_FILLRECT=y 2459 CONFIG_FB_CFB_FILLRECT=y
2134 CONFIG_FB_CFB_COPYAREA=y 2460 CONFIG_FB_CFB_COPYAREA=y
2135 CONFIG_FB_CFB_IMAGEBLIT=y 2461 CONFIG_FB_CFB_IMAGEBLIT=y
2136 # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set 2462 # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
2137 # CONFIG_FB_SYS_FILLRECT is not set 2463 # CONFIG_FB_SYS_FILLRECT is not set
2138 # CONFIG_FB_SYS_COPYAREA is not set 2464 # CONFIG_FB_SYS_COPYAREA is not set
2139 # CONFIG_FB_SYS_IMAGEBLIT is not set 2465 # CONFIG_FB_SYS_IMAGEBLIT is not set
2140 # CONFIG_FB_FOREIGN_ENDIAN is not set 2466 # CONFIG_FB_FOREIGN_ENDIAN is not set
2141 # CONFIG_FB_SYS_FOPS is not set 2467 # CONFIG_FB_SYS_FOPS is not set
2142 CONFIG_FB_DEFERRED_IO=y 2468 CONFIG_FB_DEFERRED_IO=y
2143 # CONFIG_FB_SVGALIB is not set 2469 # CONFIG_FB_SVGALIB is not set
2144 # CONFIG_FB_MACMODES is not set 2470 # CONFIG_FB_MACMODES is not set
2145 # CONFIG_FB_BACKLIGHT is not set 2471 # CONFIG_FB_BACKLIGHT is not set
2146 CONFIG_FB_MODE_HELPERS=y 2472 CONFIG_FB_MODE_HELPERS=y
2147 # CONFIG_FB_TILEBLITTING is not set 2473 # CONFIG_FB_TILEBLITTING is not set
2148 2474
2149 # 2475 #
2150 # Frame buffer hardware drivers 2476 # Frame buffer hardware drivers
2151 # 2477 #
2478 # CONFIG_FB_CIRRUS is not set
2479 # CONFIG_FB_PM2 is not set
2480 # CONFIG_FB_CYBER2000 is not set
2481 # CONFIG_FB_ASILIANT is not set
2482 # CONFIG_FB_IMSTT is not set
2152 # CONFIG_FB_UVESA is not set 2483 # CONFIG_FB_UVESA is not set
2153 # CONFIG_FB_S1D13XXX is not set 2484 # CONFIG_FB_S1D13XXX is not set
2485 # CONFIG_FB_NVIDIA is not set
2486 # CONFIG_FB_RIVA is not set
2487 # CONFIG_FB_I740 is not set
2488 # CONFIG_FB_MATROX is not set
2489 # CONFIG_FB_RADEON is not set
2490 # CONFIG_FB_ATY128 is not set
2491 # CONFIG_FB_ATY is not set
2492 # CONFIG_FB_S3 is not set
2493 # CONFIG_FB_SAVAGE is not set
2494 # CONFIG_FB_SIS is not set
2495 # CONFIG_FB_NEOMAGIC is not set
2496 # CONFIG_FB_KYRO is not set
2497 # CONFIG_FB_3DFX is not set
2498 # CONFIG_FB_VOODOO1 is not set
2499 # CONFIG_FB_VT8623 is not set
2500 # CONFIG_FB_TRIDENT is not set
2501 # CONFIG_FB_ARK is not set
2502 # CONFIG_FB_PM3 is not set
2503 # CONFIG_FB_CARMINE is not set
2154 # CONFIG_FB_TMIO is not set 2504 # CONFIG_FB_TMIO is not set
2155 # CONFIG_FB_SMSCUFX is not set 2505 # CONFIG_FB_SMSCUFX is not set
2156 # CONFIG_FB_UDL is not set 2506 # CONFIG_FB_UDL is not set
2157 # CONFIG_FB_GOLDFISH is not set 2507 # CONFIG_FB_GOLDFISH is not set
2158 # CONFIG_FB_VIRTUAL is not set 2508 # CONFIG_FB_VIRTUAL is not set
2159 # CONFIG_FB_METRONOME is not set 2509 # CONFIG_FB_METRONOME is not set
2510 # CONFIG_FB_MB862XX is not set
2160 CONFIG_FB_MX3=y 2511 CONFIG_FB_MX3=y
2161 # CONFIG_FB_BROADSHEET is not set 2512 # CONFIG_FB_BROADSHEET is not set
2162 # CONFIG_FB_AUO_K190X is not set 2513 # CONFIG_FB_AUO_K190X is not set
2163 CONFIG_FB_MXS=y 2514 CONFIG_FB_MXS=y
2164 # CONFIG_FB_SIMPLE is not set 2515 # CONFIG_FB_SIMPLE is not set
2165 # CONFIG_EXYNOS_VIDEO is not set 2516 # CONFIG_EXYNOS_VIDEO is not set
2166 CONFIG_BACKLIGHT_LCD_SUPPORT=y 2517 CONFIG_BACKLIGHT_LCD_SUPPORT=y
2167 CONFIG_LCD_CLASS_DEVICE=y 2518 CONFIG_LCD_CLASS_DEVICE=y
2168 CONFIG_LCD_L4F00242T03=y 2519 CONFIG_LCD_L4F00242T03=y
2169 # CONFIG_LCD_LMS283GF05 is not set 2520 # CONFIG_LCD_LMS283GF05 is not set
2170 # CONFIG_LCD_LTV350QV is not set 2521 # CONFIG_LCD_LTV350QV is not set
2171 # CONFIG_LCD_ILI922X is not set 2522 # CONFIG_LCD_ILI922X is not set
2172 # CONFIG_LCD_ILI9320 is not set 2523 # CONFIG_LCD_ILI9320 is not set
2173 # CONFIG_LCD_TDO24M is not set 2524 # CONFIG_LCD_TDO24M is not set
2174 # CONFIG_LCD_VGG2432A4 is not set 2525 # CONFIG_LCD_VGG2432A4 is not set
2175 CONFIG_LCD_PLATFORM=y 2526 CONFIG_LCD_PLATFORM=y
2176 # CONFIG_LCD_S6E63M0 is not set 2527 # CONFIG_LCD_S6E63M0 is not set
2177 # CONFIG_LCD_LD9040 is not set 2528 # CONFIG_LCD_LD9040 is not set
2178 # CONFIG_LCD_AMS369FG06 is not set 2529 # CONFIG_LCD_AMS369FG06 is not set
2179 # CONFIG_LCD_LMS501KF03 is not set 2530 # CONFIG_LCD_LMS501KF03 is not set
2180 # CONFIG_LCD_HX8357 is not set 2531 # CONFIG_LCD_HX8357 is not set
2181 CONFIG_BACKLIGHT_CLASS_DEVICE=y 2532 CONFIG_BACKLIGHT_CLASS_DEVICE=y
2182 CONFIG_BACKLIGHT_GENERIC=y 2533 CONFIG_BACKLIGHT_GENERIC=y
2183 CONFIG_BACKLIGHT_PWM=y 2534 CONFIG_BACKLIGHT_PWM=y
2184 # CONFIG_BACKLIGHT_DA9052 is not set 2535 # CONFIG_BACKLIGHT_DA9052 is not set
2185 # CONFIG_BACKLIGHT_ADP8860 is not set 2536 # CONFIG_BACKLIGHT_ADP8860 is not set
2186 # CONFIG_BACKLIGHT_ADP8870 is not set 2537 # CONFIG_BACKLIGHT_ADP8870 is not set
2187 # CONFIG_BACKLIGHT_LM3630 is not set 2538 # CONFIG_BACKLIGHT_LM3630 is not set
2188 # CONFIG_BACKLIGHT_LM3639 is not set 2539 # CONFIG_BACKLIGHT_LM3639 is not set
2189 # CONFIG_BACKLIGHT_LP855X is not set 2540 # CONFIG_BACKLIGHT_LP855X is not set
2190 CONFIG_FB_MXC=y 2541 CONFIG_FB_MXC=y
2191 CONFIG_FB_MXC_SYNC_PANEL=y 2542 CONFIG_FB_MXC_SYNC_PANEL=y
2192 CONFIG_FB_MXC_LDB=y 2543 CONFIG_FB_MXC_LDB=y
2193 CONFIG_FB_MXC_MIPI_DSI=y 2544 CONFIG_FB_MXC_MIPI_DSI=y
2194 CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y 2545 CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
2195 CONFIG_FB_MXC_HDMI=y 2546 CONFIG_FB_MXC_HDMI=y
2196 CONFIG_FB_MXC_EDID=y 2547 CONFIG_FB_MXC_EDID=y
2197 CONFIG_FB_MXC_EINK_PANEL=y 2548 CONFIG_FB_MXC_EINK_PANEL=y
2198 # CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set 2549 # CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set
2199 CONFIG_FB_MXS_SII902X=y 2550 CONFIG_FB_MXS_SII902X=y
2200 CONFIG_FB_MXC_DCIC=m 2551 CONFIG_FB_MXC_DCIC=m
2201 CONFIG_HANNSTAR_CABC=y 2552 CONFIG_HANNSTAR_CABC=y
2202 2553
2203 # 2554 #
2204 # Console display driver support 2555 # Console display driver support
2205 # 2556 #
2206 CONFIG_DUMMY_CONSOLE=y 2557 CONFIG_DUMMY_CONSOLE=y
2207 CONFIG_FRAMEBUFFER_CONSOLE=y 2558 CONFIG_FRAMEBUFFER_CONSOLE=y
2208 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y 2559 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
2209 # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set 2560 # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
2210 CONFIG_FONTS=y 2561 CONFIG_FONTS=y
2211 CONFIG_FONT_8x8=y 2562 CONFIG_FONT_8x8=y
2212 CONFIG_FONT_8x16=y 2563 CONFIG_FONT_8x16=y
2213 # CONFIG_FONT_6x11 is not set 2564 # CONFIG_FONT_6x11 is not set
2214 # CONFIG_FONT_7x14 is not set 2565 # CONFIG_FONT_7x14 is not set
2215 # CONFIG_FONT_PEARL_8x8 is not set 2566 # CONFIG_FONT_PEARL_8x8 is not set
2216 # CONFIG_FONT_ACORN_8x8 is not set 2567 # CONFIG_FONT_ACORN_8x8 is not set
2217 # CONFIG_FONT_MINI_4x6 is not set 2568 # CONFIG_FONT_MINI_4x6 is not set
2218 # CONFIG_FONT_SUN8x16 is not set 2569 # CONFIG_FONT_SUN8x16 is not set
2219 # CONFIG_FONT_SUN12x22 is not set 2570 # CONFIG_FONT_SUN12x22 is not set
2220 # CONFIG_FONT_10x18 is not set 2571 # CONFIG_FONT_10x18 is not set
2221 CONFIG_LOGO=y 2572 CONFIG_LOGO=y
2222 CONFIG_LOGO_LINUX_MONO=y 2573 CONFIG_LOGO_LINUX_MONO=y
2223 CONFIG_LOGO_LINUX_VGA16=y 2574 CONFIG_LOGO_LINUX_VGA16=y
2224 CONFIG_LOGO_LINUX_CLUT224=y 2575 CONFIG_LOGO_LINUX_CLUT224=y
2225 # CONFIG_FB_SSD1307 is not set 2576 # CONFIG_FB_SSD1307 is not set
2226 CONFIG_SOUND=y 2577 CONFIG_SOUND=y
2227 # CONFIG_SOUND_OSS_CORE is not set 2578 # CONFIG_SOUND_OSS_CORE is not set
2228 CONFIG_SND=y 2579 CONFIG_SND=y
2229 CONFIG_SND_TIMER=y 2580 CONFIG_SND_TIMER=y
2230 CONFIG_SND_PCM=y 2581 CONFIG_SND_PCM=y
2231 CONFIG_SND_COMPRESS_OFFLOAD=y 2582 CONFIG_SND_COMPRESS_OFFLOAD=y
2232 CONFIG_SND_JACK=y 2583 CONFIG_SND_JACK=y
2233 # CONFIG_SND_SEQUENCER is not set 2584 # CONFIG_SND_SEQUENCER is not set
2234 # CONFIG_SND_MIXER_OSS is not set 2585 # CONFIG_SND_MIXER_OSS is not set
2235 # CONFIG_SND_PCM_OSS is not set 2586 # CONFIG_SND_PCM_OSS is not set
2236 # CONFIG_SND_HRTIMER is not set 2587 # CONFIG_SND_HRTIMER is not set
2237 # CONFIG_SND_DYNAMIC_MINORS is not set 2588 # CONFIG_SND_DYNAMIC_MINORS is not set
2238 CONFIG_SND_SUPPORT_OLD_API=y 2589 CONFIG_SND_SUPPORT_OLD_API=y
2239 CONFIG_SND_VERBOSE_PROCFS=y 2590 CONFIG_SND_VERBOSE_PROCFS=y
2240 # CONFIG_SND_VERBOSE_PRINTK is not set 2591 # CONFIG_SND_VERBOSE_PRINTK is not set
2241 # CONFIG_SND_DEBUG is not set 2592 # CONFIG_SND_DEBUG is not set
2242 CONFIG_SND_KCTL_JACK=y 2593 CONFIG_SND_KCTL_JACK=y
2243 # CONFIG_SND_RAWMIDI_SEQ is not set 2594 # CONFIG_SND_RAWMIDI_SEQ is not set
2244 # CONFIG_SND_OPL3_LIB_SEQ is not set 2595 # CONFIG_SND_OPL3_LIB_SEQ is not set
2245 # CONFIG_SND_OPL4_LIB_SEQ is not set 2596 # CONFIG_SND_OPL4_LIB_SEQ is not set
2246 # CONFIG_SND_SBAWE_SEQ is not set 2597 # CONFIG_SND_SBAWE_SEQ is not set
2247 # CONFIG_SND_EMU10K1_SEQ is not set 2598 # CONFIG_SND_EMU10K1_SEQ is not set
2248 CONFIG_SND_DRIVERS=y 2599 CONFIG_SND_DRIVERS=y
2249 # CONFIG_SND_DUMMY is not set 2600 # CONFIG_SND_DUMMY is not set
2250 # CONFIG_SND_ALOOP is not set 2601 # CONFIG_SND_ALOOP is not set
2251 # CONFIG_SND_MTPAV is not set 2602 # CONFIG_SND_MTPAV is not set
2252 # CONFIG_SND_SERIAL_U16550 is not set 2603 # CONFIG_SND_SERIAL_U16550 is not set
2253 # CONFIG_SND_MPU401 is not set 2604 # CONFIG_SND_MPU401 is not set
2605 CONFIG_SND_PCI=y
2606 # CONFIG_SND_AD1889 is not set
2607 # CONFIG_SND_ALS300 is not set
2608 # CONFIG_SND_ALI5451 is not set
2609 # CONFIG_SND_ATIIXP is not set
2610 # CONFIG_SND_ATIIXP_MODEM is not set
2611 # CONFIG_SND_AU8810 is not set
2612 # CONFIG_SND_AU8820 is not set
2613 # CONFIG_SND_AU8830 is not set
2614 # CONFIG_SND_AW2 is not set
2615 # CONFIG_SND_AZT3328 is not set
2616 # CONFIG_SND_BT87X is not set
2617 # CONFIG_SND_CA0106 is not set
2618 # CONFIG_SND_CMIPCI is not set
2619 # CONFIG_SND_OXYGEN is not set
2620 # CONFIG_SND_CS4281 is not set
2621 # CONFIG_SND_CS46XX is not set
2622 # CONFIG_SND_CS5535AUDIO is not set
2623 # CONFIG_SND_CTXFI is not set
2624 # CONFIG_SND_DARLA20 is not set
2625 # CONFIG_SND_GINA20 is not set
2626 # CONFIG_SND_LAYLA20 is not set
2627 # CONFIG_SND_DARLA24 is not set
2628 # CONFIG_SND_GINA24 is not set
2629 # CONFIG_SND_LAYLA24 is not set
2630 # CONFIG_SND_MONA is not set
2631 # CONFIG_SND_MIA is not set
2632 # CONFIG_SND_ECHO3G is not set
2633 # CONFIG_SND_INDIGO is not set
2634 # CONFIG_SND_INDIGOIO is not set
2635 # CONFIG_SND_INDIGODJ is not set
2636 # CONFIG_SND_INDIGOIOX is not set
2637 # CONFIG_SND_INDIGODJX is not set
2638 # CONFIG_SND_EMU10K1 is not set
2639 # CONFIG_SND_EMU10K1X is not set
2640 # CONFIG_SND_ENS1370 is not set
2641 # CONFIG_SND_ENS1371 is not set
2642 # CONFIG_SND_ES1938 is not set
2643 # CONFIG_SND_ES1968 is not set
2644 # CONFIG_SND_FM801 is not set
2645 # CONFIG_SND_HDA_INTEL is not set
2646 # CONFIG_SND_HDSP is not set
2647 # CONFIG_SND_HDSPM is not set
2648 # CONFIG_SND_ICE1712 is not set
2649 # CONFIG_SND_ICE1724 is not set
2650 # CONFIG_SND_INTEL8X0 is not set
2651 # CONFIG_SND_INTEL8X0M is not set
2652 # CONFIG_SND_KORG1212 is not set
2653 # CONFIG_SND_LOLA is not set
2654 # CONFIG_SND_LX6464ES is not set
2655 # CONFIG_SND_MAESTRO3 is not set
2656 # CONFIG_SND_MIXART is not set
2657 # CONFIG_SND_NM256 is not set
2658 # CONFIG_SND_PCXHR is not set
2659 # CONFIG_SND_RIPTIDE is not set
2660 # CONFIG_SND_RME32 is not set
2661 # CONFIG_SND_RME96 is not set
2662 # CONFIG_SND_RME9652 is not set
2663 # CONFIG_SND_SONICVIBES is not set
2664 # CONFIG_SND_TRIDENT is not set
2665 # CONFIG_SND_VIA82XX is not set
2666 # CONFIG_SND_VIA82XX_MODEM is not set
2667 # CONFIG_SND_VIRTUOSO is not set
2668 # CONFIG_SND_VX222 is not set
2669 # CONFIG_SND_YMFPCI is not set
2254 CONFIG_SND_ARM=y 2670 CONFIG_SND_ARM=y
2255 # CONFIG_SND_SPI is not set 2671 # CONFIG_SND_SPI is not set
2256 # CONFIG_SND_USB is not set 2672 # CONFIG_SND_USB is not set
2257 CONFIG_SND_SOC=y 2673 CONFIG_SND_SOC=y
2258 CONFIG_SND_SOC_DMAENGINE_PCM=y 2674 CONFIG_SND_SOC_DMAENGINE_PCM=y
2259 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y 2675 CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
2260 # CONFIG_SND_ATMEL_SOC is not set 2676 # CONFIG_SND_ATMEL_SOC is not set
2261 # CONFIG_SND_DESIGNWARE_I2S is not set 2677 # CONFIG_SND_DESIGNWARE_I2S is not set
2262 CONFIG_SND_SOC_FSL_SAI=y 2678 CONFIG_SND_SOC_FSL_SAI=y
2263 CONFIG_SND_SOC_FSL_SSI=y 2679 CONFIG_SND_SOC_FSL_SSI=y
2264 CONFIG_SND_SOC_FSL_ASRC=y 2680 CONFIG_SND_SOC_FSL_ASRC=y
2265 CONFIG_SND_SOC_FSL_ESAI=y 2681 CONFIG_SND_SOC_FSL_ESAI=y
2266 CONFIG_SND_SOC_FSL_SPDIF=y 2682 CONFIG_SND_SOC_FSL_SPDIF=y
2267 CONFIG_SND_SOC_FSL_HDMI=y 2683 CONFIG_SND_SOC_FSL_HDMI=y
2268 CONFIG_SND_SOC_FSL_UTILS=y 2684 CONFIG_SND_SOC_FSL_UTILS=y
2269 CONFIG_SND_IMX_SOC=y 2685 CONFIG_SND_IMX_SOC=y
2270 CONFIG_SND_SOC_IMX_SSI=y 2686 CONFIG_SND_SOC_IMX_SSI=y
2271 CONFIG_SND_SOC_IMX_PCM_FIQ=y 2687 CONFIG_SND_SOC_IMX_PCM_FIQ=y
2272 CONFIG_SND_SOC_IMX_PCM_DMA=y 2688 CONFIG_SND_SOC_IMX_PCM_DMA=y
2273 CONFIG_SND_SOC_IMX_HDMI_DMA=y 2689 CONFIG_SND_SOC_IMX_HDMI_DMA=y
2274 CONFIG_SND_SOC_IMX_AUDMUX=y 2690 CONFIG_SND_SOC_IMX_AUDMUX=y
2275 CONFIG_SND_SOC_EUKREA_TLV320=y 2691 CONFIG_SND_SOC_EUKREA_TLV320=y
2276 CONFIG_SND_SOC_IMX_CS42888=y 2692 CONFIG_SND_SOC_IMX_CS42888=y
2277 CONFIG_SND_SOC_IMX_WM8962=y 2693 CONFIG_SND_SOC_IMX_WM8962=y
2278 # CONFIG_SND_SOC_IMX_WM8962_ANDROID is not set 2694 # CONFIG_SND_SOC_IMX_WM8962_ANDROID is not set
2279 CONFIG_SND_SOC_IMX_SGTL5000=y 2695 CONFIG_SND_SOC_IMX_SGTL5000=y
2280 CONFIG_SND_SOC_IMX_MQS=y 2696 CONFIG_SND_SOC_IMX_MQS=y
2281 CONFIG_SND_SOC_IMX_SPDIF=y 2697 CONFIG_SND_SOC_IMX_SPDIF=y
2282 CONFIG_SND_SOC_IMX_MC13783=y 2698 CONFIG_SND_SOC_IMX_MC13783=y
2283 CONFIG_SND_SOC_IMX_HDMI=y 2699 CONFIG_SND_SOC_IMX_HDMI=y
2284 CONFIG_SND_SOC_IMX_SI476X=y 2700 CONFIG_SND_SOC_IMX_SI476X=y
2285 CONFIG_SND_SOC_I2C_AND_SPI=y 2701 CONFIG_SND_SOC_I2C_AND_SPI=y
2286 # CONFIG_SND_SOC_ALL_CODECS is not set 2702 # CONFIG_SND_SOC_ALL_CODECS is not set
2287 # CONFIG_SND_SOC_CS42XX8_I2C is not set 2703 # CONFIG_SND_SOC_CS42XX8_I2C is not set
2288 CONFIG_SND_SOC_FSL_MQS=y 2704 CONFIG_SND_SOC_FSL_MQS=y
2289 CONFIG_SND_SOC_OMAP_HDMI_CODEC=y 2705 CONFIG_SND_SOC_OMAP_HDMI_CODEC=y
2290 CONFIG_SND_SOC_SGTL5000=y 2706 CONFIG_SND_SOC_SGTL5000=y
2291 CONFIG_SND_SOC_SI476X=y 2707 CONFIG_SND_SOC_SI476X=y
2292 CONFIG_SND_SOC_SPDIF=y 2708 CONFIG_SND_SOC_SPDIF=y
2293 CONFIG_SND_SOC_TLV320AIC23=y 2709 CONFIG_SND_SOC_TLV320AIC23=y
2294 CONFIG_SND_SOC_WM8962=y 2710 CONFIG_SND_SOC_WM8962=y
2295 CONFIG_SND_SOC_MC13783=y 2711 CONFIG_SND_SOC_MC13783=y
2296 # CONFIG_SND_SIMPLE_CARD is not set 2712 # CONFIG_SND_SIMPLE_CARD is not set
2297 # CONFIG_SOUND_PRIME is not set 2713 # CONFIG_SOUND_PRIME is not set
2298 2714
2299 # 2715 #
2300 # HID support 2716 # HID support
2301 # 2717 #
2302 CONFIG_HID=y 2718 CONFIG_HID=y
2303 # CONFIG_HID_BATTERY_STRENGTH is not set 2719 # CONFIG_HID_BATTERY_STRENGTH is not set
2304 # CONFIG_HIDRAW is not set 2720 # CONFIG_HIDRAW is not set
2305 # CONFIG_UHID is not set 2721 # CONFIG_UHID is not set
2306 CONFIG_HID_GENERIC=y 2722 CONFIG_HID_GENERIC=y
2307 2723
2308 # 2724 #
2309 # Special HID drivers 2725 # Special HID drivers
2310 # 2726 #
2311 # CONFIG_HID_A4TECH is not set 2727 # CONFIG_HID_A4TECH is not set
2312 # CONFIG_HID_ACRUX is not set 2728 # CONFIG_HID_ACRUX is not set
2313 # CONFIG_HID_APPLE is not set 2729 # CONFIG_HID_APPLE is not set
2314 # CONFIG_HID_APPLEIR is not set 2730 # CONFIG_HID_APPLEIR is not set
2315 # CONFIG_HID_AUREAL is not set 2731 # CONFIG_HID_AUREAL is not set
2316 # CONFIG_HID_BELKIN is not set 2732 # CONFIG_HID_BELKIN is not set
2317 # CONFIG_HID_CHERRY is not set 2733 # CONFIG_HID_CHERRY is not set
2318 # CONFIG_HID_CHICONY is not set 2734 # CONFIG_HID_CHICONY is not set
2319 # CONFIG_HID_PRODIKEYS is not set 2735 # CONFIG_HID_PRODIKEYS is not set
2320 # CONFIG_HID_CYPRESS is not set 2736 # CONFIG_HID_CYPRESS is not set
2321 # CONFIG_HID_DRAGONRISE is not set 2737 # CONFIG_HID_DRAGONRISE is not set
2322 # CONFIG_HID_EMS_FF is not set 2738 # CONFIG_HID_EMS_FF is not set
2323 # CONFIG_HID_ELECOM is not set 2739 # CONFIG_HID_ELECOM is not set
2324 # CONFIG_HID_EZKEY is not set 2740 # CONFIG_HID_EZKEY is not set
2325 # CONFIG_HID_HOLTEK is not set 2741 # CONFIG_HID_HOLTEK is not set
2326 # CONFIG_HID_KEYTOUCH is not set 2742 # CONFIG_HID_KEYTOUCH is not set
2327 # CONFIG_HID_KYE is not set 2743 # CONFIG_HID_KYE is not set
2328 # CONFIG_HID_UCLOGIC is not set 2744 # CONFIG_HID_UCLOGIC is not set
2329 # CONFIG_HID_WALTOP is not set 2745 # CONFIG_HID_WALTOP is not set
2330 # CONFIG_HID_GYRATION is not set 2746 # CONFIG_HID_GYRATION is not set
2331 # CONFIG_HID_ICADE is not set 2747 # CONFIG_HID_ICADE is not set
2332 # CONFIG_HID_TWINHAN is not set 2748 # CONFIG_HID_TWINHAN is not set
2333 # CONFIG_HID_KENSINGTON is not set 2749 # CONFIG_HID_KENSINGTON is not set
2334 # CONFIG_HID_LCPOWER is not set 2750 # CONFIG_HID_LCPOWER is not set
2335 # CONFIG_HID_LENOVO_TPKBD is not set 2751 # CONFIG_HID_LENOVO_TPKBD is not set
2336 # CONFIG_HID_LOGITECH is not set 2752 # CONFIG_HID_LOGITECH is not set
2337 # CONFIG_HID_MAGICMOUSE is not set 2753 # CONFIG_HID_MAGICMOUSE is not set
2338 # CONFIG_HID_MICROSOFT is not set 2754 # CONFIG_HID_MICROSOFT is not set
2339 # CONFIG_HID_MONTEREY is not set 2755 # CONFIG_HID_MONTEREY is not set
2340 # CONFIG_HID_MULTITOUCH is not set 2756 # CONFIG_HID_MULTITOUCH is not set
2341 # CONFIG_HID_NTRIG is not set 2757 # CONFIG_HID_NTRIG is not set
2342 # CONFIG_HID_ORTEK is not set 2758 # CONFIG_HID_ORTEK is not set
2343 # CONFIG_HID_PANTHERLORD is not set 2759 # CONFIG_HID_PANTHERLORD is not set
2344 # CONFIG_HID_PETALYNX is not set 2760 # CONFIG_HID_PETALYNX is not set
2345 # CONFIG_HID_PICOLCD is not set 2761 # CONFIG_HID_PICOLCD is not set
2346 # CONFIG_HID_PRIMAX is not set 2762 # CONFIG_HID_PRIMAX is not set
2347 # CONFIG_HID_PS3REMOTE is not set 2763 # CONFIG_HID_PS3REMOTE is not set
2348 # CONFIG_HID_ROCCAT is not set 2764 # CONFIG_HID_ROCCAT is not set
2349 # CONFIG_HID_SAITEK is not set 2765 # CONFIG_HID_SAITEK is not set
2350 # CONFIG_HID_SAMSUNG is not set 2766 # CONFIG_HID_SAMSUNG is not set
2351 # CONFIG_HID_SONY is not set 2767 # CONFIG_HID_SONY is not set
2352 # CONFIG_HID_SPEEDLINK is not set 2768 # CONFIG_HID_SPEEDLINK is not set
2353 # CONFIG_HID_STEELSERIES is not set 2769 # CONFIG_HID_STEELSERIES is not set
2354 # CONFIG_HID_SUNPLUS is not set 2770 # CONFIG_HID_SUNPLUS is not set
2355 # CONFIG_HID_GREENASIA is not set 2771 # CONFIG_HID_GREENASIA is not set
2356 # CONFIG_HID_SMARTJOYPLUS is not set 2772 # CONFIG_HID_SMARTJOYPLUS is not set
2357 # CONFIG_HID_TIVO is not set 2773 # CONFIG_HID_TIVO is not set
2358 # CONFIG_HID_TOPSEED is not set 2774 # CONFIG_HID_TOPSEED is not set
2359 # CONFIG_HID_THINGM is not set 2775 # CONFIG_HID_THINGM is not set
2360 # CONFIG_HID_THRUSTMASTER is not set 2776 # CONFIG_HID_THRUSTMASTER is not set
2361 # CONFIG_HID_WACOM is not set 2777 # CONFIG_HID_WACOM is not set
2362 # CONFIG_HID_WIIMOTE is not set 2778 # CONFIG_HID_WIIMOTE is not set
2363 # CONFIG_HID_ZEROPLUS is not set 2779 # CONFIG_HID_ZEROPLUS is not set
2364 # CONFIG_HID_ZYDACRON is not set 2780 # CONFIG_HID_ZYDACRON is not set
2365 # CONFIG_HID_SENSOR_HUB is not set 2781 # CONFIG_HID_SENSOR_HUB is not set
2366 2782
2367 # 2783 #
2368 # USB HID support 2784 # USB HID support
2369 # 2785 #
2370 CONFIG_USB_HID=y 2786 CONFIG_USB_HID=y
2371 # CONFIG_HID_PID is not set 2787 # CONFIG_HID_PID is not set
2372 # CONFIG_USB_HIDDEV is not set 2788 # CONFIG_USB_HIDDEV is not set
2373 2789
2374 # 2790 #
2375 # I2C HID support 2791 # I2C HID support
2376 # 2792 #
2377 # CONFIG_I2C_HID is not set 2793 # CONFIG_I2C_HID is not set
2378 # CONFIG_USB_ARCH_HAS_OHCI is not set 2794 CONFIG_USB_ARCH_HAS_OHCI=y
2379 CONFIG_USB_ARCH_HAS_EHCI=y 2795 CONFIG_USB_ARCH_HAS_EHCI=y
2380 # CONFIG_USB_ARCH_HAS_XHCI is not set 2796 CONFIG_USB_ARCH_HAS_XHCI=y
2381 CONFIG_USB_SUPPORT=y 2797 CONFIG_USB_SUPPORT=y
2382 CONFIG_USB_COMMON=y 2798 CONFIG_USB_COMMON=y
2383 CONFIG_USB_ARCH_HAS_HCD=y 2799 CONFIG_USB_ARCH_HAS_HCD=y
2384 CONFIG_USB=y 2800 CONFIG_USB=y
2385 # CONFIG_USB_DEBUG is not set 2801 # CONFIG_USB_DEBUG is not set
2386 # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set 2802 # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
2387 2803
2388 # 2804 #
2389 # Miscellaneous USB options 2805 # Miscellaneous USB options
2390 # 2806 #
2391 CONFIG_USB_DEFAULT_PERSIST=y 2807 CONFIG_USB_DEFAULT_PERSIST=y
2392 # CONFIG_USB_DYNAMIC_MINORS is not set 2808 # CONFIG_USB_DYNAMIC_MINORS is not set
2393 # CONFIG_USB_OTG is not set 2809 # CONFIG_USB_OTG is not set
2394 # CONFIG_USB_OTG_WHITELIST is not set 2810 # CONFIG_USB_OTG_WHITELIST is not set
2395 # CONFIG_USB_OTG_BLACKLIST_HUB is not set 2811 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
2396 # CONFIG_USB_OTG_FSM is not set 2812 # CONFIG_USB_OTG_FSM is not set
2397 # CONFIG_USB_MON is not set 2813 # CONFIG_USB_MON is not set
2398 # CONFIG_USB_WUSB_CBAF is not set 2814 # CONFIG_USB_WUSB_CBAF is not set
2399 2815
2400 # 2816 #
2401 # USB Host Controller Drivers 2817 # USB Host Controller Drivers
2402 # 2818 #
2403 # CONFIG_USB_C67X00_HCD is not set 2819 # CONFIG_USB_C67X00_HCD is not set
2820 # CONFIG_USB_XHCI_HCD is not set
2404 CONFIG_USB_EHCI_HCD=y 2821 CONFIG_USB_EHCI_HCD=y
2405 CONFIG_USB_EHCI_ROOT_HUB_TT=y 2822 CONFIG_USB_EHCI_ROOT_HUB_TT=y
2406 CONFIG_USB_EHCI_TT_NEWSCHED=y 2823 CONFIG_USB_EHCI_TT_NEWSCHED=y
2824 CONFIG_USB_EHCI_PCI=y
2407 # CONFIG_USB_EHCI_MXC is not set 2825 # CONFIG_USB_EHCI_MXC is not set
2408 # CONFIG_USB_EHCI_HCD_PLATFORM is not set 2826 # CONFIG_USB_EHCI_HCD_PLATFORM is not set
2409 # CONFIG_USB_OXU210HP_HCD is not set 2827 # CONFIG_USB_OXU210HP_HCD is not set
2410 # CONFIG_USB_ISP116X_HCD is not set 2828 # CONFIG_USB_ISP116X_HCD is not set
2411 # CONFIG_USB_ISP1760_HCD is not set 2829 # CONFIG_USB_ISP1760_HCD is not set
2412 # CONFIG_USB_ISP1362_HCD is not set 2830 # CONFIG_USB_ISP1362_HCD is not set
2831 # CONFIG_USB_OHCI_HCD is not set
2832 # CONFIG_USB_UHCI_HCD is not set
2413 # CONFIG_USB_SL811_HCD is not set 2833 # CONFIG_USB_SL811_HCD is not set
2414 # CONFIG_USB_R8A66597_HCD is not set 2834 # CONFIG_USB_R8A66597_HCD is not set
2415 # CONFIG_USB_IMX21_HCD is not set 2835 # CONFIG_USB_IMX21_HCD is not set
2416 CONFIG_USB_HCD_TEST_MODE=y 2836 CONFIG_USB_HCD_TEST_MODE=y
2417 # CONFIG_USB_MUSB_HDRC is not set 2837 # CONFIG_USB_MUSB_HDRC is not set
2418 # CONFIG_USB_RENESAS_USBHS is not set 2838 # CONFIG_USB_RENESAS_USBHS is not set
2419 2839
2420 # 2840 #
2421 # USB Device Class drivers 2841 # USB Device Class drivers
2422 # 2842 #
2423 # CONFIG_USB_ACM is not set 2843 # CONFIG_USB_ACM is not set
2424 # CONFIG_USB_PRINTER is not set 2844 # CONFIG_USB_PRINTER is not set
2425 # CONFIG_USB_WDM is not set 2845 # CONFIG_USB_WDM is not set
2426 # CONFIG_USB_TMC is not set 2846 # CONFIG_USB_TMC is not set
2427 2847
2428 # 2848 #
2429 # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may 2849 # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
2430 # 2850 #
2431 2851
2432 # 2852 #
2433 # also be needed; see USB_STORAGE Help for more info 2853 # also be needed; see USB_STORAGE Help for more info
2434 # 2854 #
2435 CONFIG_USB_STORAGE=y 2855 CONFIG_USB_STORAGE=y
2436 # CONFIG_USB_STORAGE_DEBUG is not set 2856 # CONFIG_USB_STORAGE_DEBUG is not set
2437 # CONFIG_USB_STORAGE_REALTEK is not set 2857 # CONFIG_USB_STORAGE_REALTEK is not set
2438 # CONFIG_USB_STORAGE_DATAFAB is not set 2858 # CONFIG_USB_STORAGE_DATAFAB is not set
2439 # CONFIG_USB_STORAGE_FREECOM is not set 2859 # CONFIG_USB_STORAGE_FREECOM is not set
2440 # CONFIG_USB_STORAGE_ISD200 is not set 2860 # CONFIG_USB_STORAGE_ISD200 is not set
2441 # CONFIG_USB_STORAGE_USBAT is not set 2861 # CONFIG_USB_STORAGE_USBAT is not set
2442 # CONFIG_USB_STORAGE_SDDR09 is not set 2862 # CONFIG_USB_STORAGE_SDDR09 is not set
2443 # CONFIG_USB_STORAGE_SDDR55 is not set 2863 # CONFIG_USB_STORAGE_SDDR55 is not set
2444 # CONFIG_USB_STORAGE_JUMPSHOT is not set 2864 # CONFIG_USB_STORAGE_JUMPSHOT is not set
2445 # CONFIG_USB_STORAGE_ALAUDA is not set 2865 # CONFIG_USB_STORAGE_ALAUDA is not set
2446 # CONFIG_USB_STORAGE_ONETOUCH is not set 2866 # CONFIG_USB_STORAGE_ONETOUCH is not set
2447 # CONFIG_USB_STORAGE_KARMA is not set 2867 # CONFIG_USB_STORAGE_KARMA is not set
2448 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set 2868 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
2449 # CONFIG_USB_STORAGE_ENE_UB6250 is not set 2869 # CONFIG_USB_STORAGE_ENE_UB6250 is not set
2450 2870
2451 # 2871 #
2452 # USB Imaging devices 2872 # USB Imaging devices
2453 # 2873 #
2454 # CONFIG_USB_MDC800 is not set 2874 # CONFIG_USB_MDC800 is not set
2455 # CONFIG_USB_MICROTEK is not set 2875 # CONFIG_USB_MICROTEK is not set
2456 # CONFIG_USB_DWC3 is not set 2876 # CONFIG_USB_DWC3 is not set
2457 CONFIG_USB_CHIPIDEA=y 2877 CONFIG_USB_CHIPIDEA=y
2458 CONFIG_USB_CHIPIDEA_UDC=y 2878 CONFIG_USB_CHIPIDEA_UDC=y
2459 CONFIG_USB_CHIPIDEA_HOST=y 2879 CONFIG_USB_CHIPIDEA_HOST=y
2460 # CONFIG_USB_CHIPIDEA_DEBUG is not set 2880 # CONFIG_USB_CHIPIDEA_DEBUG is not set
2461 2881
2462 # 2882 #
2463 # USB port drivers 2883 # USB port drivers
2464 # 2884 #
2465 # CONFIG_USB_SERIAL is not set 2885 # CONFIG_USB_SERIAL is not set
2466 2886
2467 # 2887 #
2468 # USB Miscellaneous drivers 2888 # USB Miscellaneous drivers
2469 # 2889 #
2470 # CONFIG_USB_EMI62 is not set 2890 # CONFIG_USB_EMI62 is not set
2471 # CONFIG_USB_EMI26 is not set 2891 # CONFIG_USB_EMI26 is not set
2472 # CONFIG_USB_ADUTUX is not set 2892 # CONFIG_USB_ADUTUX is not set
2473 # CONFIG_USB_SEVSEG is not set 2893 # CONFIG_USB_SEVSEG is not set
2474 # CONFIG_USB_RIO500 is not set 2894 # CONFIG_USB_RIO500 is not set
2475 # CONFIG_USB_LEGOTOWER is not set 2895 # CONFIG_USB_LEGOTOWER is not set
2476 # CONFIG_USB_LCD is not set 2896 # CONFIG_USB_LCD is not set
2477 # CONFIG_USB_LED is not set 2897 # CONFIG_USB_LED is not set
2478 # CONFIG_USB_CYPRESS_CY7C63 is not set 2898 # CONFIG_USB_CYPRESS_CY7C63 is not set
2479 # CONFIG_USB_CYTHERM is not set 2899 # CONFIG_USB_CYTHERM is not set
2480 # CONFIG_USB_IDMOUSE is not set 2900 # CONFIG_USB_IDMOUSE is not set
2481 # CONFIG_USB_FTDI_ELAN is not set 2901 # CONFIG_USB_FTDI_ELAN is not set
2482 # CONFIG_USB_APPLEDISPLAY is not set 2902 # CONFIG_USB_APPLEDISPLAY is not set
2483 # CONFIG_USB_SISUSBVGA is not set 2903 # CONFIG_USB_SISUSBVGA is not set
2484 # CONFIG_USB_LD is not set 2904 # CONFIG_USB_LD is not set
2485 # CONFIG_USB_TRANCEVIBRATOR is not set 2905 # CONFIG_USB_TRANCEVIBRATOR is not set
2486 # CONFIG_USB_IOWARRIOR is not set 2906 # CONFIG_USB_IOWARRIOR is not set
2487 # CONFIG_USB_TEST is not set 2907 # CONFIG_USB_TEST is not set
2488 CONFIG_USB_EHSET_TEST_FIXTURE=m 2908 CONFIG_USB_EHSET_TEST_FIXTURE=m
2489 # CONFIG_USB_ISIGHTFW is not set 2909 # CONFIG_USB_ISIGHTFW is not set
2490 # CONFIG_USB_YUREX is not set 2910 # CONFIG_USB_YUREX is not set
2491 # CONFIG_USB_EZUSB_FX2 is not set 2911 # CONFIG_USB_EZUSB_FX2 is not set
2492 # CONFIG_USB_HSIC_USB3503 is not set 2912 # CONFIG_USB_HSIC_USB3503 is not set
2493 2913
2494 # 2914 #
2495 # USB Physical Layer drivers 2915 # USB Physical Layer drivers
2496 # 2916 #
2497 CONFIG_USB_PHY=y 2917 CONFIG_USB_PHY=y
2498 CONFIG_NOP_USB_XCEIV=y 2918 CONFIG_NOP_USB_XCEIV=y
2499 # CONFIG_OMAP_CONTROL_USB is not set 2919 # CONFIG_OMAP_CONTROL_USB is not set
2500 # CONFIG_OMAP_USB3 is not set 2920 # CONFIG_OMAP_USB3 is not set
2501 # CONFIG_SAMSUNG_USBPHY is not set 2921 # CONFIG_SAMSUNG_USBPHY is not set
2502 # CONFIG_SAMSUNG_USB2PHY is not set 2922 # CONFIG_SAMSUNG_USB2PHY is not set
2503 # CONFIG_SAMSUNG_USB3PHY is not set 2923 # CONFIG_SAMSUNG_USB3PHY is not set
2504 # CONFIG_USB_GPIO_VBUS is not set 2924 # CONFIG_USB_GPIO_VBUS is not set
2505 # CONFIG_USB_ISP1301 is not set 2925 # CONFIG_USB_ISP1301 is not set
2506 CONFIG_USB_MXS_PHY=y 2926 CONFIG_USB_MXS_PHY=y
2507 # CONFIG_USB_RCAR_PHY is not set 2927 # CONFIG_USB_RCAR_PHY is not set
2508 # CONFIG_USB_ULPI is not set 2928 # CONFIG_USB_ULPI is not set
2509 CONFIG_USB_GADGET=y 2929 CONFIG_USB_GADGET=y
2510 # CONFIG_USB_GADGET_DEBUG is not set 2930 # CONFIG_USB_GADGET_DEBUG is not set
2511 # CONFIG_USB_GADGET_DEBUG_FILES is not set 2931 # CONFIG_USB_GADGET_DEBUG_FILES is not set
2512 # CONFIG_USB_GADGET_DEBUG_FS is not set 2932 # CONFIG_USB_GADGET_DEBUG_FS is not set
2513 CONFIG_USB_GADGET_VBUS_DRAW=2 2933 CONFIG_USB_GADGET_VBUS_DRAW=2
2514 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 2934 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
2515 2935
2516 # 2936 #
2517 # USB Peripheral Controller 2937 # USB Peripheral Controller
2518 # 2938 #
2519 # CONFIG_USB_FSL_USB2 is not set 2939 # CONFIG_USB_FSL_USB2 is not set
2520 # CONFIG_USB_FUSB300 is not set 2940 # CONFIG_USB_FUSB300 is not set
2521 # CONFIG_USB_R8A66597 is not set 2941 # CONFIG_USB_R8A66597 is not set
2522 # CONFIG_USB_PXA27X is not set 2942 # CONFIG_USB_PXA27X is not set
2523 # CONFIG_USB_MV_UDC is not set 2943 # CONFIG_USB_MV_UDC is not set
2524 # CONFIG_USB_MV_U3D is not set 2944 # CONFIG_USB_MV_U3D is not set
2525 # CONFIG_USB_M66592 is not set 2945 # CONFIG_USB_M66592 is not set
2946 # CONFIG_USB_AMD5536UDC is not set
2526 # CONFIG_USB_NET2272 is not set 2947 # CONFIG_USB_NET2272 is not set
2948 # CONFIG_USB_NET2280 is not set
2949 # CONFIG_USB_GOKU is not set
2950 # CONFIG_USB_EG20T is not set
2527 # CONFIG_USB_DUMMY_HCD is not set 2951 # CONFIG_USB_DUMMY_HCD is not set
2528 CONFIG_USB_LIBCOMPOSITE=m 2952 CONFIG_USB_LIBCOMPOSITE=m
2529 CONFIG_USB_F_ACM=m 2953 CONFIG_USB_F_ACM=m
2530 CONFIG_USB_F_SS_LB=m 2954 CONFIG_USB_F_SS_LB=m
2531 CONFIG_USB_U_SERIAL=m 2955 CONFIG_USB_U_SERIAL=m
2532 CONFIG_USB_F_SERIAL=m 2956 CONFIG_USB_F_SERIAL=m
2533 CONFIG_USB_F_OBEX=m 2957 CONFIG_USB_F_OBEX=m
2534 CONFIG_USB_ZERO=m 2958 CONFIG_USB_ZERO=m
2535 # CONFIG_USB_AUDIO is not set 2959 # CONFIG_USB_AUDIO is not set
2536 CONFIG_USB_ETH=m 2960 CONFIG_USB_ETH=m
2537 CONFIG_USB_ETH_RNDIS=y 2961 CONFIG_USB_ETH_RNDIS=y
2538 # CONFIG_USB_ETH_EEM is not set 2962 # CONFIG_USB_ETH_EEM is not set
2539 CONFIG_USB_G_NCM=m 2963 CONFIG_USB_G_NCM=m
2540 # CONFIG_USB_GADGETFS is not set 2964 # CONFIG_USB_GADGETFS is not set
2541 # CONFIG_USB_FUNCTIONFS is not set 2965 # CONFIG_USB_FUNCTIONFS is not set
2542 CONFIG_USB_MASS_STORAGE=m 2966 CONFIG_USB_MASS_STORAGE=m
2543 # CONFIG_FSL_UTP is not set 2967 # CONFIG_FSL_UTP is not set
2544 CONFIG_USB_G_SERIAL=m 2968 CONFIG_USB_G_SERIAL=m
2545 # CONFIG_USB_MIDI_GADGET is not set 2969 # CONFIG_USB_MIDI_GADGET is not set
2546 # CONFIG_USB_G_PRINTER is not set 2970 # CONFIG_USB_G_PRINTER is not set
2547 # CONFIG_USB_CDC_COMPOSITE is not set 2971 # CONFIG_USB_CDC_COMPOSITE is not set
2548 # CONFIG_USB_G_ACM_MS is not set 2972 # CONFIG_USB_G_ACM_MS is not set
2549 # CONFIG_USB_G_MULTI is not set 2973 # CONFIG_USB_G_MULTI is not set
2550 # CONFIG_USB_G_HID is not set 2974 # CONFIG_USB_G_HID is not set
2551 # CONFIG_USB_G_DBGP is not set 2975 # CONFIG_USB_G_DBGP is not set
2552 # CONFIG_USB_G_WEBCAM is not set 2976 # CONFIG_USB_G_WEBCAM is not set
2977 # CONFIG_UWB is not set
2553 CONFIG_MMC=y 2978 CONFIG_MMC=y
2554 # CONFIG_MMC_DEBUG is not set 2979 # CONFIG_MMC_DEBUG is not set
2555 CONFIG_MMC_UNSAFE_RESUME=y 2980 CONFIG_MMC_UNSAFE_RESUME=y
2556 # CONFIG_MMC_CLKGATE is not set 2981 # CONFIG_MMC_CLKGATE is not set
2557 2982
2558 # 2983 #
2559 # MMC/SD/SDIO Card Drivers 2984 # MMC/SD/SDIO Card Drivers
2560 # 2985 #
2561 CONFIG_MMC_BLOCK=y 2986 CONFIG_MMC_BLOCK=y
2562 CONFIG_MMC_BLOCK_MINORS=8 2987 CONFIG_MMC_BLOCK_MINORS=8
2563 CONFIG_MMC_BLOCK_BOUNCE=y 2988 CONFIG_MMC_BLOCK_BOUNCE=y
2564 # CONFIG_SDIO_UART is not set 2989 # CONFIG_SDIO_UART is not set
2565 # CONFIG_MMC_TEST is not set 2990 # CONFIG_MMC_TEST is not set
2566 2991
2567 # 2992 #
2568 # MMC/SD/SDIO Host Controller Drivers 2993 # MMC/SD/SDIO Host Controller Drivers
2569 # 2994 #
2570 CONFIG_MMC_SDHCI=y 2995 CONFIG_MMC_SDHCI=y
2571 CONFIG_MMC_SDHCI_IO_ACCESSORS=y 2996 CONFIG_MMC_SDHCI_IO_ACCESSORS=y
2997 # CONFIG_MMC_SDHCI_PCI is not set
2572 CONFIG_MMC_SDHCI_PLTFM=y 2998 CONFIG_MMC_SDHCI_PLTFM=y
2573 CONFIG_MMC_SDHCI_ESDHC_IMX=y 2999 CONFIG_MMC_SDHCI_ESDHC_IMX=y
2574 # CONFIG_MMC_SDHCI_PXAV3 is not set 3000 # CONFIG_MMC_SDHCI_PXAV3 is not set
2575 # CONFIG_MMC_SDHCI_PXAV2 is not set 3001 # CONFIG_MMC_SDHCI_PXAV2 is not set
2576 # CONFIG_MMC_MXC is not set 3002 # CONFIG_MMC_MXC is not set
3003 # CONFIG_MMC_TIFM_SD is not set
3004 # CONFIG_MMC_CB710 is not set
3005 # CONFIG_MMC_VIA_SDMMC is not set
2577 # CONFIG_MMC_DW is not set 3006 # CONFIG_MMC_DW is not set
2578 # CONFIG_MMC_VUB300 is not set 3007 # CONFIG_MMC_VUB300 is not set
2579 # CONFIG_MMC_USHC is not set 3008 # CONFIG_MMC_USHC is not set
2580 # CONFIG_MEMSTICK is not set 3009 # CONFIG_MEMSTICK is not set
2581 3010
2582 # 3011 #
2583 # MXC support drivers 3012 # MXC support drivers
2584 # 3013 #
2585 CONFIG_MXC_IPU=y 3014 CONFIG_MXC_IPU=y
2586 3015
2587 # 3016 #
2588 # MXC Vivante GPU support 3017 # MXC Vivante GPU support
2589 # 3018 #
2590 CONFIG_MXC_GPU_VIV=y 3019 CONFIG_MXC_GPU_VIV=y
2591 CONFIG_MXC_IPU_V3=y 3020 CONFIG_MXC_IPU_V3=y
2592 3021
2593 # 3022 #
2594 # MXC Asynchronous Sample Rate Converter support 3023 # MXC Asynchronous Sample Rate Converter support
2595 # 3024 #
2596 CONFIG_MXC_ASRC=y 3025 CONFIG_MXC_ASRC=y
2597 3026
2598 # 3027 #
2599 # MXC VPU(Video Processing Unit) support 3028 # MXC VPU(Video Processing Unit) support
2600 # 3029 #
2601 CONFIG_MXC_VPU=y 3030 CONFIG_MXC_VPU=y
2602 # CONFIG_MXC_VPU_DEBUG is not set 3031 # CONFIG_MXC_VPU_DEBUG is not set
2603 # CONFIG_MX6_VPU_352M is not set 3032 # CONFIG_MX6_VPU_352M is not set
2604 3033
2605 # 3034 #
2606 # MXC HDMI CEC (Consumer Electronics Control) support 3035 # MXC HDMI CEC (Consumer Electronics Control) support
2607 # 3036 #
2608 # CONFIG_MXC_HDMI_CEC is not set 3037 # CONFIG_MXC_HDMI_CEC is not set
2609 3038
2610 # 3039 #
2611 # MXC MIPI Support 3040 # MXC MIPI Support
2612 # 3041 #
2613 CONFIG_MXC_MIPI_CSI2=y 3042 CONFIG_MXC_MIPI_CSI2=y
2614 3043
2615 # 3044 #
2616 # MXC Media Local Bus Driver 3045 # MXC Media Local Bus Driver
2617 # 3046 #
2618 CONFIG_MXC_MLB=y 3047 CONFIG_MXC_MLB=y
2619 CONFIG_MXC_MLB150=m 3048 CONFIG_MXC_MLB150=m
2620 CONFIG_LEDS_GPIO_REGISTER=y 3049 CONFIG_LEDS_GPIO_REGISTER=y
2621 CONFIG_NEW_LEDS=y 3050 CONFIG_NEW_LEDS=y
2622 CONFIG_LEDS_CLASS=y 3051 CONFIG_LEDS_CLASS=y
2623 3052
2624 # 3053 #
2625 # LED drivers 3054 # LED drivers
2626 # 3055 #
2627 # CONFIG_LEDS_LM3530 is not set 3056 # CONFIG_LEDS_LM3530 is not set
2628 # CONFIG_LEDS_LM3642 is not set 3057 # CONFIG_LEDS_LM3642 is not set
2629 # CONFIG_LEDS_PCA9532 is not set 3058 # CONFIG_LEDS_PCA9532 is not set
2630 CONFIG_LEDS_GPIO=y 3059 CONFIG_LEDS_GPIO=y
2631 # CONFIG_LEDS_LP3944 is not set 3060 # CONFIG_LEDS_LP3944 is not set
2632 # CONFIG_LEDS_LP5521 is not set 3061 # CONFIG_LEDS_LP5521 is not set
2633 # CONFIG_LEDS_LP5523 is not set 3062 # CONFIG_LEDS_LP5523 is not set
2634 # CONFIG_LEDS_LP5562 is not set 3063 # CONFIG_LEDS_LP5562 is not set
2635 # CONFIG_LEDS_PCA955X is not set 3064 # CONFIG_LEDS_PCA955X is not set
2636 # CONFIG_LEDS_PCA9633 is not set 3065 # CONFIG_LEDS_PCA9633 is not set
2637 # CONFIG_LEDS_DA9052 is not set 3066 # CONFIG_LEDS_DA9052 is not set
2638 # CONFIG_LEDS_DAC124S085 is not set 3067 # CONFIG_LEDS_DAC124S085 is not set
2639 # CONFIG_LEDS_PWM is not set 3068 # CONFIG_LEDS_PWM is not set
2640 # CONFIG_LEDS_REGULATOR is not set 3069 # CONFIG_LEDS_REGULATOR is not set
2641 # CONFIG_LEDS_BD2802 is not set 3070 # CONFIG_LEDS_BD2802 is not set
2642 # CONFIG_LEDS_LT3593 is not set 3071 # CONFIG_LEDS_LT3593 is not set
2643 # CONFIG_LEDS_MC13783 is not set 3072 # CONFIG_LEDS_MC13783 is not set
2644 # CONFIG_LEDS_RENESAS_TPU is not set 3073 # CONFIG_LEDS_RENESAS_TPU is not set
2645 # CONFIG_LEDS_TCA6507 is not set 3074 # CONFIG_LEDS_TCA6507 is not set
2646 # CONFIG_LEDS_LM355x is not set 3075 # CONFIG_LEDS_LM355x is not set
2647 # CONFIG_LEDS_OT200 is not set 3076 # CONFIG_LEDS_OT200 is not set
2648 # CONFIG_LEDS_BLINKM is not set 3077 # CONFIG_LEDS_BLINKM is not set
2649 3078
2650 # 3079 #
2651 # LED Triggers 3080 # LED Triggers
2652 # 3081 #
2653 CONFIG_LEDS_TRIGGERS=y 3082 CONFIG_LEDS_TRIGGERS=y
2654 # CONFIG_LEDS_TRIGGER_TIMER is not set 3083 # CONFIG_LEDS_TRIGGER_TIMER is not set
2655 # CONFIG_LEDS_TRIGGER_ONESHOT is not set 3084 # CONFIG_LEDS_TRIGGER_ONESHOT is not set
2656 # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set 3085 # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
2657 # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set 3086 # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
2658 # CONFIG_LEDS_TRIGGER_CPU is not set 3087 # CONFIG_LEDS_TRIGGER_CPU is not set
2659 CONFIG_LEDS_TRIGGER_GPIO=y 3088 CONFIG_LEDS_TRIGGER_GPIO=y
2660 # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set 3089 # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
2661 3090
2662 # 3091 #
2663 # iptables trigger is under Netfilter config (LED target) 3092 # iptables trigger is under Netfilter config (LED target)
2664 # 3093 #
2665 # CONFIG_LEDS_TRIGGER_TRANSIENT is not set 3094 # CONFIG_LEDS_TRIGGER_TRANSIENT is not set
2666 # CONFIG_LEDS_TRIGGER_CAMERA is not set 3095 # CONFIG_LEDS_TRIGGER_CAMERA is not set
2667 # CONFIG_ACCESSIBILITY is not set 3096 # CONFIG_ACCESSIBILITY is not set
3097 # CONFIG_INFINIBAND is not set
2668 # CONFIG_EDAC is not set 3098 # CONFIG_EDAC is not set
2669 CONFIG_RTC_LIB=y 3099 CONFIG_RTC_LIB=y
2670 CONFIG_RTC_CLASS=y 3100 CONFIG_RTC_CLASS=y
2671 CONFIG_RTC_HCTOSYS=y 3101 CONFIG_RTC_HCTOSYS=y
2672 CONFIG_RTC_SYSTOHC=y 3102 CONFIG_RTC_SYSTOHC=y
2673 CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 3103 CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
2674 # CONFIG_RTC_DEBUG is not set 3104 # CONFIG_RTC_DEBUG is not set
2675 3105
2676 # 3106 #
2677 # RTC interfaces 3107 # RTC interfaces
2678 # 3108 #
2679 CONFIG_RTC_INTF_SYSFS=y 3109 CONFIG_RTC_INTF_SYSFS=y
2680 CONFIG_RTC_INTF_PROC=y 3110 CONFIG_RTC_INTF_PROC=y
2681 CONFIG_RTC_INTF_DEV=y 3111 CONFIG_RTC_INTF_DEV=y
2682 CONFIG_RTC_INTF_DEV_UIE_EMUL=y 3112 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
2683 # CONFIG_RTC_DRV_TEST is not set 3113 # CONFIG_RTC_DRV_TEST is not set
2684 3114
2685 # 3115 #
2686 # I2C RTC drivers 3116 # I2C RTC drivers
2687 # 3117 #
2688 # CONFIG_RTC_DRV_DS1307 is not set 3118 # CONFIG_RTC_DRV_DS1307 is not set
2689 # CONFIG_RTC_DRV_DS1374 is not set 3119 # CONFIG_RTC_DRV_DS1374 is not set
2690 # CONFIG_RTC_DRV_DS1672 is not set 3120 # CONFIG_RTC_DRV_DS1672 is not set
2691 # CONFIG_RTC_DRV_DS3232 is not set 3121 # CONFIG_RTC_DRV_DS3232 is not set
2692 # CONFIG_RTC_DRV_MAX6900 is not set 3122 # CONFIG_RTC_DRV_MAX6900 is not set
2693 # CONFIG_RTC_DRV_RS5C372 is not set 3123 # CONFIG_RTC_DRV_RS5C372 is not set
2694 # CONFIG_RTC_DRV_ISL1208 is not set 3124 # CONFIG_RTC_DRV_ISL1208 is not set
2695 # CONFIG_RTC_DRV_ISL12022 is not set 3125 # CONFIG_RTC_DRV_ISL12022 is not set
2696 # CONFIG_RTC_DRV_X1205 is not set 3126 # CONFIG_RTC_DRV_X1205 is not set
2697 # CONFIG_RTC_DRV_PCF8523 is not set 3127 # CONFIG_RTC_DRV_PCF8523 is not set
2698 # CONFIG_RTC_DRV_PCF8563 is not set 3128 # CONFIG_RTC_DRV_PCF8563 is not set
2699 # CONFIG_RTC_DRV_PCF8583 is not set 3129 # CONFIG_RTC_DRV_PCF8583 is not set
2700 # CONFIG_RTC_DRV_M41T80 is not set 3130 # CONFIG_RTC_DRV_M41T80 is not set
2701 # CONFIG_RTC_DRV_BQ32K is not set 3131 # CONFIG_RTC_DRV_BQ32K is not set
2702 CONFIG_RTC_DRV_S35390A=y 3132 CONFIG_RTC_DRV_S35390A=y
2703 # CONFIG_RTC_DRV_FM3130 is not set 3133 # CONFIG_RTC_DRV_FM3130 is not set
2704 # CONFIG_RTC_DRV_RX8581 is not set 3134 # CONFIG_RTC_DRV_RX8581 is not set
2705 # CONFIG_RTC_DRV_RX8025 is not set 3135 # CONFIG_RTC_DRV_RX8025 is not set
2706 # CONFIG_RTC_DRV_EM3027 is not set 3136 # CONFIG_RTC_DRV_EM3027 is not set
2707 # CONFIG_RTC_DRV_RV3029C2 is not set 3137 # CONFIG_RTC_DRV_RV3029C2 is not set
2708 3138
2709 # 3139 #
2710 # SPI RTC drivers 3140 # SPI RTC drivers
2711 # 3141 #
2712 # CONFIG_RTC_DRV_M41T93 is not set 3142 # CONFIG_RTC_DRV_M41T93 is not set
2713 # CONFIG_RTC_DRV_M41T94 is not set 3143 # CONFIG_RTC_DRV_M41T94 is not set
2714 # CONFIG_RTC_DRV_DS1305 is not set 3144 # CONFIG_RTC_DRV_DS1305 is not set
2715 # CONFIG_RTC_DRV_DS1390 is not set 3145 # CONFIG_RTC_DRV_DS1390 is not set
2716 # CONFIG_RTC_DRV_MAX6902 is not set 3146 # CONFIG_RTC_DRV_MAX6902 is not set
2717 # CONFIG_RTC_DRV_R9701 is not set 3147 # CONFIG_RTC_DRV_R9701 is not set
2718 # CONFIG_RTC_DRV_RS5C348 is not set 3148 # CONFIG_RTC_DRV_RS5C348 is not set
2719 # CONFIG_RTC_DRV_DS3234 is not set 3149 # CONFIG_RTC_DRV_DS3234 is not set
2720 # CONFIG_RTC_DRV_PCF2123 is not set 3150 # CONFIG_RTC_DRV_PCF2123 is not set
2721 # CONFIG_RTC_DRV_RX4581 is not set 3151 # CONFIG_RTC_DRV_RX4581 is not set
2722 3152
2723 # 3153 #
2724 # Platform RTC drivers 3154 # Platform RTC drivers
2725 # 3155 #
2726 # CONFIG_RTC_DRV_CMOS is not set 3156 # CONFIG_RTC_DRV_CMOS is not set
2727 # CONFIG_RTC_DRV_DS1286 is not set 3157 # CONFIG_RTC_DRV_DS1286 is not set
2728 # CONFIG_RTC_DRV_DS1511 is not set 3158 # CONFIG_RTC_DRV_DS1511 is not set
2729 # CONFIG_RTC_DRV_DS1553 is not set 3159 # CONFIG_RTC_DRV_DS1553 is not set
2730 # CONFIG_RTC_DRV_DS1742 is not set 3160 # CONFIG_RTC_DRV_DS1742 is not set
2731 # CONFIG_RTC_DRV_DA9052 is not set 3161 # CONFIG_RTC_DRV_DA9052 is not set
2732 # CONFIG_RTC_DRV_STK17TA8 is not set 3162 # CONFIG_RTC_DRV_STK17TA8 is not set
2733 # CONFIG_RTC_DRV_M48T86 is not set 3163 # CONFIG_RTC_DRV_M48T86 is not set
2734 # CONFIG_RTC_DRV_M48T35 is not set 3164 # CONFIG_RTC_DRV_M48T35 is not set
2735 # CONFIG_RTC_DRV_M48T59 is not set 3165 # CONFIG_RTC_DRV_M48T59 is not set
2736 # CONFIG_RTC_DRV_MSM6242 is not set 3166 # CONFIG_RTC_DRV_MSM6242 is not set
2737 # CONFIG_RTC_DRV_BQ4802 is not set 3167 # CONFIG_RTC_DRV_BQ4802 is not set
2738 # CONFIG_RTC_DRV_RP5C01 is not set 3168 # CONFIG_RTC_DRV_RP5C01 is not set
2739 # CONFIG_RTC_DRV_V3020 is not set 3169 # CONFIG_RTC_DRV_V3020 is not set
2740 # CONFIG_RTC_DRV_DS2404 is not set 3170 # CONFIG_RTC_DRV_DS2404 is not set
2741 3171
2742 # 3172 #
2743 # on-CPU RTC drivers 3173 # on-CPU RTC drivers
2744 # 3174 #
2745 # CONFIG_RTC_DRV_IMXDI is not set 3175 # CONFIG_RTC_DRV_IMXDI is not set
2746 # CONFIG_RTC_DRV_MC13XXX is not set 3176 # CONFIG_RTC_DRV_MC13XXX is not set
2747 # CONFIG_RTC_DRV_MXC is not set 3177 # CONFIG_RTC_DRV_MXC is not set
2748 # CONFIG_RTC_DRV_SNVS is not set 3178 # CONFIG_RTC_DRV_SNVS is not set
2749 3179
2750 # 3180 #
2751 # HID Sensor RTC drivers 3181 # HID Sensor RTC drivers
2752 # 3182 #
2753 # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set 3183 # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
2754 CONFIG_DMADEVICES=y 3184 CONFIG_DMADEVICES=y
2755 # CONFIG_DMADEVICES_DEBUG is not set 3185 # CONFIG_DMADEVICES_DEBUG is not set
2756 3186
2757 # 3187 #
2758 # DMA Devices 3188 # DMA Devices
2759 # 3189 #
2760 # CONFIG_DW_DMAC is not set 3190 # CONFIG_DW_DMAC is not set
2761 CONFIG_MX3_IPU=y 3191 CONFIG_MX3_IPU=y
2762 CONFIG_MX3_IPU_IRQS=4 3192 CONFIG_MX3_IPU_IRQS=4
2763 CONFIG_MXC_PXP_V2=y 3193 CONFIG_MXC_PXP_V2=y
2764 CONFIG_MXC_PXP_CLIENT_DEVICE=y 3194 CONFIG_MXC_PXP_CLIENT_DEVICE=y
2765 # CONFIG_TIMB_DMA is not set 3195 # CONFIG_TIMB_DMA is not set
2766 CONFIG_IMX_SDMA=y 3196 CONFIG_IMX_SDMA=y
2767 # CONFIG_IMX_DMA is not set 3197 # CONFIG_IMX_DMA is not set
2768 CONFIG_MXS_DMA=y 3198 CONFIG_MXS_DMA=y
2769 CONFIG_DMA_ENGINE=y 3199 CONFIG_DMA_ENGINE=y
2770 CONFIG_DMA_OF=y 3200 CONFIG_DMA_OF=y
2771 3201
2772 # 3202 #
2773 # DMA Clients 3203 # DMA Clients
2774 # 3204 #
2775 # CONFIG_ASYNC_TX_DMA is not set 3205 # CONFIG_ASYNC_TX_DMA is not set
2776 # CONFIG_DMATEST is not set 3206 # CONFIG_DMATEST is not set
2777 # CONFIG_AUXDISPLAY is not set 3207 # CONFIG_AUXDISPLAY is not set
2778 # CONFIG_UIO is not set 3208 # CONFIG_UIO is not set
2779 # CONFIG_VIRT_DRIVERS is not set 3209 # CONFIG_VIRT_DRIVERS is not set
2780 3210
2781 # 3211 #
2782 # Virtio drivers 3212 # Virtio drivers
2783 # 3213 #
3214 # CONFIG_VIRTIO_PCI is not set
2784 # CONFIG_VIRTIO_MMIO is not set 3215 # CONFIG_VIRTIO_MMIO is not set
2785 3216
2786 # 3217 #
2787 # Microsoft Hyper-V guest support 3218 # Microsoft Hyper-V guest support
2788 # 3219 #
2789 CONFIG_STAGING=y 3220 CONFIG_STAGING=y
3221 # CONFIG_ET131X is not set
2790 # CONFIG_USBIP_CORE is not set 3222 # CONFIG_USBIP_CORE is not set
2791 # CONFIG_W35UND is not set 3223 # CONFIG_W35UND is not set
2792 # CONFIG_PRISM2_USB is not set 3224 # CONFIG_PRISM2_USB is not set
2793 # CONFIG_ECHO is not set 3225 # CONFIG_ECHO is not set
2794 # CONFIG_COMEDI is not set 3226 # CONFIG_COMEDI is not set
2795 # CONFIG_ASUS_OLED is not set 3227 # CONFIG_ASUS_OLED is not set
3228 # CONFIG_R8187SE is not set
3229 # CONFIG_RTL8192U is not set
2796 # CONFIG_RTLLIB is not set 3230 # CONFIG_RTLLIB is not set
2797 # CONFIG_R8712U is not set 3231 # CONFIG_R8712U is not set
2798 # CONFIG_RTS5139 is not set 3232 # CONFIG_RTS5139 is not set
2799 # CONFIG_TRANZPORT is not set 3233 # CONFIG_TRANZPORT is not set
3234 # CONFIG_IDE_PHISON is not set
2800 # CONFIG_LINE6_USB is not set 3235 # CONFIG_LINE6_USB is not set
3236 # CONFIG_VT6655 is not set
2801 # CONFIG_VT6656 is not set 3237 # CONFIG_VT6656 is not set
3238 # CONFIG_DX_SEP is not set
2802 3239
2803 # 3240 #
2804 # IIO staging drivers 3241 # IIO staging drivers
2805 # 3242 #
2806 3243
2807 # 3244 #
2808 # Accelerometers 3245 # Accelerometers
2809 # 3246 #
2810 # CONFIG_ADIS16201 is not set 3247 # CONFIG_ADIS16201 is not set
2811 # CONFIG_ADIS16203 is not set 3248 # CONFIG_ADIS16203 is not set
2812 # CONFIG_ADIS16204 is not set 3249 # CONFIG_ADIS16204 is not set
2813 # CONFIG_ADIS16209 is not set 3250 # CONFIG_ADIS16209 is not set
2814 # CONFIG_ADIS16220 is not set 3251 # CONFIG_ADIS16220 is not set
2815 # CONFIG_ADIS16240 is not set 3252 # CONFIG_ADIS16240 is not set
2816 # CONFIG_LIS3L02DQ is not set 3253 # CONFIG_LIS3L02DQ is not set
2817 3254
2818 # 3255 #
2819 # Analog to digital converters 3256 # Analog to digital converters
2820 # 3257 #
2821 # CONFIG_AD7291 is not set 3258 # CONFIG_AD7291 is not set
2822 # CONFIG_AD7606 is not set 3259 # CONFIG_AD7606 is not set
2823 # CONFIG_AD799X is not set 3260 # CONFIG_AD799X is not set
2824 # CONFIG_AD7780 is not set 3261 # CONFIG_AD7780 is not set
2825 # CONFIG_AD7816 is not set 3262 # CONFIG_AD7816 is not set
2826 # CONFIG_AD7192 is not set 3263 # CONFIG_AD7192 is not set
2827 # CONFIG_AD7280 is not set 3264 # CONFIG_AD7280 is not set
2828 3265
2829 # 3266 #
2830 # Analog digital bi-direction converters 3267 # Analog digital bi-direction converters
2831 # 3268 #
2832 # CONFIG_ADT7316 is not set 3269 # CONFIG_ADT7316 is not set
2833 3270
2834 # 3271 #
2835 # Capacitance to digital converters 3272 # Capacitance to digital converters
2836 # 3273 #
2837 # CONFIG_AD7150 is not set 3274 # CONFIG_AD7150 is not set
2838 # CONFIG_AD7152 is not set 3275 # CONFIG_AD7152 is not set
2839 # CONFIG_AD7746 is not set 3276 # CONFIG_AD7746 is not set
2840 3277
2841 # 3278 #
2842 # Direct Digital Synthesis 3279 # Direct Digital Synthesis
2843 # 3280 #
2844 # CONFIG_AD5930 is not set 3281 # CONFIG_AD5930 is not set
2845 # CONFIG_AD9832 is not set 3282 # CONFIG_AD9832 is not set
2846 # CONFIG_AD9834 is not set 3283 # CONFIG_AD9834 is not set
2847 # CONFIG_AD9850 is not set 3284 # CONFIG_AD9850 is not set
2848 # CONFIG_AD9852 is not set 3285 # CONFIG_AD9852 is not set
2849 # CONFIG_AD9910 is not set 3286 # CONFIG_AD9910 is not set
2850 # CONFIG_AD9951 is not set 3287 # CONFIG_AD9951 is not set
2851 3288
2852 # 3289 #
2853 # Digital gyroscope sensors 3290 # Digital gyroscope sensors
2854 # 3291 #
2855 # CONFIG_ADIS16060 is not set 3292 # CONFIG_ADIS16060 is not set
2856 # CONFIG_ADIS16130 is not set 3293 # CONFIG_ADIS16130 is not set
2857 # CONFIG_ADIS16260 is not set 3294 # CONFIG_ADIS16260 is not set
2858 3295
2859 # 3296 #
2860 # Network Analyzer, Impedance Converters 3297 # Network Analyzer, Impedance Converters
2861 # 3298 #
2862 # CONFIG_AD5933 is not set 3299 # CONFIG_AD5933 is not set
2863 3300
2864 # 3301 #
2865 # Light sensors 3302 # Light sensors
2866 # 3303 #
2867 # CONFIG_SENSORS_ISL29018 is not set 3304 # CONFIG_SENSORS_ISL29018 is not set
2868 # CONFIG_SENSORS_ISL29028 is not set 3305 # CONFIG_SENSORS_ISL29028 is not set
2869 # CONFIG_TSL2583 is not set 3306 # CONFIG_TSL2583 is not set
2870 # CONFIG_TSL2x7x is not set 3307 # CONFIG_TSL2x7x is not set
2871 3308
2872 # 3309 #
2873 # Magnetometer sensors 3310 # Magnetometer sensors
2874 # 3311 #
2875 # CONFIG_SENSORS_HMC5843 is not set 3312 # CONFIG_SENSORS_HMC5843 is not set
2876 3313
2877 # 3314 #
2878 # Active energy metering IC 3315 # Active energy metering IC
2879 # 3316 #
2880 # CONFIG_ADE7753 is not set 3317 # CONFIG_ADE7753 is not set
2881 # CONFIG_ADE7754 is not set 3318 # CONFIG_ADE7754 is not set
2882 # CONFIG_ADE7758 is not set 3319 # CONFIG_ADE7758 is not set
2883 # CONFIG_ADE7759 is not set 3320 # CONFIG_ADE7759 is not set
2884 # CONFIG_ADE7854 is not set 3321 # CONFIG_ADE7854 is not set
2885 3322
2886 # 3323 #
2887 # Resolver to digital converters 3324 # Resolver to digital converters
2888 # 3325 #
2889 # CONFIG_AD2S90 is not set 3326 # CONFIG_AD2S90 is not set
2890 # CONFIG_AD2S1200 is not set 3327 # CONFIG_AD2S1200 is not set
2891 # CONFIG_AD2S1210 is not set 3328 # CONFIG_AD2S1210 is not set
2892 3329
2893 # 3330 #
2894 # Triggers - standalone 3331 # Triggers - standalone
2895 # 3332 #
2896 # CONFIG_IIO_SIMPLE_DUMMY is not set 3333 # CONFIG_IIO_SIMPLE_DUMMY is not set
2897 # CONFIG_ZSMALLOC is not set 3334 # CONFIG_ZSMALLOC is not set
3335 # CONFIG_FB_SM7XX is not set
3336 # CONFIG_CRYSTALHD is not set
3337 # CONFIG_FB_XGI is not set
2898 # CONFIG_USB_ENESTORAGE is not set 3338 # CONFIG_USB_ENESTORAGE is not set
2899 # CONFIG_BCM_WIMAX is not set 3339 # CONFIG_BCM_WIMAX is not set
2900 # CONFIG_FT1000 is not set 3340 # CONFIG_FT1000 is not set
2901 3341
2902 # 3342 #
2903 # Speakup console speech 3343 # Speakup console speech
2904 # 3344 #
2905 # CONFIG_SPEAKUP is not set 3345 # CONFIG_SPEAKUP is not set
2906 # CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set 3346 # CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
2907 # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set 3347 # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
2908 # CONFIG_STAGING_MEDIA is not set 3348 # CONFIG_STAGING_MEDIA is not set
2909 3349
2910 # 3350 #
2911 # Android 3351 # Android
2912 # 3352 #
2913 # CONFIG_ANDROID is not set 3353 # CONFIG_ANDROID is not set
2914 # CONFIG_USB_WPAN_HCD is not set 3354 # CONFIG_USB_WPAN_HCD is not set
2915 # CONFIG_WIMAX_GDM72XX is not set 3355 # CONFIG_WIMAX_GDM72XX is not set
2916 # CONFIG_CSR_WIFI is not set 3356 # CONFIG_CSR_WIFI is not set
3357 CONFIG_NET_VENDOR_SILICOM=y
3358 # CONFIG_SBYPASS is not set
3359 # CONFIG_BPCTL is not set
2917 # CONFIG_CED1401 is not set 3360 # CONFIG_CED1401 is not set
2918 # CONFIG_DRM_IMX is not set 3361 # CONFIG_DRM_IMX is not set
2919 # CONFIG_DGRP is not set 3362 # CONFIG_DGRP is not set
2920 CONFIG_CLKDEV_LOOKUP=y 3363 CONFIG_CLKDEV_LOOKUP=y
2921 CONFIG_HAVE_CLK_PREPARE=y 3364 CONFIG_HAVE_CLK_PREPARE=y
2922 CONFIG_COMMON_CLK=y 3365 CONFIG_COMMON_CLK=y
2923 3366
2924 # 3367 #
2925 # Common Clock Framework 3368 # Common Clock Framework
2926 # 3369 #
2927 CONFIG_COMMON_CLK_DEBUG=y 3370 CONFIG_COMMON_CLK_DEBUG=y
2928 # CONFIG_COMMON_CLK_SI5351 is not set 3371 # CONFIG_COMMON_CLK_SI5351 is not set
2929 3372
2930 # 3373 #
2931 # Hardware Spinlock drivers 3374 # Hardware Spinlock drivers
2932 # 3375 #
2933 CONFIG_CLKSRC_OF=y 3376 CONFIG_CLKSRC_OF=y
2934 CONFIG_CLKSRC_MMIO=y 3377 CONFIG_CLKSRC_MMIO=y
2935 CONFIG_VF_PIT_TIMER=y 3378 CONFIG_VF_PIT_TIMER=y
2936 # CONFIG_MAILBOX is not set 3379 # CONFIG_MAILBOX is not set
2937 # CONFIG_IOMMU_SUPPORT is not set 3380 # CONFIG_IOMMU_SUPPORT is not set
2938 3381
2939 # 3382 #
2940 # Remoteproc drivers 3383 # Remoteproc drivers
2941 # 3384 #
2942 # CONFIG_STE_MODEM_RPROC is not set 3385 # CONFIG_STE_MODEM_RPROC is not set
2943 3386
2944 # 3387 #
2945 # Rpmsg drivers 3388 # Rpmsg drivers
2946 # 3389 #
2947 # CONFIG_PM_DEVFREQ is not set 3390 # CONFIG_PM_DEVFREQ is not set
2948 # CONFIG_EXTCON is not set 3391 # CONFIG_EXTCON is not set
2949 # CONFIG_MEMORY is not set 3392 # CONFIG_MEMORY is not set
2950 CONFIG_IIO=y 3393 CONFIG_IIO=y
2951 # CONFIG_IIO_BUFFER is not set 3394 # CONFIG_IIO_BUFFER is not set
2952 # CONFIG_IIO_TRIGGER is not set 3395 # CONFIG_IIO_TRIGGER is not set
2953 3396
2954 # 3397 #
2955 # Accelerometers 3398 # Accelerometers
2956 # 3399 #
2957 # CONFIG_KXSD9 is not set 3400 # CONFIG_KXSD9 is not set
2958 # CONFIG_IIO_ST_ACCEL_3AXIS is not set 3401 # CONFIG_IIO_ST_ACCEL_3AXIS is not set
2959 3402
2960 # 3403 #
2961 # Analog to digital converters 3404 # Analog to digital converters
2962 # 3405 #
2963 # CONFIG_AD7266 is not set 3406 # CONFIG_AD7266 is not set
2964 # CONFIG_AD7298 is not set 3407 # CONFIG_AD7298 is not set
2965 # CONFIG_AD7923 is not set 3408 # CONFIG_AD7923 is not set
2966 # CONFIG_AD7791 is not set 3409 # CONFIG_AD7791 is not set
2967 # CONFIG_AD7793 is not set 3410 # CONFIG_AD7793 is not set
2968 # CONFIG_AD7476 is not set 3411 # CONFIG_AD7476 is not set
2969 # CONFIG_AD7887 is not set 3412 # CONFIG_AD7887 is not set
2970 # CONFIG_EXYNOS_ADC is not set 3413 # CONFIG_EXYNOS_ADC is not set
2971 # CONFIG_MAX1363 is not set 3414 # CONFIG_MAX1363 is not set
2972 # CONFIG_TI_ADC081C is not set 3415 # CONFIG_TI_ADC081C is not set
2973 CONFIG_VF610_ADC=y 3416 CONFIG_VF610_ADC=y
2974 3417
2975 # 3418 #
2976 # Amplifiers 3419 # Amplifiers
2977 # 3420 #
2978 # CONFIG_AD8366 is not set 3421 # CONFIG_AD8366 is not set
2979 3422
2980 # 3423 #
2981 # Hid Sensor IIO Common 3424 # Hid Sensor IIO Common
2982 # 3425 #
2983 3426
2984 # 3427 #
2985 # Digital to analog converters 3428 # Digital to analog converters
2986 # 3429 #
2987 # CONFIG_AD5064 is not set 3430 # CONFIG_AD5064 is not set
2988 # CONFIG_AD5360 is not set 3431 # CONFIG_AD5360 is not set
2989 # CONFIG_AD5380 is not set 3432 # CONFIG_AD5380 is not set
2990 # CONFIG_AD5421 is not set 3433 # CONFIG_AD5421 is not set
2991 # CONFIG_AD5624R_SPI is not set 3434 # CONFIG_AD5624R_SPI is not set
2992 # CONFIG_AD5446 is not set 3435 # CONFIG_AD5446 is not set
2993 # CONFIG_AD5449 is not set 3436 # CONFIG_AD5449 is not set
2994 # CONFIG_AD5504 is not set 3437 # CONFIG_AD5504 is not set
2995 # CONFIG_AD5755 is not set 3438 # CONFIG_AD5755 is not set
2996 # CONFIG_AD5764 is not set 3439 # CONFIG_AD5764 is not set
2997 # CONFIG_AD5791 is not set 3440 # CONFIG_AD5791 is not set
2998 # CONFIG_AD5686 is not set 3441 # CONFIG_AD5686 is not set
2999 # CONFIG_MAX517 is not set 3442 # CONFIG_MAX517 is not set
3000 # CONFIG_MCP4725 is not set 3443 # CONFIG_MCP4725 is not set
3001 3444
3002 # 3445 #
3003 # Frequency Synthesizers DDS/PLL 3446 # Frequency Synthesizers DDS/PLL
3004 # 3447 #
3005 3448
3006 # 3449 #
3007 # Clock Generator/Distribution 3450 # Clock Generator/Distribution
3008 # 3451 #
3009 # CONFIG_AD9523 is not set 3452 # CONFIG_AD9523 is not set
3010 3453
3011 # 3454 #
3012 # Phase-Locked Loop (PLL) frequency synthesizers 3455 # Phase-Locked Loop (PLL) frequency synthesizers
3013 # 3456 #
3014 # CONFIG_ADF4350 is not set 3457 # CONFIG_ADF4350 is not set
3015 3458
3016 # 3459 #
3017 # Digital gyroscope sensors 3460 # Digital gyroscope sensors
3018 # 3461 #
3019 # CONFIG_ADIS16080 is not set 3462 # CONFIG_ADIS16080 is not set
3020 # CONFIG_ADIS16136 is not set 3463 # CONFIG_ADIS16136 is not set
3021 # CONFIG_ADXRS450 is not set 3464 # CONFIG_ADXRS450 is not set
3022 # CONFIG_IIO_ST_GYRO_3AXIS is not set 3465 # CONFIG_IIO_ST_GYRO_3AXIS is not set
3023 # CONFIG_ITG3200 is not set 3466 # CONFIG_ITG3200 is not set
3024 3467
3025 # 3468 #
3026 # Inertial measurement units 3469 # Inertial measurement units
3027 # 3470 #
3028 # CONFIG_ADIS16400 is not set 3471 # CONFIG_ADIS16400 is not set
3029 # CONFIG_ADIS16480 is not set 3472 # CONFIG_ADIS16480 is not set
3030 # CONFIG_INV_MPU6050_IIO is not set 3473 # CONFIG_INV_MPU6050_IIO is not set
3031 3474
3032 # 3475 #
3033 # Light sensors 3476 # Light sensors
3034 # 3477 #
3035 # CONFIG_ADJD_S311 is not set 3478 # CONFIG_ADJD_S311 is not set
3036 # CONFIG_SENSORS_TSL2563 is not set 3479 # CONFIG_SENSORS_TSL2563 is not set
3037 # CONFIG_VCNL4000 is not set 3480 # CONFIG_VCNL4000 is not set
3038 3481
3039 # 3482 #
3040 # Magnetometer sensors 3483 # Magnetometer sensors
3041 # 3484 #
3042 # CONFIG_AK8975 is not set 3485 # CONFIG_AK8975 is not set
3043 # CONFIG_IIO_ST_MAGN_3AXIS is not set 3486 # CONFIG_IIO_ST_MAGN_3AXIS is not set
3487 # CONFIG_VME_BUS is not set
3044 CONFIG_PWM=y 3488 CONFIG_PWM=y
3045 CONFIG_PWM_IMX=y 3489 CONFIG_PWM_IMX=y
3046 CONFIG_IRQCHIP=y 3490 CONFIG_IRQCHIP=y
3047 CONFIG_ARM_GIC=y 3491 CONFIG_ARM_GIC=y
3048 # CONFIG_IPACK_BUS is not set 3492 # CONFIG_IPACK_BUS is not set
3049 CONFIG_ARCH_HAS_RESET_CONTROLLER=y 3493 CONFIG_ARCH_HAS_RESET_CONTROLLER=y
3050 CONFIG_RESET_CONTROLLER=y 3494 CONFIG_RESET_CONTROLLER=y
3051 CONFIG_RESET_GPIO=y 3495 CONFIG_RESET_GPIO=y
3052 3496
3053 # 3497 #
3054 # File systems 3498 # File systems
3055 # 3499 #
3056 CONFIG_DCACHE_WORD_ACCESS=y 3500 CONFIG_DCACHE_WORD_ACCESS=y
3057 CONFIG_EXT2_FS=y 3501 CONFIG_EXT2_FS=y
3058 CONFIG_EXT2_FS_XATTR=y 3502 CONFIG_EXT2_FS_XATTR=y
3059 CONFIG_EXT2_FS_POSIX_ACL=y 3503 CONFIG_EXT2_FS_POSIX_ACL=y
3060 CONFIG_EXT2_FS_SECURITY=y 3504 CONFIG_EXT2_FS_SECURITY=y
3061 # CONFIG_EXT2_FS_XIP is not set 3505 # CONFIG_EXT2_FS_XIP is not set
3062 CONFIG_EXT3_FS=y 3506 CONFIG_EXT3_FS=y
3063 CONFIG_EXT3_DEFAULTS_TO_ORDERED=y 3507 CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
3064 CONFIG_EXT3_FS_XATTR=y 3508 CONFIG_EXT3_FS_XATTR=y
3065 CONFIG_EXT3_FS_POSIX_ACL=y 3509 CONFIG_EXT3_FS_POSIX_ACL=y
3066 CONFIG_EXT3_FS_SECURITY=y 3510 CONFIG_EXT3_FS_SECURITY=y
3067 CONFIG_EXT4_FS=y 3511 CONFIG_EXT4_FS=y
3068 CONFIG_EXT4_FS_POSIX_ACL=y 3512 CONFIG_EXT4_FS_POSIX_ACL=y
3069 CONFIG_EXT4_FS_SECURITY=y 3513 CONFIG_EXT4_FS_SECURITY=y
3070 # CONFIG_EXT4_DEBUG is not set 3514 # CONFIG_EXT4_DEBUG is not set
3071 CONFIG_JBD=y 3515 CONFIG_JBD=y
3072 # CONFIG_JBD_DEBUG is not set 3516 # CONFIG_JBD_DEBUG is not set
3073 CONFIG_JBD2=y 3517 CONFIG_JBD2=y
3074 # CONFIG_JBD2_DEBUG is not set 3518 # CONFIG_JBD2_DEBUG is not set
3075 CONFIG_FS_MBCACHE=y 3519 CONFIG_FS_MBCACHE=y
3076 # CONFIG_REISERFS_FS is not set 3520 # CONFIG_REISERFS_FS is not set
3077 # CONFIG_JFS_FS is not set 3521 # CONFIG_JFS_FS is not set
3078 # CONFIG_XFS_FS is not set 3522 # CONFIG_XFS_FS is not set
3079 # CONFIG_GFS2_FS is not set 3523 # CONFIG_GFS2_FS is not set
3080 # CONFIG_OCFS2_FS is not set 3524 # CONFIG_OCFS2_FS is not set
3081 # CONFIG_BTRFS_FS is not set 3525 # CONFIG_BTRFS_FS is not set
3082 # CONFIG_NILFS2_FS is not set 3526 # CONFIG_NILFS2_FS is not set
3083 CONFIG_FS_POSIX_ACL=y 3527 CONFIG_FS_POSIX_ACL=y
3084 CONFIG_FILE_LOCKING=y 3528 CONFIG_FILE_LOCKING=y
3085 CONFIG_FSNOTIFY=y 3529 CONFIG_FSNOTIFY=y
3086 CONFIG_DNOTIFY=y 3530 CONFIG_DNOTIFY=y
3087 CONFIG_INOTIFY_USER=y 3531 CONFIG_INOTIFY_USER=y
3088 # CONFIG_FANOTIFY is not set 3532 # CONFIG_FANOTIFY is not set
3089 CONFIG_QUOTA=y 3533 CONFIG_QUOTA=y
3090 CONFIG_QUOTA_NETLINK_INTERFACE=y 3534 CONFIG_QUOTA_NETLINK_INTERFACE=y
3091 # CONFIG_PRINT_QUOTA_WARNING is not set 3535 # CONFIG_PRINT_QUOTA_WARNING is not set
3092 # CONFIG_QUOTA_DEBUG is not set 3536 # CONFIG_QUOTA_DEBUG is not set
3093 # CONFIG_QFMT_V1 is not set 3537 # CONFIG_QFMT_V1 is not set
3094 # CONFIG_QFMT_V2 is not set 3538 # CONFIG_QFMT_V2 is not set
3095 CONFIG_QUOTACTL=y 3539 CONFIG_QUOTACTL=y
3096 CONFIG_AUTOFS4_FS=y 3540 CONFIG_AUTOFS4_FS=y
3097 CONFIG_FUSE_FS=y 3541 CONFIG_FUSE_FS=y
3098 # CONFIG_CUSE is not set 3542 # CONFIG_CUSE is not set
3099 3543
3100 # 3544 #
3101 # Caches 3545 # Caches
3102 # 3546 #
3103 # CONFIG_FSCACHE is not set 3547 # CONFIG_FSCACHE is not set
3104 3548
3105 # 3549 #
3106 # CD-ROM/DVD Filesystems 3550 # CD-ROM/DVD Filesystems
3107 # 3551 #
3108 CONFIG_ISO9660_FS=m 3552 CONFIG_ISO9660_FS=m
3109 CONFIG_JOLIET=y 3553 CONFIG_JOLIET=y
3110 CONFIG_ZISOFS=y 3554 CONFIG_ZISOFS=y
3111 CONFIG_UDF_FS=m 3555 CONFIG_UDF_FS=m
3112 CONFIG_UDF_NLS=y 3556 CONFIG_UDF_NLS=y
3113 3557
3114 # 3558 #
3115 # DOS/FAT/NT Filesystems 3559 # DOS/FAT/NT Filesystems
3116 # 3560 #
3117 CONFIG_FAT_FS=y 3561 CONFIG_FAT_FS=y
3118 CONFIG_MSDOS_FS=m 3562 CONFIG_MSDOS_FS=m
3119 CONFIG_VFAT_FS=y 3563 CONFIG_VFAT_FS=y
3120 CONFIG_FAT_DEFAULT_CODEPAGE=437 3564 CONFIG_FAT_DEFAULT_CODEPAGE=437
3121 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" 3565 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3122 # CONFIG_NTFS_FS is not set 3566 # CONFIG_NTFS_FS is not set
3123 3567
3124 # 3568 #
3125 # Pseudo filesystems 3569 # Pseudo filesystems
3126 # 3570 #
3127 CONFIG_PROC_FS=y 3571 CONFIG_PROC_FS=y
3128 CONFIG_PROC_SYSCTL=y 3572 CONFIG_PROC_SYSCTL=y
3129 CONFIG_PROC_PAGE_MONITOR=y 3573 CONFIG_PROC_PAGE_MONITOR=y
3130 CONFIG_SYSFS=y 3574 CONFIG_SYSFS=y
3131 CONFIG_TMPFS=y 3575 CONFIG_TMPFS=y
3132 # CONFIG_TMPFS_POSIX_ACL is not set 3576 # CONFIG_TMPFS_POSIX_ACL is not set
3133 # CONFIG_TMPFS_XATTR is not set 3577 # CONFIG_TMPFS_XATTR is not set
3134 # CONFIG_HUGETLB_PAGE is not set 3578 # CONFIG_HUGETLB_PAGE is not set
3135 CONFIG_CONFIGFS_FS=m 3579 CONFIG_CONFIGFS_FS=m
3136 CONFIG_MISC_FILESYSTEMS=y 3580 CONFIG_MISC_FILESYSTEMS=y
3137 # CONFIG_ADFS_FS is not set 3581 # CONFIG_ADFS_FS is not set
3138 # CONFIG_AFFS_FS is not set 3582 # CONFIG_AFFS_FS is not set
3139 # CONFIG_ECRYPT_FS is not set 3583 # CONFIG_ECRYPT_FS is not set
3140 # CONFIG_HFS_FS is not set 3584 # CONFIG_HFS_FS is not set
3141 # CONFIG_HFSPLUS_FS is not set 3585 # CONFIG_HFSPLUS_FS is not set
3142 # CONFIG_BEFS_FS is not set 3586 # CONFIG_BEFS_FS is not set
3143 # CONFIG_BFS_FS is not set 3587 # CONFIG_BFS_FS is not set
3144 # CONFIG_EFS_FS is not set 3588 # CONFIG_EFS_FS is not set
3145 CONFIG_JFFS2_FS=y 3589 CONFIG_JFFS2_FS=y
3146 CONFIG_JFFS2_FS_DEBUG=0 3590 CONFIG_JFFS2_FS_DEBUG=0
3147 CONFIG_JFFS2_FS_WRITEBUFFER=y 3591 CONFIG_JFFS2_FS_WRITEBUFFER=y
3148 # CONFIG_JFFS2_FS_WBUF_VERIFY is not set 3592 # CONFIG_JFFS2_FS_WBUF_VERIFY is not set
3149 # CONFIG_JFFS2_SUMMARY is not set 3593 # CONFIG_JFFS2_SUMMARY is not set
3150 # CONFIG_JFFS2_FS_XATTR is not set 3594 # CONFIG_JFFS2_FS_XATTR is not set
3151 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 3595 # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3152 CONFIG_JFFS2_ZLIB=y 3596 CONFIG_JFFS2_ZLIB=y
3153 # CONFIG_JFFS2_LZO is not set 3597 # CONFIG_JFFS2_LZO is not set
3154 CONFIG_JFFS2_RTIME=y 3598 CONFIG_JFFS2_RTIME=y
3155 # CONFIG_JFFS2_RUBIN is not set 3599 # CONFIG_JFFS2_RUBIN is not set
3156 CONFIG_UBIFS_FS=y 3600 CONFIG_UBIFS_FS=y
3157 # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set 3601 # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
3158 CONFIG_UBIFS_FS_LZO=y 3602 CONFIG_UBIFS_FS_LZO=y
3159 CONFIG_UBIFS_FS_ZLIB=y 3603 CONFIG_UBIFS_FS_ZLIB=y
3160 # CONFIG_LOGFS is not set 3604 # CONFIG_LOGFS is not set
3161 # CONFIG_CRAMFS is not set 3605 # CONFIG_CRAMFS is not set
3162 # CONFIG_SQUASHFS is not set 3606 # CONFIG_SQUASHFS is not set
3163 # CONFIG_VXFS_FS is not set 3607 # CONFIG_VXFS_FS is not set
3164 # CONFIG_MINIX_FS is not set 3608 # CONFIG_MINIX_FS is not set
3165 # CONFIG_OMFS_FS is not set 3609 # CONFIG_OMFS_FS is not set
3166 # CONFIG_HPFS_FS is not set 3610 # CONFIG_HPFS_FS is not set
3167 # CONFIG_QNX4FS_FS is not set 3611 # CONFIG_QNX4FS_FS is not set
3168 # CONFIG_QNX6FS_FS is not set 3612 # CONFIG_QNX6FS_FS is not set
3169 # CONFIG_ROMFS_FS is not set 3613 # CONFIG_ROMFS_FS is not set
3170 # CONFIG_PSTORE is not set 3614 # CONFIG_PSTORE is not set
3171 # CONFIG_SYSV_FS is not set 3615 # CONFIG_SYSV_FS is not set
3172 # CONFIG_UFS_FS is not set 3616 # CONFIG_UFS_FS is not set
3173 # CONFIG_F2FS_FS is not set 3617 # CONFIG_F2FS_FS is not set
3174 CONFIG_NETWORK_FILESYSTEMS=y 3618 CONFIG_NETWORK_FILESYSTEMS=y
3175 CONFIG_NFS_FS=y 3619 CONFIG_NFS_FS=y
3176 CONFIG_NFS_V2=y 3620 CONFIG_NFS_V2=y
3177 CONFIG_NFS_V3=y 3621 CONFIG_NFS_V3=y
3178 CONFIG_NFS_V3_ACL=y 3622 CONFIG_NFS_V3_ACL=y
3179 CONFIG_NFS_V4=y 3623 CONFIG_NFS_V4=y
3180 # CONFIG_NFS_SWAP is not set 3624 # CONFIG_NFS_SWAP is not set
3181 # CONFIG_NFS_V4_1 is not set 3625 # CONFIG_NFS_V4_1 is not set
3182 CONFIG_ROOT_NFS=y 3626 CONFIG_ROOT_NFS=y
3183 # CONFIG_NFS_USE_LEGACY_DNS is not set 3627 # CONFIG_NFS_USE_LEGACY_DNS is not set
3184 CONFIG_NFS_USE_KERNEL_DNS=y 3628 CONFIG_NFS_USE_KERNEL_DNS=y
3185 # CONFIG_NFSD is not set 3629 # CONFIG_NFSD is not set
3186 CONFIG_LOCKD=y 3630 CONFIG_LOCKD=y
3187 CONFIG_LOCKD_V4=y 3631 CONFIG_LOCKD_V4=y
3188 CONFIG_NFS_ACL_SUPPORT=y 3632 CONFIG_NFS_ACL_SUPPORT=y
3189 CONFIG_NFS_COMMON=y 3633 CONFIG_NFS_COMMON=y
3190 CONFIG_SUNRPC=y 3634 CONFIG_SUNRPC=y
3191 CONFIG_SUNRPC_GSS=y 3635 CONFIG_SUNRPC_GSS=y
3192 # CONFIG_SUNRPC_DEBUG is not set 3636 # CONFIG_SUNRPC_DEBUG is not set
3193 # CONFIG_CEPH_FS is not set 3637 # CONFIG_CEPH_FS is not set
3194 # CONFIG_CIFS is not set 3638 # CONFIG_CIFS is not set
3195 # CONFIG_NCP_FS is not set 3639 # CONFIG_NCP_FS is not set
3196 # CONFIG_CODA_FS is not set 3640 # CONFIG_CODA_FS is not set
3197 # CONFIG_AFS_FS is not set 3641 # CONFIG_AFS_FS is not set
3198 CONFIG_NLS=y 3642 CONFIG_NLS=y
3199 CONFIG_NLS_DEFAULT="cp437" 3643 CONFIG_NLS_DEFAULT="cp437"
3200 CONFIG_NLS_CODEPAGE_437=y 3644 CONFIG_NLS_CODEPAGE_437=y
3201 # CONFIG_NLS_CODEPAGE_737 is not set 3645 # CONFIG_NLS_CODEPAGE_737 is not set
3202 # CONFIG_NLS_CODEPAGE_775 is not set 3646 # CONFIG_NLS_CODEPAGE_775 is not set
3203 # CONFIG_NLS_CODEPAGE_850 is not set 3647 # CONFIG_NLS_CODEPAGE_850 is not set
3204 # CONFIG_NLS_CODEPAGE_852 is not set 3648 # CONFIG_NLS_CODEPAGE_852 is not set
3205 # CONFIG_NLS_CODEPAGE_855 is not set 3649 # CONFIG_NLS_CODEPAGE_855 is not set
3206 # CONFIG_NLS_CODEPAGE_857 is not set 3650 # CONFIG_NLS_CODEPAGE_857 is not set
3207 # CONFIG_NLS_CODEPAGE_860 is not set 3651 # CONFIG_NLS_CODEPAGE_860 is not set
3208 # CONFIG_NLS_CODEPAGE_861 is not set 3652 # CONFIG_NLS_CODEPAGE_861 is not set
3209 # CONFIG_NLS_CODEPAGE_862 is not set 3653 # CONFIG_NLS_CODEPAGE_862 is not set
3210 # CONFIG_NLS_CODEPAGE_863 is not set 3654 # CONFIG_NLS_CODEPAGE_863 is not set
3211 # CONFIG_NLS_CODEPAGE_864 is not set 3655 # CONFIG_NLS_CODEPAGE_864 is not set
3212 # CONFIG_NLS_CODEPAGE_865 is not set 3656 # CONFIG_NLS_CODEPAGE_865 is not set
3213 # CONFIG_NLS_CODEPAGE_866 is not set 3657 # CONFIG_NLS_CODEPAGE_866 is not set
3214 # CONFIG_NLS_CODEPAGE_869 is not set 3658 # CONFIG_NLS_CODEPAGE_869 is not set
3215 # CONFIG_NLS_CODEPAGE_936 is not set 3659 # CONFIG_NLS_CODEPAGE_936 is not set
3216 # CONFIG_NLS_CODEPAGE_950 is not set 3660 # CONFIG_NLS_CODEPAGE_950 is not set
3217 # CONFIG_NLS_CODEPAGE_932 is not set 3661 # CONFIG_NLS_CODEPAGE_932 is not set
3218 # CONFIG_NLS_CODEPAGE_949 is not set 3662 # CONFIG_NLS_CODEPAGE_949 is not set
3219 # CONFIG_NLS_CODEPAGE_874 is not set 3663 # CONFIG_NLS_CODEPAGE_874 is not set
3220 # CONFIG_NLS_ISO8859_8 is not set 3664 # CONFIG_NLS_ISO8859_8 is not set
3221 # CONFIG_NLS_CODEPAGE_1250 is not set 3665 # CONFIG_NLS_CODEPAGE_1250 is not set
3222 # CONFIG_NLS_CODEPAGE_1251 is not set 3666 # CONFIG_NLS_CODEPAGE_1251 is not set
3223 CONFIG_NLS_ASCII=y 3667 CONFIG_NLS_ASCII=y
3224 CONFIG_NLS_ISO8859_1=y 3668 CONFIG_NLS_ISO8859_1=y
3225 # CONFIG_NLS_ISO8859_2 is not set 3669 # CONFIG_NLS_ISO8859_2 is not set
3226 # CONFIG_NLS_ISO8859_3 is not set 3670 # CONFIG_NLS_ISO8859_3 is not set
3227 # CONFIG_NLS_ISO8859_4 is not set 3671 # CONFIG_NLS_ISO8859_4 is not set
3228 # CONFIG_NLS_ISO8859_5 is not set 3672 # CONFIG_NLS_ISO8859_5 is not set
3229 # CONFIG_NLS_ISO8859_6 is not set 3673 # CONFIG_NLS_ISO8859_6 is not set
3230 # CONFIG_NLS_ISO8859_7 is not set 3674 # CONFIG_NLS_ISO8859_7 is not set
3231 # CONFIG_NLS_ISO8859_9 is not set 3675 # CONFIG_NLS_ISO8859_9 is not set
3232 # CONFIG_NLS_ISO8859_13 is not set 3676 # CONFIG_NLS_ISO8859_13 is not set
3233 # CONFIG_NLS_ISO8859_14 is not set 3677 # CONFIG_NLS_ISO8859_14 is not set
3234 CONFIG_NLS_ISO8859_15=m 3678 CONFIG_NLS_ISO8859_15=m
3235 # CONFIG_NLS_KOI8_R is not set 3679 # CONFIG_NLS_KOI8_R is not set
3236 # CONFIG_NLS_KOI8_U is not set 3680 # CONFIG_NLS_KOI8_U is not set
3237 # CONFIG_NLS_MAC_ROMAN is not set 3681 # CONFIG_NLS_MAC_ROMAN is not set
3238 # CONFIG_NLS_MAC_CELTIC is not set 3682 # CONFIG_NLS_MAC_CELTIC is not set
3239 # CONFIG_NLS_MAC_CENTEURO is not set 3683 # CONFIG_NLS_MAC_CENTEURO is not set
3240 # CONFIG_NLS_MAC_CROATIAN is not set 3684 # CONFIG_NLS_MAC_CROATIAN is not set
3241 # CONFIG_NLS_MAC_CYRILLIC is not set 3685 # CONFIG_NLS_MAC_CYRILLIC is not set
3242 # CONFIG_NLS_MAC_GAELIC is not set 3686 # CONFIG_NLS_MAC_GAELIC is not set
3243 # CONFIG_NLS_MAC_GREEK is not set 3687 # CONFIG_NLS_MAC_GREEK is not set
3244 # CONFIG_NLS_MAC_ICELAND is not set 3688 # CONFIG_NLS_MAC_ICELAND is not set
3245 # CONFIG_NLS_MAC_INUIT is not set 3689 # CONFIG_NLS_MAC_INUIT is not set
3246 # CONFIG_NLS_MAC_ROMANIAN is not set 3690 # CONFIG_NLS_MAC_ROMANIAN is not set
3247 # CONFIG_NLS_MAC_TURKISH is not set 3691 # CONFIG_NLS_MAC_TURKISH is not set
3248 CONFIG_NLS_UTF8=y 3692 CONFIG_NLS_UTF8=y
3249 # CONFIG_DLM is not set 3693 # CONFIG_DLM is not set
3250 3694
3251 # 3695 #
3252 # Kernel hacking 3696 # Kernel hacking
3253 # 3697 #
3254 # CONFIG_PRINTK_TIME is not set 3698 # CONFIG_PRINTK_TIME is not set
3255 CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 3699 CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
3256 CONFIG_ENABLE_WARN_DEPRECATED=y 3700 CONFIG_ENABLE_WARN_DEPRECATED=y
3257 CONFIG_ENABLE_MUST_CHECK=y 3701 CONFIG_ENABLE_MUST_CHECK=y
3258 CONFIG_FRAME_WARN=1024 3702 CONFIG_FRAME_WARN=1024
3259 CONFIG_MAGIC_SYSRQ=y 3703 CONFIG_MAGIC_SYSRQ=y
3260 # CONFIG_STRIP_ASM_SYMS is not set 3704 # CONFIG_STRIP_ASM_SYMS is not set
3261 # CONFIG_READABLE_ASM is not set 3705 # CONFIG_READABLE_ASM is not set
3262 # CONFIG_UNUSED_SYMBOLS is not set 3706 # CONFIG_UNUSED_SYMBOLS is not set
3263 CONFIG_DEBUG_FS=y 3707 CONFIG_DEBUG_FS=y
3264 # CONFIG_HEADERS_CHECK is not set 3708 # CONFIG_HEADERS_CHECK is not set
3265 # CONFIG_DEBUG_SECTION_MISMATCH is not set 3709 # CONFIG_DEBUG_SECTION_MISMATCH is not set
3266 CONFIG_DEBUG_KERNEL=y 3710 CONFIG_DEBUG_KERNEL=y
3267 # CONFIG_DEBUG_SHIRQ is not set 3711 # CONFIG_DEBUG_SHIRQ is not set
3268 # CONFIG_LOCKUP_DETECTOR is not set 3712 # CONFIG_LOCKUP_DETECTOR is not set
3269 # CONFIG_PANIC_ON_OOPS is not set 3713 # CONFIG_PANIC_ON_OOPS is not set
3270 CONFIG_PANIC_ON_OOPS_VALUE=0 3714 CONFIG_PANIC_ON_OOPS_VALUE=0
3271 # CONFIG_DETECT_HUNG_TASK is not set 3715 # CONFIG_DETECT_HUNG_TASK is not set
3272 # CONFIG_SCHED_DEBUG is not set 3716 # CONFIG_SCHED_DEBUG is not set
3273 # CONFIG_SCHEDSTATS is not set 3717 # CONFIG_SCHEDSTATS is not set
3274 # CONFIG_TIMER_STATS is not set 3718 # CONFIG_TIMER_STATS is not set
3275 # CONFIG_DEBUG_OBJECTS is not set 3719 # CONFIG_DEBUG_OBJECTS is not set
3276 # CONFIG_SLUB_STATS is not set 3720 # CONFIG_SLUB_STATS is not set
3277 CONFIG_HAVE_DEBUG_KMEMLEAK=y 3721 CONFIG_HAVE_DEBUG_KMEMLEAK=y
3278 # CONFIG_DEBUG_KMEMLEAK is not set 3722 # CONFIG_DEBUG_KMEMLEAK is not set
3279 CONFIG_DEBUG_PREEMPT=y 3723 CONFIG_DEBUG_PREEMPT=y
3280 # CONFIG_DEBUG_RT_MUTEXES is not set 3724 # CONFIG_DEBUG_RT_MUTEXES is not set
3281 # CONFIG_RT_MUTEX_TESTER is not set 3725 # CONFIG_RT_MUTEX_TESTER is not set
3282 # CONFIG_DEBUG_SPINLOCK is not set 3726 # CONFIG_DEBUG_SPINLOCK is not set
3283 # CONFIG_DEBUG_MUTEXES is not set 3727 # CONFIG_DEBUG_MUTEXES is not set
3284 # CONFIG_DEBUG_LOCK_ALLOC is not set 3728 # CONFIG_DEBUG_LOCK_ALLOC is not set
3285 # CONFIG_PROVE_LOCKING is not set 3729 # CONFIG_PROVE_LOCKING is not set
3286 # CONFIG_LOCK_STAT is not set 3730 # CONFIG_LOCK_STAT is not set
3287 # CONFIG_DEBUG_ATOMIC_SLEEP is not set 3731 # CONFIG_DEBUG_ATOMIC_SLEEP is not set
3288 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 3732 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
3289 # CONFIG_DEBUG_STACK_USAGE is not set 3733 # CONFIG_DEBUG_STACK_USAGE is not set
3290 # CONFIG_DEBUG_KOBJECT is not set 3734 # CONFIG_DEBUG_KOBJECT is not set
3291 # CONFIG_DEBUG_HIGHMEM is not set 3735 # CONFIG_DEBUG_HIGHMEM is not set
3292 # CONFIG_DEBUG_BUGVERBOSE is not set 3736 # CONFIG_DEBUG_BUGVERBOSE is not set
3293 # CONFIG_DEBUG_INFO is not set 3737 # CONFIG_DEBUG_INFO is not set
3294 # CONFIG_DEBUG_VM is not set 3738 # CONFIG_DEBUG_VM is not set
3295 # CONFIG_DEBUG_WRITECOUNT is not set 3739 # CONFIG_DEBUG_WRITECOUNT is not set
3296 # CONFIG_DEBUG_MEMORY_INIT is not set 3740 # CONFIG_DEBUG_MEMORY_INIT is not set
3297 # CONFIG_DEBUG_LIST is not set 3741 # CONFIG_DEBUG_LIST is not set
3298 # CONFIG_TEST_LIST_SORT is not set 3742 # CONFIG_TEST_LIST_SORT is not set
3299 # CONFIG_DEBUG_SG is not set 3743 # CONFIG_DEBUG_SG is not set
3300 # CONFIG_DEBUG_NOTIFIERS is not set 3744 # CONFIG_DEBUG_NOTIFIERS is not set
3301 # CONFIG_DEBUG_CREDENTIALS is not set 3745 # CONFIG_DEBUG_CREDENTIALS is not set
3302 # CONFIG_BOOT_PRINTK_DELAY is not set 3746 # CONFIG_BOOT_PRINTK_DELAY is not set
3303 3747
3304 # 3748 #
3305 # RCU Debugging 3749 # RCU Debugging
3306 # 3750 #
3307 # CONFIG_PROVE_RCU_DELAY is not set 3751 # CONFIG_PROVE_RCU_DELAY is not set
3308 # CONFIG_SPARSE_RCU_POINTER is not set 3752 # CONFIG_SPARSE_RCU_POINTER is not set
3309 # CONFIG_RCU_TORTURE_TEST is not set 3753 # CONFIG_RCU_TORTURE_TEST is not set
3310 CONFIG_RCU_CPU_STALL_TIMEOUT=21 3754 CONFIG_RCU_CPU_STALL_TIMEOUT=21
3311 CONFIG_RCU_CPU_STALL_VERBOSE=y 3755 CONFIG_RCU_CPU_STALL_VERBOSE=y
3312 # CONFIG_RCU_CPU_STALL_INFO is not set 3756 # CONFIG_RCU_CPU_STALL_INFO is not set
3313 # CONFIG_RCU_TRACE is not set 3757 # CONFIG_RCU_TRACE is not set
3314 # CONFIG_BACKTRACE_SELF_TEST is not set 3758 # CONFIG_BACKTRACE_SELF_TEST is not set
3315 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 3759 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
3316 # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set 3760 # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
3317 # CONFIG_DEBUG_PER_CPU_MAPS is not set 3761 # CONFIG_DEBUG_PER_CPU_MAPS is not set
3318 # CONFIG_LKDTM is not set 3762 # CONFIG_LKDTM is not set
3319 # CONFIG_NOTIFIER_ERROR_INJECTION is not set 3763 # CONFIG_NOTIFIER_ERROR_INJECTION is not set
3320 # CONFIG_FAULT_INJECTION is not set 3764 # CONFIG_FAULT_INJECTION is not set
3321 # CONFIG_DEBUG_PAGEALLOC is not set 3765 # CONFIG_DEBUG_PAGEALLOC is not set
3322 CONFIG_HAVE_FUNCTION_TRACER=y 3766 CONFIG_HAVE_FUNCTION_TRACER=y
3323 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y 3767 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
3324 CONFIG_HAVE_DYNAMIC_FTRACE=y 3768 CONFIG_HAVE_DYNAMIC_FTRACE=y
3325 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 3769 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
3326 CONFIG_HAVE_SYSCALL_TRACEPOINTS=y 3770 CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
3327 CONFIG_HAVE_C_RECORDMCOUNT=y 3771 CONFIG_HAVE_C_RECORDMCOUNT=y
3328 CONFIG_TRACING_SUPPORT=y 3772 CONFIG_TRACING_SUPPORT=y
3329 # CONFIG_FTRACE is not set 3773 # CONFIG_FTRACE is not set
3330 # CONFIG_RBTREE_TEST is not set 3774 # CONFIG_RBTREE_TEST is not set
3331 # CONFIG_INTERVAL_TREE_TEST is not set 3775 # CONFIG_INTERVAL_TREE_TEST is not set
3332 # CONFIG_DYNAMIC_DEBUG is not set 3776 # CONFIG_DYNAMIC_DEBUG is not set
3333 # CONFIG_DMA_API_DEBUG is not set 3777 # CONFIG_DMA_API_DEBUG is not set
3334 # CONFIG_ATOMIC64_SELFTEST is not set 3778 # CONFIG_ATOMIC64_SELFTEST is not set
3335 # CONFIG_SAMPLES is not set 3779 # CONFIG_SAMPLES is not set
3336 CONFIG_HAVE_ARCH_KGDB=y 3780 CONFIG_HAVE_ARCH_KGDB=y
3337 # CONFIG_KGDB is not set 3781 # CONFIG_KGDB is not set
3338 # CONFIG_TEST_STRING_HELPERS is not set 3782 # CONFIG_TEST_STRING_HELPERS is not set
3339 # CONFIG_TEST_KSTRTOX is not set 3783 # CONFIG_TEST_KSTRTOX is not set
3340 # CONFIG_STRICT_DEVMEM is not set 3784 # CONFIG_STRICT_DEVMEM is not set
3341 CONFIG_ARM_UNWIND=y 3785 CONFIG_ARM_UNWIND=y
3342 # CONFIG_DEBUG_USER is not set 3786 # CONFIG_DEBUG_USER is not set
3343 # CONFIG_DEBUG_LL is not set 3787 # CONFIG_DEBUG_LL is not set
3344 CONFIG_DEBUG_IMX_UART_PORT=1 3788 CONFIG_DEBUG_IMX_UART_PORT=1
3345 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" 3789 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
3346 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" 3790 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
3347 # CONFIG_PID_IN_CONTEXTIDR is not set 3791 # CONFIG_PID_IN_CONTEXTIDR is not set
3348 3792
3349 # 3793 #
3350 # Security options 3794 # Security options
3351 # 3795 #
3352 CONFIG_KEYS=y 3796 CONFIG_KEYS=y
3353 # CONFIG_ENCRYPTED_KEYS is not set 3797 # CONFIG_ENCRYPTED_KEYS is not set
3354 # CONFIG_KEYS_DEBUG_PROC_KEYS is not set 3798 # CONFIG_KEYS_DEBUG_PROC_KEYS is not set
3355 # CONFIG_SECURITY_DMESG_RESTRICT is not set 3799 # CONFIG_SECURITY_DMESG_RESTRICT is not set
3356 # CONFIG_SECURITY is not set 3800 # CONFIG_SECURITY is not set
3357 CONFIG_SECURITYFS=y 3801 CONFIG_SECURITYFS=y
3358 CONFIG_DEFAULT_SECURITY_DAC=y 3802 CONFIG_DEFAULT_SECURITY_DAC=y
3359 CONFIG_DEFAULT_SECURITY="" 3803 CONFIG_DEFAULT_SECURITY=""
3360 CONFIG_CRYPTO=y 3804 CONFIG_CRYPTO=y
3361 3805
3362 # 3806 #
3363 # Crypto core or helper 3807 # Crypto core or helper
3364 # 3808 #
3365 CONFIG_CRYPTO_ALGAPI=y 3809 CONFIG_CRYPTO_ALGAPI=y
3366 CONFIG_CRYPTO_ALGAPI2=y 3810 CONFIG_CRYPTO_ALGAPI2=y
3367 CONFIG_CRYPTO_AEAD=y 3811 CONFIG_CRYPTO_AEAD=y
3368 CONFIG_CRYPTO_AEAD2=y 3812 CONFIG_CRYPTO_AEAD2=y
3369 CONFIG_CRYPTO_BLKCIPHER=y 3813 CONFIG_CRYPTO_BLKCIPHER=y
3370 CONFIG_CRYPTO_BLKCIPHER2=y 3814 CONFIG_CRYPTO_BLKCIPHER2=y
3371 CONFIG_CRYPTO_HASH=y 3815 CONFIG_CRYPTO_HASH=y
3372 CONFIG_CRYPTO_HASH2=y 3816 CONFIG_CRYPTO_HASH2=y
3373 CONFIG_CRYPTO_RNG=y 3817 CONFIG_CRYPTO_RNG=y
3374 CONFIG_CRYPTO_RNG2=y 3818 CONFIG_CRYPTO_RNG2=y
3375 CONFIG_CRYPTO_PCOMP2=y 3819 CONFIG_CRYPTO_PCOMP2=y
3376 CONFIG_CRYPTO_MANAGER=y 3820 CONFIG_CRYPTO_MANAGER=y
3377 CONFIG_CRYPTO_MANAGER2=y 3821 CONFIG_CRYPTO_MANAGER2=y
3378 CONFIG_CRYPTO_USER=y 3822 CONFIG_CRYPTO_USER=y
3379 CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y 3823 CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
3380 CONFIG_CRYPTO_GF128MUL=y 3824 CONFIG_CRYPTO_GF128MUL=y
3381 CONFIG_CRYPTO_NULL=y 3825 CONFIG_CRYPTO_NULL=y
3382 # CONFIG_CRYPTO_PCRYPT is not set 3826 # CONFIG_CRYPTO_PCRYPT is not set
3383 CONFIG_CRYPTO_WORKQUEUE=y 3827 CONFIG_CRYPTO_WORKQUEUE=y
3384 # CONFIG_CRYPTO_CRYPTD is not set 3828 # CONFIG_CRYPTO_CRYPTD is not set
3385 CONFIG_CRYPTO_AUTHENC=y 3829 CONFIG_CRYPTO_AUTHENC=y
3386 CONFIG_CRYPTO_TEST=m 3830 CONFIG_CRYPTO_TEST=m
3387 3831
3388 # 3832 #
3389 # Authenticated Encryption with Associated Data 3833 # Authenticated Encryption with Associated Data
3390 # 3834 #
3391 CONFIG_CRYPTO_CCM=y 3835 CONFIG_CRYPTO_CCM=y
3392 CONFIG_CRYPTO_GCM=y 3836 CONFIG_CRYPTO_GCM=y
3393 CONFIG_CRYPTO_SEQIV=y 3837 CONFIG_CRYPTO_SEQIV=y
3394 3838
3395 # 3839 #
3396 # Block modes 3840 # Block modes
3397 # 3841 #
3398 CONFIG_CRYPTO_CBC=y 3842 CONFIG_CRYPTO_CBC=y
3399 CONFIG_CRYPTO_CTR=y 3843 CONFIG_CRYPTO_CTR=y
3400 CONFIG_CRYPTO_CTS=y 3844 CONFIG_CRYPTO_CTS=y
3401 CONFIG_CRYPTO_ECB=y 3845 CONFIG_CRYPTO_ECB=y
3402 CONFIG_CRYPTO_LRW=y 3846 CONFIG_CRYPTO_LRW=y
3403 # CONFIG_CRYPTO_PCBC is not set 3847 # CONFIG_CRYPTO_PCBC is not set
3404 CONFIG_CRYPTO_XTS=y 3848 CONFIG_CRYPTO_XTS=y
3405 3849
3406 # 3850 #
3407 # Hash modes 3851 # Hash modes
3408 # 3852 #
3409 # CONFIG_CRYPTO_CMAC is not set 3853 # CONFIG_CRYPTO_CMAC is not set
3410 # CONFIG_CRYPTO_HMAC is not set 3854 # CONFIG_CRYPTO_HMAC is not set
3411 # CONFIG_CRYPTO_XCBC is not set 3855 # CONFIG_CRYPTO_XCBC is not set
3412 # CONFIG_CRYPTO_VMAC is not set 3856 # CONFIG_CRYPTO_VMAC is not set
3413 3857
3414 # 3858 #
3415 # Digest 3859 # Digest
3416 # 3860 #
3417 CONFIG_CRYPTO_CRC32C=y 3861 CONFIG_CRYPTO_CRC32C=y
3418 # CONFIG_CRYPTO_CRC32 is not set 3862 # CONFIG_CRYPTO_CRC32 is not set
3419 CONFIG_CRYPTO_GHASH=y 3863 CONFIG_CRYPTO_GHASH=y
3420 CONFIG_CRYPTO_MD4=y 3864 CONFIG_CRYPTO_MD4=y
3421 CONFIG_CRYPTO_MD5=y 3865 CONFIG_CRYPTO_MD5=y
3422 CONFIG_CRYPTO_MICHAEL_MIC=y 3866 CONFIG_CRYPTO_MICHAEL_MIC=y
3423 CONFIG_CRYPTO_RMD128=y 3867 CONFIG_CRYPTO_RMD128=y
3424 CONFIG_CRYPTO_RMD160=y 3868 CONFIG_CRYPTO_RMD160=y
3425 CONFIG_CRYPTO_RMD256=y 3869 CONFIG_CRYPTO_RMD256=y
3426 CONFIG_CRYPTO_RMD320=y 3870 CONFIG_CRYPTO_RMD320=y
3427 CONFIG_CRYPTO_SHA1=y 3871 CONFIG_CRYPTO_SHA1=y
3428 # CONFIG_CRYPTO_SHA1_ARM is not set 3872 # CONFIG_CRYPTO_SHA1_ARM is not set
3429 CONFIG_CRYPTO_SHA256=y 3873 CONFIG_CRYPTO_SHA256=y
3430 CONFIG_CRYPTO_SHA512=y 3874 CONFIG_CRYPTO_SHA512=y
3431 CONFIG_CRYPTO_TGR192=y 3875 CONFIG_CRYPTO_TGR192=y
3432 CONFIG_CRYPTO_WP512=y 3876 CONFIG_CRYPTO_WP512=y
3433 3877
3434 # 3878 #
3435 # Ciphers 3879 # Ciphers
3436 # 3880 #
3437 CONFIG_CRYPTO_AES=y 3881 CONFIG_CRYPTO_AES=y
3438 # CONFIG_CRYPTO_AES_ARM is not set 3882 # CONFIG_CRYPTO_AES_ARM is not set
3439 # CONFIG_CRYPTO_ANUBIS is not set 3883 # CONFIG_CRYPTO_ANUBIS is not set
3440 CONFIG_CRYPTO_ARC4=y 3884 CONFIG_CRYPTO_ARC4=y
3441 CONFIG_CRYPTO_BLOWFISH=y 3885 CONFIG_CRYPTO_BLOWFISH=y
3442 CONFIG_CRYPTO_BLOWFISH_COMMON=y 3886 CONFIG_CRYPTO_BLOWFISH_COMMON=y
3443 CONFIG_CRYPTO_CAMELLIA=y 3887 CONFIG_CRYPTO_CAMELLIA=y
3444 # CONFIG_CRYPTO_CAST5 is not set 3888 # CONFIG_CRYPTO_CAST5 is not set
3445 # CONFIG_CRYPTO_CAST6 is not set 3889 # CONFIG_CRYPTO_CAST6 is not set
3446 CONFIG_CRYPTO_DES=y 3890 CONFIG_CRYPTO_DES=y
3447 # CONFIG_CRYPTO_FCRYPT is not set 3891 # CONFIG_CRYPTO_FCRYPT is not set
3448 # CONFIG_CRYPTO_KHAZAD is not set 3892 # CONFIG_CRYPTO_KHAZAD is not set
3449 # CONFIG_CRYPTO_SALSA20 is not set 3893 # CONFIG_CRYPTO_SALSA20 is not set
3450 # CONFIG_CRYPTO_SEED is not set 3894 # CONFIG_CRYPTO_SEED is not set
3451 # CONFIG_CRYPTO_SERPENT is not set 3895 # CONFIG_CRYPTO_SERPENT is not set
3452 # CONFIG_CRYPTO_TEA is not set 3896 # CONFIG_CRYPTO_TEA is not set
3453 CONFIG_CRYPTO_TWOFISH=y 3897 CONFIG_CRYPTO_TWOFISH=y
3454 CONFIG_CRYPTO_TWOFISH_COMMON=y 3898 CONFIG_CRYPTO_TWOFISH_COMMON=y
3455 3899
3456 # 3900 #
3457 # Compression 3901 # Compression
3458 # 3902 #
3459 CONFIG_CRYPTO_DEFLATE=y 3903 CONFIG_CRYPTO_DEFLATE=y
3460 # CONFIG_CRYPTO_ZLIB is not set 3904 # CONFIG_CRYPTO_ZLIB is not set
3461 CONFIG_CRYPTO_LZO=y 3905 CONFIG_CRYPTO_LZO=y
3462 3906
3463 # 3907 #
3464 # Random Number Generation 3908 # Random Number Generation
3465 # 3909 #
3466 # CONFIG_CRYPTO_ANSI_CPRNG is not set 3910 # CONFIG_CRYPTO_ANSI_CPRNG is not set
3467 # CONFIG_CRYPTO_USER_API_HASH is not set 3911 # CONFIG_CRYPTO_USER_API_HASH is not set
3468 # CONFIG_CRYPTO_USER_API_SKCIPHER is not set 3912 # CONFIG_CRYPTO_USER_API_SKCIPHER is not set
3469 CONFIG_CRYPTO_HW=y 3913 CONFIG_CRYPTO_HW=y
3914 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
3470 CONFIG_CRYPTO_DEV_FSL_CAAM=y 3915 CONFIG_CRYPTO_DEV_FSL_CAAM=y
3471 CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y 3916 CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
3472 CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 3917 CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
3473 # CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set 3918 # CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
3474 CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y 3919 CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
3475 CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y 3920 CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
3476 CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y 3921 CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
3477 # CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set 3922 # CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
3478 CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y 3923 CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
3479 CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7 3924 CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
3480 CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y 3925 CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
3481 CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y 3926 CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
3482 # CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set 3927 # CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
3483 # CONFIG_ASYMMETRIC_KEY_TYPE is not set 3928 # CONFIG_ASYMMETRIC_KEY_TYPE is not set
3484 # CONFIG_BINARY_PRINTF is not set 3929 # CONFIG_BINARY_PRINTF is not set
3485 3930
3486 # 3931 #
3487 # Library routines 3932 # Library routines
3488 # 3933 #
3489 CONFIG_BITREVERSE=y 3934 CONFIG_BITREVERSE=y
3490 CONFIG_RATIONAL=y 3935 CONFIG_RATIONAL=y
3491 CONFIG_GENERIC_STRNCPY_FROM_USER=y 3936 CONFIG_GENERIC_STRNCPY_FROM_USER=y
3492 CONFIG_GENERIC_STRNLEN_USER=y 3937 CONFIG_GENERIC_STRNLEN_USER=y
3493 CONFIG_GENERIC_PCI_IOMAP=y 3938 CONFIG_GENERIC_PCI_IOMAP=y
3494 CONFIG_GENERIC_IO=y 3939 CONFIG_GENERIC_IO=y
3495 CONFIG_STMP_DEVICE=y 3940 CONFIG_STMP_DEVICE=y
3496 CONFIG_CRC_CCITT=m 3941 CONFIG_CRC_CCITT=m
3497 CONFIG_CRC16=y 3942 CONFIG_CRC16=y
3498 CONFIG_CRC_T10DIF=y 3943 CONFIG_CRC_T10DIF=y
3499 CONFIG_CRC_ITU_T=m 3944 CONFIG_CRC_ITU_T=m
3500 CONFIG_CRC32=y 3945 CONFIG_CRC32=y
3501 # CONFIG_CRC32_SELFTEST is not set 3946 # CONFIG_CRC32_SELFTEST is not set
3502 CONFIG_CRC32_SLICEBY8=y 3947 CONFIG_CRC32_SLICEBY8=y
3503 # CONFIG_CRC32_SLICEBY4 is not set 3948 # CONFIG_CRC32_SLICEBY4 is not set
3504 # CONFIG_CRC32_SARWATE is not set 3949 # CONFIG_CRC32_SARWATE is not set
3505 # CONFIG_CRC32_BIT is not set 3950 # CONFIG_CRC32_BIT is not set
3506 CONFIG_CRC7=m 3951 CONFIG_CRC7=m
3507 CONFIG_LIBCRC32C=m 3952 CONFIG_LIBCRC32C=m
3508 # CONFIG_CRC8 is not set 3953 # CONFIG_CRC8 is not set
3509 CONFIG_ZLIB_INFLATE=y 3954 CONFIG_ZLIB_INFLATE=y
3510 CONFIG_ZLIB_DEFLATE=y 3955 CONFIG_ZLIB_DEFLATE=y
3511 CONFIG_LZO_COMPRESS=y 3956 CONFIG_LZO_COMPRESS=y
3512 CONFIG_LZO_DECOMPRESS=y 3957 CONFIG_LZO_DECOMPRESS=y
3513 # CONFIG_XZ_DEC is not set 3958 # CONFIG_XZ_DEC is not set
3514 # CONFIG_XZ_DEC_BCJ is not set 3959 # CONFIG_XZ_DEC_BCJ is not set
3515 CONFIG_DECOMPRESS_GZIP=y 3960 CONFIG_DECOMPRESS_GZIP=y
3516 CONFIG_GENERIC_ALLOCATOR=y 3961 CONFIG_GENERIC_ALLOCATOR=y
3517 CONFIG_HAS_IOMEM=y 3962 CONFIG_HAS_IOMEM=y
3518 CONFIG_HAS_IOPORT=y 3963 CONFIG_HAS_IOPORT=y
3519 CONFIG_HAS_DMA=y 3964 CONFIG_HAS_DMA=y
3520 CONFIG_CPU_RMAP=y 3965 CONFIG_CPU_RMAP=y
3521 CONFIG_DQL=y 3966 CONFIG_DQL=y
3522 CONFIG_NLATTR=y 3967 CONFIG_NLATTR=y
3523 CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y 3968 CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
3524 CONFIG_AVERAGE=y 3969 CONFIG_AVERAGE=y
3525 # CONFIG_CORDIC is not set 3970 # CONFIG_CORDIC is not set
3526 # CONFIG_DDR is not set 3971 # CONFIG_DDR is not set
arch/arm/mach-imx/clk-imx6q.c
Diff comments   View file @ 8f7b130
1 /* 1 /*
2 * Copyright 2011-2015 Freescale Semiconductor, Inc. 2 * Copyright 2011-2015 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd. 3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License 6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations: 7 * Version 2 or later at the following locations:
8 * 8 *
9 * http://www.opensource.org/licenses/gpl-license.html 9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13 #include <linux/init.h> 13 #include <linux/init.h>
14 #include <linux/types.h> 14 #include <linux/types.h>
15 #include <linux/clk.h> 15 #include <linux/clk.h>
16 #include <linux/clkdev.h> 16 #include <linux/clkdev.h>
17 #include <linux/err.h> 17 #include <linux/err.h>
18 #include <linux/io.h> 18 #include <linux/io.h>
19 #include <linux/of.h> 19 #include <linux/of.h>
20 #include <linux/of_address.h> 20 #include <linux/of_address.h>
21 #include <linux/of_irq.h> 21 #include <linux/of_irq.h>
22 22
23 #include "clk.h" 23 #include "clk.h"
24 #include "common.h" 24 #include "common.h"
25 #include "hardware.h" 25 #include "hardware.h"
26 26
27 #define CCM_CCGR_OFFSET(index) (index * 2) 27 #define CCM_CCGR_OFFSET(index) (index * 2)
28 28
29 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; 29 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
30 static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; 30 static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
31 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; 31 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
32 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; 32 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
33 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 33 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
34 static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; 34 static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
35 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; 35 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
36 static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; 36 static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
37 static const char *axi_sels[] = { "periph", "axi_alt_sel", }; 37 static const char *axi_sels[] = { "periph", "axi_alt_sel", };
38 static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; 38 static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
39 static const char *gpu_axi_sels[] = { "axi", "ahb", }; 39 static const char *gpu_axi_sels[] = { "axi", "ahb", };
40 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; 40 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
41 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi_podf", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; 41 static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi_podf", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
42 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi_podf", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; 42 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi_podf", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
43 static const char *ipu_sels[] = { "mmdc_ch0_axi_podf", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; 43 static const char *ipu_sels[] = { "mmdc_ch0_axi_podf", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
44 static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; 44 static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
45 static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; 45 static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
46 static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; 46 static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
47 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi_podf", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 47 static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi_podf", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
48 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 48 static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
49 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 49 static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
50 static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 50 static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
51 static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; 51 static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
52 static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; 52 static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
53 static const char *pcie_axi_sels[] = { "axi", "ahb", }; 53 static const char *pcie_axi_sels[] = { "axi", "ahb", };
54 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; 54 static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
55 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 55 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
56 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; 56 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
57 static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; 57 static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
58 static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 58 static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
59 static const char *vdo_axi_sels[] = { "axi", "ahb", }; 59 static const char *vdo_axi_sels[] = { "axi", "ahb", };
60 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; 60 static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
61 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 61 static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
62 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", 62 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
63 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; 63 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
64 static const char *cko2_sels[] = { 64 static const char *cko2_sels[] = {
65 "mmdc_ch0_axi_podf", "mmdc_ch1_axi", "usdhc4", "usdhc1", 65 "mmdc_ch0_axi_podf", "mmdc_ch1_axi", "usdhc4", "usdhc1",
66 "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", 66 "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
67 "usdhc3", "dummy", "arm", "ipu1", 67 "usdhc3", "dummy", "arm", "ipu1",
68 "ipu2", "vdo_axi", "osc", "gpu2d_core", 68 "ipu2", "vdo_axi", "osc", "gpu2d_core",
69 "gpu3d_core", "usdhc2", "ssi1", "ssi2", 69 "gpu3d_core", "usdhc2", "ssi1", "ssi2",
70 "ssi3", "gpu3d_shader", "vpu_axi", "can_root", 70 "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
71 "ldb_di0", "ldb_di1", "esai_extal", "eim_slow", 71 "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
72 "uart_serial", "spdif", "spdif1", "hsi_tx", 72 "uart_serial", "spdif", "spdif1", "hsi_tx",
73 }; 73 };
74 static const char *cko_sels[] = { "cko1", "cko2", }; 74 static const char *cko_sels[] = { "cko1", "cko2", };
75 static const char *lvds_sels[] = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", 75 static const char *lvds_sels[] = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
76 "dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", }; 76 "dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", };
77 static const char *pll_av_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; 77 static const char *pll_av_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
78 static void __iomem *anatop_base; 78 static void __iomem *anatop_base;
79 static void __iomem *ccm_base; 79 static void __iomem *ccm_base;
80 80
81 static u32 share_count_esai; 81 static u32 share_count_esai;
82 static u32 share_count_ssi1; 82 static u32 share_count_ssi1;
83 static u32 share_count_ssi2; 83 static u32 share_count_ssi2;
84 static u32 share_count_ssi3; 84 static u32 share_count_ssi3;
85 85
86 enum mx6q_clks { 86 enum mx6q_clks {
87 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, 87 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
88 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m, 88 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
89 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw, 89 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
90 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel, 90 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
91 esai_sel, spdif1_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel, 91 esai_sel, spdif1_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
92 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel, 92 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
93 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel, 93 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
94 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, 94 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
95 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel, 95 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
96 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel, 96 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
97 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2, 97 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
98 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf, 98 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
99 spdif1_pred, spdif1_podf, spdif_pred, spdif_podf, can_root, ecspi_root, 99 spdif1_pred, spdif1_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
100 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf, 100 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
101 ldb_di0_podf_unused, ldb_di1_podf_unused, ipu1_di0_pre, ipu1_di1_pre, 101 ldb_di0_podf_unused, ldb_di1_podf_unused, ipu1_di0_pre, ipu1_di1_pre,
102 ipu2_di0_pre, ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, 102 ipu2_di0_pre, ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf,
103 ssi2_pred, ssi2_podf, ssi3_pred, ssi3_podf, uart_serial_podf, 103 ssi2_pred, ssi2_podf, ssi3_pred, ssi3_podf, uart_serial_podf,
104 usdhc1_podf, usdhc2_podf, usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, 104 usdhc1_podf, usdhc2_podf, usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf,
105 emi_podf, emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf, 105 emi_podf, emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
106 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc_gate, can1_ipg, can1_serial, 106 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc_gate, can1_ipg, can1_serial,
107 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet, 107 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
108 esai_extal, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, 108 esai_extal, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
109 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, 109 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
110 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, 110 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
111 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, 111 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
112 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, 112 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
113 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, 113 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
114 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, 114 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
115 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 115 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
116 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 116 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
117 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 117 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
118 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, 118 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
119 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, gpt_3m, video_27m, 119 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, gpt_3m, video_27m,
120 ldb_di0_div_7, ldb_di1_div_7, ldb_di0_div_sel, ldb_di1_div_sel, 120 ldb_di0_div_7, ldb_di1_div_7, ldb_di0_div_sel, ldb_di1_div_sel,
121 pll4_audio_div, lvds1_sel, lvds1_in, lvds1_out, caam_mem, caam_aclk, 121 pll4_audio_div, lvds1_sel, lvds1_in, lvds1_out, caam_mem, caam_aclk,
122 caam_ipg, epit1, epit2, tzasc2, pll4_sel, lvds2_sel, lvds2_in, lvds2_out, 122 caam_ipg, epit1, epit2, tzasc2, pll4_sel, lvds2_sel, lvds2_in, lvds2_out,
123 anaclk1, anaclk2, spdif1, asrc_ipg, asrc_mem, esai_ipg, esai_mem, 123 anaclk1, anaclk2, spdif1, asrc_ipg, asrc_mem, esai_ipg, esai_mem,
124 axi_alt_sel, dcic1, dcic2, clk_max 124 axi_alt_sel, dcic1, dcic2, clk_max
125 }; 125 };
126 126
127 static struct clk *clk[clk_max]; 127 static struct clk *clk[clk_max];
128 static struct clk_onecell_data clk_data; 128 static struct clk_onecell_data clk_data;
129 129
130 static enum mx6q_clks const clks_init_on[] __initconst = { 130 static enum mx6q_clks const clks_init_on[] __initconst = {
131 mmdc_ch0_axi, rom, arm, ocram, 131 mmdc_ch0_axi, rom, arm, ocram,
132 }; 132 };
133 133
134 static struct clk_div_table clk_enet_ref_table[] = { 134 static struct clk_div_table clk_enet_ref_table[] = {
135 { .val = 0, .div = 20, }, 135 { .val = 0, .div = 20, },
136 { .val = 1, .div = 10, }, 136 { .val = 1, .div = 10, },
137 { .val = 2, .div = 5, }, 137 { .val = 2, .div = 5, },
138 { .val = 3, .div = 4, }, 138 { .val = 3, .div = 4, },
139 }; 139 };
140 140
141 static struct clk_div_table post_div_table[] = { 141 static struct clk_div_table post_div_table[] = {
142 { .val = 2, .div = 1, }, 142 { .val = 2, .div = 1, },
143 { .val = 1, .div = 2, }, 143 { .val = 1, .div = 2, },
144 { .val = 0, .div = 4, }, 144 { .val = 0, .div = 4, },
145 { } 145 { }
146 }; 146 };
147 147
148 static struct clk_div_table video_div_table[] = { 148 static struct clk_div_table video_div_table[] = {
149 { .val = 0, .div = 1, }, 149 { .val = 0, .div = 1, },
150 { .val = 1, .div = 2, }, 150 { .val = 1, .div = 2, },
151 { .val = 2, .div = 1, }, 151 { .val = 2, .div = 1, },
152 { .val = 3, .div = 4, }, 152 { .val = 3, .div = 4, },
153 { } 153 { }
154 }; 154 };
155 155
156 /* 156 /*
157 * Kernel parameter 'ldb_di_clk_sel' is used to select parent of ldb_di_clk, 157 * Kernel parameter 'ldb_di_clk_sel' is used to select parent of ldb_di_clk,
158 * among the following clocks. 158 * among the following clocks.
159 * 'pll5_video_div' 159 * 'pll5_video_div'
160 * 'pll2_pfd0_352m' 160 * 'pll2_pfd0_352m'
161 * 'pll2_pfd2_396m' 161 * 'pll2_pfd2_396m'
162 * 'mmdc_ch1_axi' 162 * 'mmdc_ch1_axi'
163 * 'pll3_usb_otg' 163 * 'pll3_usb_otg'
164 * Example format: ldb_di_clk_sel=pll5_video_div 164 * Example format: ldb_di_clk_sel=pll5_video_div
165 * If the kernel parameter is absent or invalid, pll2_pfd0_352m will be 165 * If the kernel parameter is absent or invalid, pll2_pfd0_352m will be
166 * selected by default. 166 * selected by default.
167 */ 167 */
168 static int ldb_di_sel = 1; 168 static int ldb_di_sel = 1;
169 169
170 static int __init get_ldb_di_parent(char *p) 170 static int __init get_ldb_di_parent(char *p)
171 { 171 {
172 int i; 172 int i;
173 173
174 for (i = 0; i < ARRAY_SIZE(ldb_di_sels); i++) { 174 for (i = 0; i < ARRAY_SIZE(ldb_di_sels); i++) {
175 if (strcmp(p, ldb_di_sels[i]) == 0) { 175 if (strcmp(p, ldb_di_sels[i]) == 0) {
176 ldb_di_sel = i; 176 ldb_di_sel = i;
177 break; 177 break;
178 } 178 }
179 } 179 }
180 180
181 return 0; 181 return 0;
182 } 182 }
183 early_param("ldb_di_clk_sel", get_ldb_di_parent); 183 early_param("ldb_di_clk_sel", get_ldb_di_parent);
184 184
185 static void init_ldb_clks(void) 185 static void init_ldb_clks(void)
186 { 186 {
187 u32 reg; 187 u32 reg;
188 188
189 /* 189 /*
190 * Need to follow a strict procedure when changing the LDB 190 * Need to follow a strict procedure when changing the LDB
191 * clock, else we can introduce a glitch. Things to keep in 191 * clock, else we can introduce a glitch. Things to keep in
192 * mind: 192 * mind:
193 * 1. The current and new parent clocks must be disabled. 193 * 1. The current and new parent clocks must be disabled.
194 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has 194 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
195 * no CG bit. 195 * no CG bit.
196 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux 196 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
197 * the top four options are in one mux and the PLL3 option along 197 * the top four options are in one mux and the PLL3 option along
198 * with another option is in the second mux. There is third mux 198 * with another option is in the second mux. There is third mux
199 * used to decide between the first and second mux. 199 * used to decide between the first and second mux.
200 * The code below switches the parent to the bottom mux first 200 * The code below switches the parent to the bottom mux first
201 * and then manipulates the top mux. This ensures that no glitch 201 * and then manipulates the top mux. This ensures that no glitch
202 * will enter the divider. 202 * will enter the divider.
203 * 203 *
204 * Need to disable MMDC_CH1 clock manually as there is no CG bit 204 * Need to disable MMDC_CH1 clock manually as there is no CG bit
205 * for this clock. The only way to disable this clock is to move 205 * for this clock. The only way to disable this clock is to move
206 * it topll3_sw_clk and then to disable pll3_sw_clk 206 * it topll3_sw_clk and then to disable pll3_sw_clk
207 * Make sure periph2_clk2_sel is set to pll3_sw_clk 207 * Make sure periph2_clk2_sel is set to pll3_sw_clk
208 */ 208 */
209 reg = readl_relaxed(ccm_base + 0x18); 209 reg = readl_relaxed(ccm_base + 0x18);
210 reg &= ~(1 << 20); 210 reg &= ~(1 << 20);
211 writel_relaxed(reg, ccm_base + 0x18); 211 writel_relaxed(reg, ccm_base + 0x18);
212 212
213 /* 213 /*
214 * Set MMDC_CH1 mask bit. 214 * Set MMDC_CH1 mask bit.
215 */ 215 */
216 reg = readl_relaxed(ccm_base + 0x4); 216 reg = readl_relaxed(ccm_base + 0x4);
217 reg |= 1 << 16; 217 reg |= 1 << 16;
218 writel_relaxed(reg, ccm_base + 0x4); 218 writel_relaxed(reg, ccm_base + 0x4);
219 219
220 /* 220 /*
221 * Set the periph2_clk_sel to the top mux so that 221 * Set the periph2_clk_sel to the top mux so that
222 * mmdc_ch1 is from pll3_sw_clk. 222 * mmdc_ch1 is from pll3_sw_clk.
223 */ 223 */
224 reg = readl_relaxed(ccm_base + 0x14); 224 reg = readl_relaxed(ccm_base + 0x14);
225 reg |= 1 << 26; 225 reg |= 1 << 26;
226 writel_relaxed(reg, ccm_base + 0x14); 226 writel_relaxed(reg, ccm_base + 0x14);
227 227
228 /* 228 /*
229 * Wait for the clock switch. 229 * Wait for the clock switch.
230 */ 230 */
231 while (readl_relaxed(ccm_base + 0x48)) 231 while (readl_relaxed(ccm_base + 0x48))
232 ; 232 ;
233 233
234 /* 234 /*
235 * Disable pll3_sw_clk by selecting the bypass clock source. 235 * Disable pll3_sw_clk by selecting the bypass clock source.
236 */ 236 */
237 reg = readl_relaxed(ccm_base + 0xc); 237 reg = readl_relaxed(ccm_base + 0xc);
238 reg |= 1 << 0; 238 reg |= 1 << 0;
239 writel_relaxed(reg, ccm_base + 0xc); 239 writel_relaxed(reg, ccm_base + 0xc);
240 240
241 /* 241 /*
242 * Set the ldb_di0_clk and ldb_di1_clk to 111b. 242 * Set the ldb_di0_clk and ldb_di1_clk to 111b.
243 */ 243 */
244 reg = readl_relaxed(ccm_base + 0x2c); 244 reg = readl_relaxed(ccm_base + 0x2c);
245 reg |= ((7 << 9) | (7 << 12)); 245 reg |= ((7 << 9) | (7 << 12));
246 writel_relaxed(reg, ccm_base + 0x2c); 246 writel_relaxed(reg, ccm_base + 0x2c);
247 247
248 /* 248 /*
249 * Set the ldb_di0_clk and ldb_di1_clk to 100b. 249 * Set the ldb_di0_clk and ldb_di1_clk to 100b.
250 */ 250 */
251 reg = readl_relaxed(ccm_base + 0x2c); 251 reg = readl_relaxed(ccm_base + 0x2c);
252 reg &= ~((7 << 9) | (7 << 12)); 252 reg &= ~((7 << 9) | (7 << 12));
253 reg |= ((4 << 9) | (4 << 12)); 253 reg |= ((4 << 9) | (4 << 12));
254 writel_relaxed(reg, ccm_base + 0x2c); 254 writel_relaxed(reg, ccm_base + 0x2c);
255 255
256 /* 256 /*
257 * Perform the LDB parent clock switch. 257 * Perform the LDB parent clock switch.
258 */ 258 */
259 reg = readl_relaxed(ccm_base + 0x2c); 259 reg = readl_relaxed(ccm_base + 0x2c);
260 reg &= ~((7 << 9) | (7 << 12)); 260 reg &= ~((7 << 9) | (7 << 12));
261 reg |= ((ldb_di_sel << 9) | (ldb_di_sel << 12)); 261 reg |= ((ldb_di_sel << 9) | (ldb_di_sel << 12));
262 writel_relaxed(reg, ccm_base + 0x2c); 262 writel_relaxed(reg, ccm_base + 0x2c);
263 263
264 /* 264 /*
265 * Unbypass pll3_sw_clk. 265 * Unbypass pll3_sw_clk.
266 */ 266 */
267 reg = readl_relaxed(ccm_base + 0xc); 267 reg = readl_relaxed(ccm_base + 0xc);
268 reg &= ~(1 << 0); 268 reg &= ~(1 << 0);
269 writel_relaxed(reg, ccm_base + 0xc); 269 writel_relaxed(reg, ccm_base + 0xc);
270 270
271 /* 271 /*
272 * Set the periph2_clk_sel back to the bottom mux so that 272 * Set the periph2_clk_sel back to the bottom mux so that
273 * mmdc_ch1 is from its original parent. 273 * mmdc_ch1 is from its original parent.
274 */ 274 */
275 reg = readl_relaxed(ccm_base + 0x14); 275 reg = readl_relaxed(ccm_base + 0x14);
276 reg &= ~(1 << 26); 276 reg &= ~(1 << 26);
277 writel_relaxed(reg, ccm_base + 0x14); 277 writel_relaxed(reg, ccm_base + 0x14);
278 278
279 /* 279 /*
280 * Wait for the clock switch. 280 * Wait for the clock switch.
281 */ 281 */
282 while (readl_relaxed(ccm_base + 0x48)) 282 while (readl_relaxed(ccm_base + 0x48))
283 ; 283 ;
284 284
285 /* 285 /*
286 * Clear MMDC_CH1 mask bit. 286 * Clear MMDC_CH1 mask bit.
287 */ 287 */
288 reg = readl_relaxed(ccm_base + 0x4); 288 reg = readl_relaxed(ccm_base + 0x4);
289 reg &= ~(1 << 16); 289 reg &= ~(1 << 16);
290 writel_relaxed(reg, ccm_base + 0x4); 290 writel_relaxed(reg, ccm_base + 0x4);
291 291
292 } 292 }
293 293
294 static void __init imx6q_clocks_init(struct device_node *ccm_node) 294 static void __init imx6q_clocks_init(struct device_node *ccm_node)
295 { 295 {
296 struct device_node *np; 296 struct device_node *np;
297 void __iomem *base; 297 void __iomem *base;
298 int i, irq; 298 int i, irq;
299 u32 reg; 299 u32 reg;
300 300
301 clk[dummy] = imx_clk_fixed("dummy", 0); 301 clk[dummy] = imx_clk_fixed("dummy", 0);
302 clk[ckil] = imx_obtain_fixed_clock("ckil", 0); 302 clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
303 clk[ckih] = imx_obtain_fixed_clock("ckih1", 0); 303 clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
304 clk[osc] = imx_obtain_fixed_clock("osc", 0); 304 clk[osc] = imx_obtain_fixed_clock("osc", 0);
305 /* Clock source from external clock via ANACLK1/2 PADs */ 305 /* Clock source from external clock via ANACLK1/2 PADs */
306 clk[anaclk1] = imx_obtain_fixed_clock("anaclk1", 0); 306 clk[anaclk1] = imx_obtain_fixed_clock("anaclk1", 0);
307 clk[anaclk2] = imx_obtain_fixed_clock("anaclk2", 0); 307 clk[anaclk2] = imx_obtain_fixed_clock("anaclk2", 0);
308 308
309 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 309 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
310 anatop_base = base = of_iomap(np, 0); 310 anatop_base = base = of_iomap(np, 0);
311 WARN_ON(!base); 311 WARN_ON(!base);
312 312
313 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ 313 /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
314 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { 314 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
315 post_div_table[1].div = 1; 315 post_div_table[1].div = 1;
316 post_div_table[2].div = 1; 316 post_div_table[2].div = 1;
317 video_div_table[1].div = 1; 317 video_div_table[1].div = 1;
318 video_div_table[2].div = 1; 318 video_div_table[2].div = 1;
319 }; 319 };
320 320
321 /* type name parent_name base div_mask */ 321 /* type name parent_name base div_mask */
322 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f, false); 322 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f, false);
323 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1, false); 323 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1, false);
324 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3, false); 324 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3, false);
325 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "pll4_sel", base + 0x70, 0x7f, false); 325 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "pll4_sel", base + 0x70, 0x7f, false);
326 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f, false); 326 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f, false);
327 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3, false); 327 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3, false);
328 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3, false); 328 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3, false);
329 329
330 /* name reg shift width parent_names num_parents */ 330 /* name reg shift width parent_names num_parents */
331 clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 331 clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
332 clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); 332 clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
333 clk[pll4_sel] = imx_clk_mux("pll4_sel", base + 0x70, 14, 2, pll_av_sels, ARRAY_SIZE(pll_av_sels)); 333 clk[pll4_sel] = imx_clk_mux("pll4_sel", base + 0x70, 14, 2, pll_av_sels, ARRAY_SIZE(pll_av_sels));
334 334
335 /* 335 /*
336 * Bit 20 is the reserved and read-only bit, we do this only for: 336 * Bit 20 is the reserved and read-only bit, we do this only for:
337 * - Do nothing for usbphy clk_enable/disable 337 * - Do nothing for usbphy clk_enable/disable
338 * - Keep refcount when do usbphy clk_enable/disable, in that case, 338 * - Keep refcount when do usbphy clk_enable/disable, in that case,
339 * the clk framework may need to enable/disable usbphy's parent 339 * the clk framework may need to enable/disable usbphy's parent
340 */ 340 */
341 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); 341 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
342 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); 342 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
343 343
344 /* 344 /*
345 * usbphy*_gate needs to be on after system boots up, and software 345 * usbphy*_gate needs to be on after system boots up, and software
346 * never needs to control it anymore. 346 * never needs to control it anymore.
347 */ 347 */
348 clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); 348 clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
349 clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); 349 clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
350 350
351 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); 351 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
352 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); 352 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
353 /* NOTICE: The gate of the lvds1/2 in/out is used to select the clk direction */ 353 /* NOTICE: The gate of the lvds1/2 in/out is used to select the clk direction */
354 clk[lvds1_in] = imx_clk_gate("lvds1_in", "anaclk1", base + 0x160, 12); 354 clk[lvds1_in] = imx_clk_gate("lvds1_in", "anaclk1", base + 0x160, 12);
355 clk[lvds2_in] = imx_clk_gate("lvds2_in", "anaclk2", base + 0x160, 13); 355 clk[lvds2_in] = imx_clk_gate("lvds2_in", "anaclk2", base + 0x160, 13);
356 clk[lvds1_out] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10); 356 clk[lvds1_out] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
357 clk[lvds2_out] = imx_clk_gate("lvds2_out", "lvds2_sel", base + 0x160, 11); 357 clk[lvds2_out] = imx_clk_gate("lvds2_out", "lvds2_sel", base + 0x160, 11);
358 358
359 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); 359 clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
360 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); 360 clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
361 361
362 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, 362 clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
363 base + 0xe0, 0, 2, 0, clk_enet_ref_table, 363 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
364 &imx_ccm_lock); 364 &imx_ccm_lock);
365 365
366 /* name parent_name reg idx */ 366 /* name parent_name reg idx */
367 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); 367 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
368 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); 368 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
369 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); 369 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
370 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); 370 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
371 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); 371 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
372 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); 372 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
373 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); 373 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
374 374
375 /* name parent_name mult div */ 375 /* name parent_name mult div */
376 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); 376 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
377 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); 377 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
378 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); 378 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
379 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); 379 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
380 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); 380 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
381 clk[gpt_3m] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); 381 clk[gpt_3m] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
382 clk[video_27m] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); 382 clk[video_27m] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
383 if (cpu_is_imx6dl()) { 383 if (cpu_is_imx6dl()) {
384 clk[gpu2d_axi] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); 384 clk[gpu2d_axi] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
385 clk[gpu3d_axi] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); 385 clk[gpu3d_axi] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
386 } 386 }
387 387
388 clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); 388 clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
389 clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); 389 clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
390 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 390 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
391 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 391 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
392 392
393 np = ccm_node; 393 np = ccm_node;
394 ccm_base = base = of_iomap(np, 0); 394 ccm_base = base = of_iomap(np, 0);
395 WARN_ON(!base); 395 WARN_ON(!base);
396 imx6_pm_set_ccm_base(base); 396 imx6_pm_set_ccm_base(base);
397 397
398 /* name reg shift width parent_names num_parents */ 398 /* name reg shift width parent_names num_parents */
399 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); 399 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
400 clk[pll1_sw] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); 400 clk[pll1_sw] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
401 clk[periph_pre] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 401 clk[periph_pre] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
402 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); 402 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
403 clk[periph_clk2_sel] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 403 clk[periph_clk2_sel] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
404 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); 404 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
405 clk[axi_alt_sel] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); 405 clk[axi_alt_sel] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
406 clk[axi_sel] = imx_clk_mux_glitchless("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels)); 406 clk[axi_sel] = imx_clk_mux_glitchless("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels));
407 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); 407 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
408 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); 408 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
409 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); 409 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
410 if (cpu_is_imx6q()) { 410 if (cpu_is_imx6q()) {
411 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 411 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
412 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); 412 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
413 } 413 }
414 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); 414 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
415 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); 415 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
416 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); 416 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
417 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 417 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
418 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); 418 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
419 clk[ldb_di0_div_sel] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT); 419 clk[ldb_di0_div_sel] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
420 clk[ldb_di1_div_sel] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT); 420 clk[ldb_di1_div_sel] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
421 clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 421 clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
422 clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 422 clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
423 clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 423 clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
424 clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); 424 clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
425 clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); 425 clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
426 clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); 426 clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
427 clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); 427 clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
428 clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); 428 clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
429 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); 429 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
430 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); 430 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
431 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 431 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
432 clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 432 clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
433 clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); 433 clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
434 clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 434 clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
435 clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 435 clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
436 clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 436 clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
437 clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); 437 clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
438 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 438 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
439 clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup); 439 clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
440 clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup); 440 clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
441 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 441 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
442 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 442 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
443 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 443 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
444 clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); 444 clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
445 clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); 445 clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
446 446
447 /* name reg shift width busy: reg, shift parent_names num_parents */ 447 /* name reg shift width busy: reg, shift parent_names num_parents */
448 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); 448 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
449 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); 449 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
450 450
451 /* name parent_name reg shift width */ 451 /* name parent_name reg shift width */
452 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); 452 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
453 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); 453 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
454 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); 454 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
455 clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); 455 clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
456 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); 456 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
457 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); 457 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
458 clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3); 458 clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3);
459 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3); 459 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3);
460 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); 460 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
461 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); 461 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
462 clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); 462 clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
463 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); 463 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
464 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); 464 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
465 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); 465 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
466 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); 466 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
467 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); 467 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
468 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); 468 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
469 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", ldb_di_sels[ldb_di_sel], 2, 7); 469 clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", ldb_di_sels[ldb_di_sel], 2, 7);
470 clk[ldb_di0_div_7] = imx_clk_fixed_factor("ldb_di0_div_7", ldb_di_sels[ldb_di_sel], 1, 7); 470 clk[ldb_di0_div_7] = imx_clk_fixed_factor("ldb_di0_div_7", ldb_di_sels[ldb_di_sel], 1, 7);
471 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", ldb_di_sels[ldb_di_sel], 2, 7); 471 clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", ldb_di_sels[ldb_di_sel], 2, 7);
472 clk[ldb_di1_div_7] = imx_clk_fixed_factor("ldb_di1_div_7", ldb_di_sels[ldb_di_sel], 1, 7); 472 clk[ldb_di1_div_7] = imx_clk_fixed_factor("ldb_di1_div_7", ldb_di_sels[ldb_di_sel], 1, 7);
473 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); 473 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
474 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); 474 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
475 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); 475 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
476 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); 476 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
477 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); 477 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
478 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); 478 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
479 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); 479 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
480 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); 480 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
481 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); 481 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
482 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); 482 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
483 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); 483 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
484 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); 484 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
485 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); 485 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
486 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); 486 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
487 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); 487 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
488 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 488 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
489 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 489 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
490 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 490 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
491 clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); 491 clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
492 clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); 492 clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
493 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 493 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
494 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 494 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
495 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); 495 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
496 496
497 /* name parent_name reg shift width busy: reg, shift */ 497 /* name parent_name reg shift width busy: reg, shift */
498 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); 498 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
499 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); 499 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
500 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); 500 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
501 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); 501 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
502 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); 502 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
503 503
504 /* name parent_name reg shift */ 504 /* name parent_name reg shift */
505 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); 505 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
506 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ahb", base + 0x68, 6); 506 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ahb", base + 0x68, 6);
507 clk[asrc_ipg] = imx_clk_fixed_factor("asrc_ipg", "asrc_gate", 1, 1); 507 clk[asrc_ipg] = imx_clk_fixed_factor("asrc_ipg", "asrc_gate", 1, 1);
508 clk[asrc_mem] = imx_clk_fixed_factor("asrc_mem", "asrc_gate", 1, 1); 508 clk[asrc_mem] = imx_clk_fixed_factor("asrc_mem", "asrc_gate", 1, 1);
509 clk[caam_mem] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); 509 clk[caam_mem] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
510 clk[caam_aclk] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); 510 clk[caam_aclk] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
511 clk[caam_ipg] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); 511 clk[caam_ipg] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
512 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); 512 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
513 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); 513 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
514 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); 514 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
515 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); 515 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
516 clk[dcic1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24); 516 clk[dcic1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
517 clk[dcic2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26); 517 clk[dcic2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
518 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); 518 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
519 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); 519 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
520 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); 520 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
521 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); 521 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
522 if (cpu_is_imx6dl()) 522 if (cpu_is_imx6dl())
523 /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */ 523 /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
524 clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); 524 clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
525 else 525 else
526 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 526 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
527 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 527 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
528 clk[epit1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12); 528 clk[epit1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12);
529 clk[epit2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14); 529 clk[epit2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14);
530 clk[esai_extal] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); 530 clk[esai_extal] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
531 clk[esai_ipg] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); 531 clk[esai_ipg] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
532 clk[esai_mem] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); 532 clk[esai_mem] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
533 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 533 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
534 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 534 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
535 if (cpu_is_imx6dl()) 535 if (cpu_is_imx6dl())
536 /* 536 /*
537 * The multiplexer and divider of imx6q clock gpu3d_shader get 537 * The multiplexer and divider of imx6q clock gpu3d_shader get
538 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. 538 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
539 */ 539 */
540 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); 540 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
541 else 541 else
542 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 542 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
543 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 543 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
544 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 544 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
545 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); 545 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
546 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); 546 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
547 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); 547 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
548 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); 548 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
549 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); 549 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
550 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); 550 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
551 clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24); 551 clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24);
552 clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); 552 clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
553 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); 553 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
554 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); 554 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
555 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); 555 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
556 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); 556 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
557 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); 557 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
558 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 558 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
559 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12); 559 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
560 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_div_sel", base + 0x74, 14); 560 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_div_sel", base + 0x74, 14);
561 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); 561 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
562 if (cpu_is_imx6dl()) 562 if (cpu_is_imx6dl())
563 /* 563 /*
564 * The multiplexer and divider of the imx6q clock gpu2d get 564 * The multiplexer and divider of the imx6q clock gpu2d get
565 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. 565 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
566 */ 566 */
567 clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); 567 clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
568 else 568 else
569 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); 569 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
570 clk[ocram] = imx_clk_busy_gate("ocram", "ahb", base + 0x74, 28); 570 clk[ocram] = imx_clk_busy_gate("ocram", "ahb", base + 0x74, 28);
571 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); 571 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
572 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); 572 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
573 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); 573 clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
574 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); 574 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
575 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); 575 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
576 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); 576 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
577 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); 577 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
578 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); 578 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
579 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); 579 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
580 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); 580 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
581 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); 581 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
582 clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); 582 clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
583 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); 583 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
584 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 584 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
585 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 585 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
586 clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14); 586 clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
587 clk[ssi1_ipg] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); 587 clk[ssi1_ipg] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
588 clk[ssi2_ipg] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); 588 clk[ssi2_ipg] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
589 clk[ssi3_ipg] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); 589 clk[ssi3_ipg] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
590 clk[ssi1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); 590 clk[ssi1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
591 clk[ssi2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); 591 clk[ssi2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
592 clk[ssi3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); 592 clk[ssi3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
593 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 593 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
594 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); 594 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
595 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 595 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
596 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); 596 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
597 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 597 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
598 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 598 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
599 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 599 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
600 clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10); 600 clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
601 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 601 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
602 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 602 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
603 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 603 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
604 clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); 604 clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
605 605
606 /* 606 /*
607 * These two clocks (mmdc_ch0_axi and mmdc_ch1_axi) were incorrectly 607 * These two clocks (mmdc_ch0_axi and mmdc_ch1_axi) were incorrectly
608 * implemented as gate at the beginning. To fix them with the minimized 608 * implemented as gate at the beginning. To fix them with the minimized
609 * impact, let's point them to their dividers. 609 * impact, let's point them to their dividers.
610 */ 610 */
611 clk[mmdc_ch0_axi] = clk[mmdc_ch0_axi_podf]; 611 clk[mmdc_ch0_axi] = clk[mmdc_ch0_axi_podf];
612 clk[mmdc_ch1_axi] = clk[mmdc_ch1_axi_podf]; 612 clk[mmdc_ch1_axi] = clk[mmdc_ch1_axi_podf];
613 613
614 for (i = 0; i < ARRAY_SIZE(clk); i++) 614 for (i = 0; i < ARRAY_SIZE(clk); i++)
615 if (IS_ERR(clk[i])) 615 if (IS_ERR(clk[i]))
616 pr_err("i.MX6q clk %d: register failed with %ld\n", 616 pr_err("i.MX6q clk %d: register failed with %ld\n",
617 i, PTR_ERR(clk[i])); 617 i, PTR_ERR(clk[i]));
618 618
619 /* Initialize clock gate status */ 619 /* Initialize clock gate status */
620 writel_relaxed(1 << CCM_CCGR_OFFSET(11) | 620 writel_relaxed(1 << CCM_CCGR_OFFSET(11) |
621 3 << CCM_CCGR_OFFSET(1) | 621 3 << CCM_CCGR_OFFSET(1) |
622 3 << CCM_CCGR_OFFSET(0), base + 0x68); 622 3 << CCM_CCGR_OFFSET(0), base + 0x68);
623 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) 623 if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
624 writel_relaxed(3 << CCM_CCGR_OFFSET(11) | 624 writel_relaxed(3 << CCM_CCGR_OFFSET(11) |
625 3 << CCM_CCGR_OFFSET(10), base + 0x6c); 625 3 << CCM_CCGR_OFFSET(10), base + 0x6c);
626 else 626 else
627 writel_relaxed(3 << CCM_CCGR_OFFSET(10), base + 0x6c); 627 writel_relaxed(3 << CCM_CCGR_OFFSET(10), base + 0x6c);
628 writel_relaxed(1 << CCM_CCGR_OFFSET(12) | 628 writel_relaxed(1 << CCM_CCGR_OFFSET(12) |
629 3 << CCM_CCGR_OFFSET(11) | 629 3 << CCM_CCGR_OFFSET(11) |
630 3 << CCM_CCGR_OFFSET(10) | 630 3 << CCM_CCGR_OFFSET(10) |
631 3 << CCM_CCGR_OFFSET(9) | 631 3 << CCM_CCGR_OFFSET(9) |
632 3 << CCM_CCGR_OFFSET(8), base + 0x70); 632 3 << CCM_CCGR_OFFSET(8), base + 0x70);
633 writel_relaxed(1 << CCM_CCGR_OFFSET(13) | 633 writel_relaxed(1 << CCM_CCGR_OFFSET(13) |
634 3 << CCM_CCGR_OFFSET(12) | 634 3 << CCM_CCGR_OFFSET(12) |
635 1 << CCM_CCGR_OFFSET(11) | 635 1 << CCM_CCGR_OFFSET(11) |
636 3 << CCM_CCGR_OFFSET(10), base + 0x74); 636 3 << CCM_CCGR_OFFSET(10), base + 0x74);
637 writel_relaxed(3 << CCM_CCGR_OFFSET(7) | 637 writel_relaxed(3 << CCM_CCGR_OFFSET(7) |
638 3 << CCM_CCGR_OFFSET(6) | 638 3 << CCM_CCGR_OFFSET(6) |
639 3 << CCM_CCGR_OFFSET(4), base + 0x78); 639 3 << CCM_CCGR_OFFSET(4), base + 0x78);
640 writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c); 640 writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c);
641 writel_relaxed(0, base + 0x80); 641 writel_relaxed(0, base + 0x80);
642 642
643 /* Make sure PFDs are disabled at boot. */ 643 /* Make sure PFDs are disabled at boot. */
644 reg = readl_relaxed(anatop_base + 0x100); 644 reg = readl_relaxed(anatop_base + 0x100);
645 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */ 645 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
646 if (cpu_is_imx6dl()) 646 if (cpu_is_imx6dl())
647 reg |= 0x80008080; 647 reg |= 0x80008080;
648 else 648 else
649 reg |= 0x80808080; 649 reg |= 0x80808080;
650 writel_relaxed(reg, anatop_base + 0x100); 650 writel_relaxed(reg, anatop_base + 0x100);
651 651
652 /* Disable PLL3 PFDs. */ 652 /* Disable PLL3 PFDs. */
653 reg = readl_relaxed(anatop_base + 0xF0); 653 reg = readl_relaxed(anatop_base + 0xF0);
654 reg |= 0x80808080; 654 reg |= 0x80808080;
655 writel_relaxed(reg, anatop_base + 0xF0); 655 writel_relaxed(reg, anatop_base + 0xF0);
656 656
657 /* Make sure PLLs is disabled */ 657 /* Make sure PLLs is disabled */
658 reg = readl_relaxed(anatop_base + 0xA0); 658 reg = readl_relaxed(anatop_base + 0xA0);
659 reg &= ~(1 << 13); 659 reg &= ~(1 << 13);
660 writel_relaxed(reg, anatop_base + 0xA0); 660 writel_relaxed(reg, anatop_base + 0xA0);
661 661
662 clk_data.clks = clk; 662 clk_data.clks = clk;
663 clk_data.clk_num = ARRAY_SIZE(clk); 663 clk_data.clk_num = ARRAY_SIZE(clk);
664 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 664 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
665 665
666 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); 666 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
667 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 667 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
668 clk_register_clkdev(clk[gpt_3m], "gpt_3m", "imx-gpt.0"); 668 clk_register_clkdev(clk[gpt_3m], "gpt_3m", "imx-gpt.0");
669 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL); 669 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
670 clk_register_clkdev(clk[ahb], "ahb", NULL); 670 clk_register_clkdev(clk[ahb], "ahb", NULL);
671 clk_register_clkdev(clk[cko1], "cko1", NULL); 671 clk_register_clkdev(clk[cko1], "cko1", NULL);
672 clk_register_clkdev(clk[arm], NULL, "cpu0"); 672 clk_register_clkdev(clk[arm], NULL, "cpu0");
673 clk_register_clkdev(clk[pll4_audio_div], "pll4_audio_div", NULL); 673 clk_register_clkdev(clk[pll4_audio_div], "pll4_audio_div", NULL);
674 clk_register_clkdev(clk[pll4_sel], "pll4_sel", NULL); 674 clk_register_clkdev(clk[pll4_sel], "pll4_sel", NULL);
675 clk_register_clkdev(clk[lvds2_in], "lvds2_in", NULL); 675 clk_register_clkdev(clk[lvds2_in], "lvds2_in", NULL);
676 clk_register_clkdev(clk[esai_extal], "esai_extal", NULL); 676 clk_register_clkdev(clk[esai_extal], "esai_extal", NULL);
677 677
678 /* 678 /*
679 * The gpmi needs 100MHz frequency in the EDO/Sync mode, 679 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
680 * We can not get the 100MHz from the pll2_pfd0_352m. 680 * We can not get the 100MHz from the pll2_pfd0_352m.
681 * So choose pll2_pfd2_396m as enfc_sel's parent. 681 * So choose pll2_pfd2_396m as enfc_sel's parent.
682 */ 682 */
683 imx_clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]); 683 imx_clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
684 684
685 /* Set the parent clks of PCIe lvds1 and pcie_axi to be sata ref, axi */ 685 /* Set the parent clks of PCIe lvds1 and pcie_axi to be sata ref, axi */
686 imx_clk_set_parent(clk[lvds1_sel], clk[sata_ref]); 686 imx_clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
687 imx_clk_set_parent(clk[pcie_axi_sel], clk[axi]); 687 imx_clk_set_parent(clk[pcie_axi_sel], clk[axi]);
688 688
689 /* gpu clock initilazation */ 689 /* gpu clock initilazation */
690 /* 690 /*
691 * On mx6dl, 2d core clock sources(sel, podf) is from 3d 691 * On mx6dl, 2d core clock sources(sel, podf) is from 3d
692 * shader core clock, but 3d shader clock multiplexer of 692 * shader core clock, but 3d shader clock multiplexer of
693 * mx6dl is different. For instance the equivalent of 693 * mx6dl is different. For instance the equivalent of
694 * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl. 694 * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl.
695 * Make a note here. 695 * Make a note here.
696 */ 696 */
697 imx_clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]); 697 imx_clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
698 if (cpu_is_imx6dl()) { 698 if (cpu_is_imx6dl()) {
699 imx_clk_set_rate(clk[gpu2d_core], 528000000); 699 imx_clk_set_rate(clk[gpu2d_core], 528000000);
700 /* for mx6dl, change gpu3d_core parent to 594_PFD*/ 700 /* for mx6dl, change gpu3d_core parent to 594_PFD*/
701 imx_clk_set_parent(clk[gpu3d_core_sel], clk[pll2_pfd1_594m]); 701 imx_clk_set_parent(clk[gpu3d_core_sel], clk[pll2_pfd1_594m]);
702 imx_clk_set_rate(clk[gpu3d_core], 528000000); 702 imx_clk_set_rate(clk[gpu3d_core], 528000000);
703 } else if (cpu_is_imx6q()) { 703 } else if (cpu_is_imx6q()) {
704 imx_clk_set_rate(clk[gpu3d_shader], 594000000); 704 imx_clk_set_rate(clk[gpu3d_shader], 594000000);
705 imx_clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]); 705 imx_clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
706 imx_clk_set_rate(clk[gpu3d_core], 528000000); 706 imx_clk_set_rate(clk[gpu3d_core], 528000000);
707 imx_clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]); 707 imx_clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
708 } 708 }
709 709
710 710
711 711
712 /* ipu clock initialization */ 712 /* ipu clock initialization */
713 init_ldb_clks(); 713 init_ldb_clks();
714 imx_clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
715 imx_clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
714 imx_clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); 716 imx_clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
715 imx_clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); 717 imx_clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
716 imx_clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); 718 imx_clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
717 imx_clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); 719 imx_clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
718 imx_clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); 720 imx_clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
719 imx_clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); 721 imx_clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
720 imx_clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); 722 imx_clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
721 imx_clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); 723 imx_clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
722 if (cpu_is_imx6dl()) { 724 if (cpu_is_imx6dl()) {
723 imx_clk_set_rate(clk[pll3_pfd1_540m], 540000000); 725 imx_clk_set_rate(clk[pll3_pfd1_540m], 540000000);
724 imx_clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]); 726 imx_clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
725 imx_clk_set_parent(clk[axi_alt_sel], clk[pll3_pfd1_540m]); 727 imx_clk_set_parent(clk[axi_alt_sel], clk[pll3_pfd1_540m]);
726 imx_clk_set_parent(clk[axi_sel], clk[axi_alt_sel]); 728 imx_clk_set_parent(clk[axi_sel], clk[axi_alt_sel]);
727 /* set epdc/pxp axi clock to 200Mhz */ 729 /* set epdc/pxp axi clock to 200Mhz */
728 imx_clk_set_parent(clk[ipu2_sel], clk[pll2_pfd2_396m]); 730 imx_clk_set_parent(clk[ipu2_sel], clk[pll2_pfd2_396m]);
729 imx_clk_set_rate(clk[ipu2], 200000000); 731 imx_clk_set_rate(clk[ipu2], 200000000);
730 } else if (cpu_is_imx6q()) { 732 } else if (cpu_is_imx6q()) {
731 imx_clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]); 733 imx_clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]);
732 imx_clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]); 734 imx_clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]);
733 } 735 }
734 736
735 /* 737 /*
736 * Let's initially set up CLKO with OSC24M, since this configuration 738 * Let's initially set up CLKO with OSC24M, since this configuration
737 * is widely used by imx6q board designs to clock audio codec. 739 * is widely used by imx6q board designs to clock audio codec.
738 */ 740 */
739 imx_clk_set_parent(clk[cko2_sel], clk[osc]); 741 imx_clk_set_parent(clk[cko2_sel], clk[osc]);
740 imx_clk_set_parent(clk[cko], clk[cko2]); 742 imx_clk_set_parent(clk[cko], clk[cko2]);
741 743
742 /* Audio clocks */ 744 /* Audio clocks */
743 imx_clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]); 745 imx_clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);
744 imx_clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]); 746 imx_clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
745 imx_clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]); 747 imx_clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
746 imx_clk_set_parent(clk[esai_sel], clk[pll4_audio_div]); 748 imx_clk_set_parent(clk[esai_sel], clk[pll4_audio_div]);
747 imx_clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]); 749 imx_clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
748 imx_clk_set_rate(clk[spdif_podf], 227368421); 750 imx_clk_set_rate(clk[spdif_podf], 227368421);
749 imx_clk_set_parent(clk[spdif1_sel], clk[pll3_usb_otg]); 751 imx_clk_set_parent(clk[spdif1_sel], clk[pll3_usb_otg]);
750 imx_clk_set_rate(clk[spdif1_sel], 7500000); 752 imx_clk_set_rate(clk[spdif1_sel], 7500000);
751 753
752 /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */ 754 /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */
753 imx_clk_set_rate(clk[pll4_audio_div], 541900800); 755 imx_clk_set_rate(clk[pll4_audio_div], 541900800);
754 756
755 #ifdef CONFIG_MX6_VPU_352M 757 #ifdef CONFIG_MX6_VPU_352M
756 /* 758 /*
757 * If VPU 352M is enabled, then PLL2_PDF2 need to be 759 * If VPU 352M is enabled, then PLL2_PDF2 need to be
758 * set to 352M, cpufreq will be disabled as VDDSOC/PU 760 * set to 352M, cpufreq will be disabled as VDDSOC/PU
759 * need to be at highest voltage, scaling cpu freq is 761 * need to be at highest voltage, scaling cpu freq is
760 * not saving any power, and busfreq will be also disabled 762 * not saving any power, and busfreq will be also disabled
761 * as the PLL2_PFD2 is not at default freq, in a word, 763 * as the PLL2_PFD2 is not at default freq, in a word,
762 * all modules that sourceing clk from PLL2_PFD2 will 764 * all modules that sourceing clk from PLL2_PFD2 will
763 * be impacted. 765 * be impacted.
764 */ 766 */
765 imx_clk_set_rate(clk[pll2_pfd2_396m], 352000000); 767 imx_clk_set_rate(clk[pll2_pfd2_396m], 352000000);
766 imx_clk_set_parent(clk[vpu_axi_sel], clk[pll2_pfd2_396m]); 768 imx_clk_set_parent(clk[vpu_axi_sel], clk[pll2_pfd2_396m]);
767 pr_info("VPU 352M is enabled!\n"); 769 pr_info("VPU 352M is enabled!\n");
768 #endif 770 #endif
769 771
770 /* 772 /*
771 * Enable clocks only after both parent and rate are all initialized 773 * Enable clocks only after both parent and rate are all initialized
772 * as needed 774 * as needed
773 */ 775 */
774 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 776 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
775 imx_clk_prepare_enable(clk[clks_init_on[i]]); 777 imx_clk_prepare_enable(clk[clks_init_on[i]]);
776 778
777 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { 779 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
778 imx_clk_prepare_enable(clk[usbphy1_gate]); 780 imx_clk_prepare_enable(clk[usbphy1_gate]);
779 imx_clk_prepare_enable(clk[usbphy2_gate]); 781 imx_clk_prepare_enable(clk[usbphy2_gate]);
780 } 782 }
781 783
782 /* Set initial power mode */ 784 /* Set initial power mode */
783 imx6_set_lpm(WAIT_CLOCKED); 785 imx6_set_lpm(WAIT_CLOCKED);
784 786
785 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); 787 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
786 base = of_iomap(np, 0); 788 base = of_iomap(np, 0);
787 WARN_ON(!base); 789 WARN_ON(!base);
788 irq = irq_of_parse_and_map(np, 0); 790 irq = irq_of_parse_and_map(np, 0);
789 mxc_timer_init(base, irq); 791 mxc_timer_init(base, irq);
790 } 792 }
791 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); 793 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
792 794
drivers/pci/host/pci-imx6.c
Diff comments   View file @ 8f7b130
1 /* 1 /*
2 * PCIe host controller driver for Freescale i.MX6 SoCs 2 * PCIe host controller driver for Freescale i.MX6 SoCs
3 * 3 *
4 * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (C) 2013 Kosagi 5 * Copyright (C) 2013 Kosagi
6 * http://www.kosagi.com 6 * http://www.kosagi.com
7 * 7 *
8 * Author: Sean Cross <xobs@kosagi.com> 8 * Author: Sean Cross <xobs@kosagi.com>
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15 #include <linux/clk.h> 15 #include <linux/clk.h>
16 #include <linux/delay.h> 16 #include <linux/delay.h>
17 #include <linux/gpio.h> 17 #include <linux/gpio.h>
18 #include <linux/interrupt.h> 18 #include <linux/interrupt.h>
19 #include <linux/kernel.h> 19 #include <linux/kernel.h>
20 #include <linux/mfd/syscon.h> 20 #include <linux/mfd/syscon.h>
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
22 #include <linux/module.h> 22 #include <linux/module.h>
23 #include <linux/of_gpio.h> 23 #include <linux/of_gpio.h>
24 #include <linux/of_device.h> 24 #include <linux/of_device.h>
25 #include <linux/of_address.h> 25 #include <linux/of_address.h>
26 #include <linux/pci.h> 26 #include <linux/pci.h>
27 #include <linux/platform_device.h> 27 #include <linux/platform_device.h>
28 #include <linux/regmap.h> 28 #include <linux/regmap.h>
29 #include <linux/resource.h> 29 #include <linux/resource.h>
30 #include <linux/signal.h> 30 #include <linux/signal.h>
31 #include <linux/types.h> 31 #include <linux/types.h>
32 #include <linux/busfreq-imx6.h> 32 #include <linux/busfreq-imx6.h>
33 #include <linux/regulator/consumer.h> 33 #include <linux/regulator/consumer.h>
34 34
35 #include "pcie-designware.h" 35 #include "pcie-designware.h"
36 36
37 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) 37 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
38 38
39 /* 39 /*
40 * The default value of the reserved ddr memory 40 * The default value of the reserved ddr memory
41 * used to verify EP/RC memory space access operations. 41 * used to verify EP/RC memory space access operations.
42 * The layout of the 1G ddr on SD boards 42 * The layout of the 1G ddr on SD boards
43 * [others]0x1000_0000 ~ 0x4FFF_FFFF 43 * [others]0x1000_0000 ~ 0x4FFF_FFFF
44 * [imx6sx]0x8000_0000 ~ 0xBFFF_FFFF 44 * [imx6sx]0x8000_0000 ~ 0xBFFF_FFFF
45 * 45 *
46 */ 46 */
47 static u32 ddr_test_region = 0x40000000; 47 static u32 ddr_test_region = 0x40000000;
48 static u32 test_region_size = SZ_2M; 48 static u32 test_region_size = SZ_2M;
49 49
50 /* The pcie who have standalone power domain */ 50 /* The pcie who have standalone power domain */
51 #define PCIE_PHY_HAS_PWR_DOMAIN BIT(0) 51 #define PCIE_PHY_HAS_PWR_DOMAIN BIT(0)
52 52
53 struct imx_pcie_data { 53 struct imx_pcie_data {
54 unsigned int flags; 54 unsigned int flags;
55 }; 55 };
56 56
57 static const struct imx_pcie_data imx6sx_pcie_data = { 57 static const struct imx_pcie_data imx6sx_pcie_data = {
58 .flags = PCIE_PHY_HAS_PWR_DOMAIN, 58 .flags = PCIE_PHY_HAS_PWR_DOMAIN,
59 }; 59 };
60 60
61 struct imx6_pcie { 61 struct imx6_pcie {
62 int reset_gpio; 62 int reset_gpio;
63 int power_on_gpio; 63 int power_on_gpio;
64 int wake_up_gpio; 64 int wake_up_gpio;
65 int disable_gpio; 65 int disable_gpio;
66 const struct imx_pcie_data *data; 66 const struct imx_pcie_data *data;
67 struct clk *lvds_gate; 67 struct clk *lvds_gate;
68 struct clk *sata_ref_100m; 68 struct clk *sata_ref_100m;
69 struct clk *pcie_ref_125m; 69 struct clk *pcie_ref_125m;
70 struct clk *pcie_axi; 70 struct clk *pcie_axi;
71 struct clk *dis_axi; 71 struct clk *dis_axi;
72 struct pcie_port pp; 72 struct pcie_port pp;
73 struct regmap *iomuxc_gpr; 73 struct regmap *iomuxc_gpr;
74 struct regulator *pcie_reg; 74 struct regulator *pcie_reg;
75 struct regulator *pcie_phy_reg; 75 struct regulator *pcie_phy_reg;
76 void __iomem *mem_base; 76 void __iomem *mem_base;
77 }; 77 };
78 static struct imx6_pcie *imx6_pcie; 78 static struct imx6_pcie *imx6_pcie;
79 79
80 /* PCIe Port Logic registers (memory-mapped) */ 80 /* PCIe Port Logic registers (memory-mapped) */
81 #define PL_OFFSET 0x700 81 #define PL_OFFSET 0x700
82 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) 82 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
83 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) 83 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
84 84
85 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 85 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
86 #define PCIE_PHY_CTRL_DATA_LOC 0 86 #define PCIE_PHY_CTRL_DATA_LOC 0
87 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 87 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
88 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 88 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
89 #define PCIE_PHY_CTRL_WR_LOC 18 89 #define PCIE_PHY_CTRL_WR_LOC 18
90 #define PCIE_PHY_CTRL_RD_LOC 19 90 #define PCIE_PHY_CTRL_RD_LOC 19
91 91
92 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 92 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
93 #define PCIE_PHY_STAT_ACK_LOC 16 93 #define PCIE_PHY_STAT_ACK_LOC 16
94 94
95 /* PHY registers (not memory-mapped) */ 95 /* PHY registers (not memory-mapped) */
96 #define PCIE_PHY_RX_ASIC_OUT 0x100D 96 #define PCIE_PHY_RX_ASIC_OUT 0x100D
97 97
98 #define PHY_RX_OVRD_IN_LO 0x1005 98 #define PHY_RX_OVRD_IN_LO 0x1005
99 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) 99 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
100 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) 100 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
101 101
102 static inline bool is_imx6sx_pcie(struct imx6_pcie *imx6_pcie) 102 static inline bool is_imx6sx_pcie(struct imx6_pcie *imx6_pcie)
103 { 103 {
104 return imx6_pcie->data == &imx6sx_pcie_data; 104 return imx6_pcie->data == &imx6sx_pcie_data;
105 } 105 }
106 106
107 #ifdef DEBUG 107 #ifdef DEBUG
108 static int pcie_reg_dump(struct imx6_pcie *imx6_pcie) 108 static int pcie_reg_dump(struct imx6_pcie *imx6_pcie)
109 { 109 {
110 u32 val; 110 u32 val;
111 struct regmap *anatop_g; 111 struct regmap *anatop_g;
112 112
113 /* GPRs registers */ 113 /* GPRs registers */
114 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &val); 114 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &val);
115 pr_info("<F> %s <L> %d gpr1 0x%08x.\n", __func__, __LINE__, val); 115 pr_info("<F> %s <L> %d gpr1 0x%08x.\n", __func__, __LINE__, val);
116 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, &val); 116 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, &val);
117 pr_info("<F> %s <L> %d gpr5 0x%08x.\n", __func__, __LINE__, val); 117 pr_info("<F> %s <L> %d gpr5 0x%08x.\n", __func__, __LINE__, val);
118 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, &val); 118 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, &val);
119 pr_info("<F> %s <L> %d gpr8 0x%08x.\n", __func__, __LINE__, val); 119 pr_info("<F> %s <L> %d gpr8 0x%08x.\n", __func__, __LINE__, val);
120 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &val); 120 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &val);
121 pr_info("<F> %s <L> %d gpr12 0x%08x.\n", __func__, __LINE__, val); 121 pr_info("<F> %s <L> %d gpr12 0x%08x.\n", __func__, __LINE__, val);
122 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR13, &val); 122 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR13, &val);
123 pr_info("<F> %s <L> %d gpr13 0x%08x.\n", __func__, __LINE__, val); 123 pr_info("<F> %s <L> %d gpr13 0x%08x.\n", __func__, __LINE__, val);
124 124
125 /* anatop registers: pll6_enet, misc1 */ 125 /* anatop registers: pll6_enet, misc1 */
126 anatop_g = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop"); 126 anatop_g = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
127 if (IS_ERR(anatop_g)) 127 if (IS_ERR(anatop_g))
128 pr_err("failed to find fsl,imx6sx-anatop regmap\n"); 128 pr_err("failed to find fsl,imx6sx-anatop regmap\n");
129 regmap_read(anatop_g, 0xe0, &val); 129 regmap_read(anatop_g, 0xe0, &val);
130 pr_info("<F> %s <L> %d pll6_enet 0x%08x.\n", __func__, __LINE__, val); 130 pr_info("<F> %s <L> %d pll6_enet 0x%08x.\n", __func__, __LINE__, val);
131 regmap_read(anatop_g, 0x160, &val); 131 regmap_read(anatop_g, 0x160, &val);
132 pr_info("<F> %s <L> %d misc1 0x%08x.\n", __func__, __LINE__, val); 132 pr_info("<F> %s <L> %d misc1 0x%08x.\n", __func__, __LINE__, val);
133 } 133 }
134 #endif 134 #endif
135 135
136 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) 136 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
137 { 137 {
138 u32 val; 138 u32 val;
139 u32 max_iterations = 10; 139 u32 max_iterations = 10;
140 u32 wait_counter = 0; 140 u32 wait_counter = 0;
141 141
142 do { 142 do {
143 val = readl(dbi_base + PCIE_PHY_STAT); 143 val = readl(dbi_base + PCIE_PHY_STAT);
144 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 144 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
145 wait_counter++; 145 wait_counter++;
146 146
147 if (val == exp_val) 147 if (val == exp_val)
148 return 0; 148 return 0;
149 149
150 udelay(1); 150 udelay(1);
151 } while (wait_counter < max_iterations); 151 } while (wait_counter < max_iterations);
152 152
153 return -ETIMEDOUT; 153 return -ETIMEDOUT;
154 } 154 }
155 155
156 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) 156 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
157 { 157 {
158 u32 val; 158 u32 val;
159 int ret; 159 int ret;
160 160
161 val = addr << PCIE_PHY_CTRL_DATA_LOC; 161 val = addr << PCIE_PHY_CTRL_DATA_LOC;
162 writel(val, dbi_base + PCIE_PHY_CTRL); 162 writel(val, dbi_base + PCIE_PHY_CTRL);
163 163
164 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); 164 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
165 writel(val, dbi_base + PCIE_PHY_CTRL); 165 writel(val, dbi_base + PCIE_PHY_CTRL);
166 166
167 ret = pcie_phy_poll_ack(dbi_base, 1); 167 ret = pcie_phy_poll_ack(dbi_base, 1);
168 if (ret) 168 if (ret)
169 return ret; 169 return ret;
170 170
171 val = addr << PCIE_PHY_CTRL_DATA_LOC; 171 val = addr << PCIE_PHY_CTRL_DATA_LOC;
172 writel(val, dbi_base + PCIE_PHY_CTRL); 172 writel(val, dbi_base + PCIE_PHY_CTRL);
173 173
174 ret = pcie_phy_poll_ack(dbi_base, 0); 174 ret = pcie_phy_poll_ack(dbi_base, 0);
175 if (ret) 175 if (ret)
176 return ret; 176 return ret;
177 177
178 return 0; 178 return 0;
179 } 179 }
180 180
181 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 181 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
182 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) 182 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
183 { 183 {
184 u32 val, phy_ctl; 184 u32 val, phy_ctl;
185 int ret; 185 int ret;
186 186
187 ret = pcie_phy_wait_ack(dbi_base, addr); 187 ret = pcie_phy_wait_ack(dbi_base, addr);
188 if (ret) 188 if (ret)
189 return ret; 189 return ret;
190 190
191 /* assert Read signal */ 191 /* assert Read signal */
192 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; 192 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
193 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); 193 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
194 194
195 ret = pcie_phy_poll_ack(dbi_base, 1); 195 ret = pcie_phy_poll_ack(dbi_base, 1);
196 if (ret) 196 if (ret)
197 return ret; 197 return ret;
198 198
199 val = readl(dbi_base + PCIE_PHY_STAT); 199 val = readl(dbi_base + PCIE_PHY_STAT);
200 *data = val & 0xffff; 200 *data = val & 0xffff;
201 201
202 /* deassert Read signal */ 202 /* deassert Read signal */
203 writel(0x00, dbi_base + PCIE_PHY_CTRL); 203 writel(0x00, dbi_base + PCIE_PHY_CTRL);
204 204
205 ret = pcie_phy_poll_ack(dbi_base, 0); 205 ret = pcie_phy_poll_ack(dbi_base, 0);
206 if (ret) 206 if (ret)
207 return ret; 207 return ret;
208 208
209 return 0; 209 return 0;
210 } 210 }
211 211
212 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) 212 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
213 { 213 {
214 u32 var; 214 u32 var;
215 int ret; 215 int ret;
216 216
217 /* write addr */ 217 /* write addr */
218 /* cap addr */ 218 /* cap addr */
219 ret = pcie_phy_wait_ack(dbi_base, addr); 219 ret = pcie_phy_wait_ack(dbi_base, addr);
220 if (ret) 220 if (ret)
221 return ret; 221 return ret;
222 222
223 var = data << PCIE_PHY_CTRL_DATA_LOC; 223 var = data << PCIE_PHY_CTRL_DATA_LOC;
224 writel(var, dbi_base + PCIE_PHY_CTRL); 224 writel(var, dbi_base + PCIE_PHY_CTRL);
225 225
226 /* capture data */ 226 /* capture data */
227 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); 227 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
228 writel(var, dbi_base + PCIE_PHY_CTRL); 228 writel(var, dbi_base + PCIE_PHY_CTRL);
229 229
230 ret = pcie_phy_poll_ack(dbi_base, 1); 230 ret = pcie_phy_poll_ack(dbi_base, 1);
231 if (ret) 231 if (ret)
232 return ret; 232 return ret;
233 233
234 /* deassert cap data */ 234 /* deassert cap data */
235 var = data << PCIE_PHY_CTRL_DATA_LOC; 235 var = data << PCIE_PHY_CTRL_DATA_LOC;
236 writel(var, dbi_base + PCIE_PHY_CTRL); 236 writel(var, dbi_base + PCIE_PHY_CTRL);
237 237
238 /* wait for ack de-assertion */ 238 /* wait for ack de-assertion */
239 ret = pcie_phy_poll_ack(dbi_base, 0); 239 ret = pcie_phy_poll_ack(dbi_base, 0);
240 if (ret) 240 if (ret)
241 return ret; 241 return ret;
242 242
243 /* assert wr signal */ 243 /* assert wr signal */
244 var = 0x1 << PCIE_PHY_CTRL_WR_LOC; 244 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
245 writel(var, dbi_base + PCIE_PHY_CTRL); 245 writel(var, dbi_base + PCIE_PHY_CTRL);
246 246
247 /* wait for ack */ 247 /* wait for ack */
248 ret = pcie_phy_poll_ack(dbi_base, 1); 248 ret = pcie_phy_poll_ack(dbi_base, 1);
249 if (ret) 249 if (ret)
250 return ret; 250 return ret;
251 251
252 /* deassert wr signal */ 252 /* deassert wr signal */
253 var = data << PCIE_PHY_CTRL_DATA_LOC; 253 var = data << PCIE_PHY_CTRL_DATA_LOC;
254 writel(var, dbi_base + PCIE_PHY_CTRL); 254 writel(var, dbi_base + PCIE_PHY_CTRL);
255 255
256 /* wait for ack de-assertion */ 256 /* wait for ack de-assertion */
257 ret = pcie_phy_poll_ack(dbi_base, 0); 257 ret = pcie_phy_poll_ack(dbi_base, 0);
258 if (ret) 258 if (ret)
259 return ret; 259 return ret;
260 260
261 writel(0x0, dbi_base + PCIE_PHY_CTRL); 261 writel(0x0, dbi_base + PCIE_PHY_CTRL);
262 262
263 return 0; 263 return 0;
264 } 264 }
265 265
266 /* Added for PCI abort handling */ 266 /* Added for PCI abort handling */
267 static int imx6q_pcie_abort_handler(unsigned long addr, 267 static int imx6q_pcie_abort_handler(unsigned long addr,
268 unsigned int fsr, struct pt_regs *regs) 268 unsigned int fsr, struct pt_regs *regs)
269 { 269 {
270 return 0; 270 return 0;
271 } 271 }
272 272
273 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) 273 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
274 { 274 {
275 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); 275 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
276 int ret; 276 int ret;
277 277
278 if (gpio_is_valid(imx6_pcie->power_on_gpio)) 278 if (gpio_is_valid(imx6_pcie->power_on_gpio))
279 gpio_set_value_cansleep(imx6_pcie->power_on_gpio, 1); 279 gpio_set_value_cansleep(imx6_pcie->power_on_gpio, 1);
280 280
281 request_bus_freq(BUS_FREQ_HIGH); 281 request_bus_freq(BUS_FREQ_HIGH);
282 282
283 if (is_imx6sx_pcie(imx6_pcie)) { 283 if (is_imx6sx_pcie(imx6_pcie)) {
284 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 284 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
285 IMX6Q_GPR12_PCIE_TEST_PD, 0 << 30); 285 IMX6Q_GPR12_PCIE_TEST_PD, 0 << 30);
286 286
287 ret = clk_prepare_enable(imx6_pcie->dis_axi); 287 ret = clk_prepare_enable(imx6_pcie->dis_axi);
288 if (ret) { 288 if (ret) {
289 dev_err(pp->dev, "unable to enable dis_axi\n"); 289 dev_err(pp->dev, "unable to enable dis_axi\n");
290 goto err_dis_axi; 290 goto err_dis_axi;
291 } 291 }
292 } else { 292 } else {
293 /* Those bits are not used anymore on imx6sx */ 293 /* Those bits are not used anymore on imx6sx */
294 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 294 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
295 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 295 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
296 296
297 /* sata_ref is not used by pcie on imx6sx */ 297 /* sata_ref is not used by pcie on imx6sx */
298 ret = clk_prepare_enable(imx6_pcie->sata_ref_100m); 298 ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
299 if (ret) { 299 if (ret) {
300 dev_err(pp->dev, "unable to enable sata_ref_100m\n"); 300 dev_err(pp->dev, "unable to enable sata_ref_100m\n");
301 goto err_sata_ref; 301 goto err_sata_ref;
302 } 302 }
303 } 303 }
304 304
305 ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m); 305 ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
306 if (ret) { 306 if (ret) {
307 dev_err(pp->dev, "unable to enable pcie_ref_125m\n"); 307 dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
308 goto err_pcie_ref; 308 goto err_pcie_ref;
309 } 309 }
310 310
311 if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS) 311 if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
312 && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) { 312 && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) {
313 ret = clk_prepare_enable(imx6_pcie->lvds_gate); 313 ret = clk_prepare_enable(imx6_pcie->lvds_gate);
314 if (ret) { 314 if (ret) {
315 dev_err(pp->dev, "unable to enable lvds_gate\n"); 315 dev_err(pp->dev, "unable to enable lvds_gate\n");
316 goto err_lvds_gate; 316 goto err_lvds_gate;
317 } 317 }
318 } 318 }
319 319
320 ret = clk_prepare_enable(imx6_pcie->pcie_axi); 320 ret = clk_prepare_enable(imx6_pcie->pcie_axi);
321 if (ret) { 321 if (ret) {
322 dev_err(pp->dev, "unable to enable pcie_axi\n"); 322 dev_err(pp->dev, "unable to enable pcie_axi\n");
323 goto err_pcie_axi; 323 goto err_pcie_axi;
324 } 324 }
325 325
326 if (!is_imx6sx_pcie(imx6_pcie)) { 326 if (!is_imx6sx_pcie(imx6_pcie)) {
327 /* 327 /*
328 * This bit is not used anymore on imx6sx. 328 * This bit is not used anymore on imx6sx.
329 * wailt for the pcie clks are stable. 329 * wailt for the pcie clks are stable.
330 * ~4us is requried, let it to be 10us here. 330 * ~4us is requried, let it to be 10us here.
331 */ 331 */
332 udelay(10); 332 udelay(10);
333 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 333 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
334 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 334 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
335 } 335 }
336 336
337 /* allow the clocks to stabilize */ 337 /* allow the clocks to stabilize */
338 udelay(200); 338 usleep_range(200, 500);
339 339
340 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 340 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
341 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0); 341 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0);
342 mdelay(1); 342 msleep(100);
343 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1); 343 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
344 } 344 }
345 345
346 return 0; 346 return 0;
347 347
348 err_pcie_axi: 348 err_pcie_axi:
349 clk_disable_unprepare(imx6_pcie->lvds_gate); 349 clk_disable_unprepare(imx6_pcie->lvds_gate);
350 err_lvds_gate: 350 err_lvds_gate:
351 clk_disable_unprepare(imx6_pcie->pcie_ref_125m); 351 clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
352 err_pcie_ref: 352 err_pcie_ref:
353 if (!is_imx6sx_pcie(imx6_pcie)) 353 if (!is_imx6sx_pcie(imx6_pcie))
354 clk_disable_unprepare(imx6_pcie->sata_ref_100m); 354 clk_disable_unprepare(imx6_pcie->sata_ref_100m);
355 err_sata_ref: 355 err_sata_ref:
356 if (is_imx6sx_pcie(imx6_pcie)) 356 if (is_imx6sx_pcie(imx6_pcie))
357 clk_disable_unprepare(imx6_pcie->dis_axi); 357 clk_disable_unprepare(imx6_pcie->dis_axi);
358 err_dis_axi: 358 err_dis_axi:
359 release_bus_freq(BUS_FREQ_HIGH); 359 release_bus_freq(BUS_FREQ_HIGH);
360 return ret; 360 return ret;
361 361
362 } 362 }
363 363
364 static void imx6_pcie_init_phy(struct pcie_port *pp) 364 static void imx6_pcie_init_phy(struct pcie_port *pp)
365 { 365 {
366 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); 366 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
367 int ret; 367 int ret;
368 368
369 /* 369 /*
370 * iMX6SX PCIe has the stand-alone power domain 370 * iMX6SX PCIe has the stand-alone power domain
371 * add the initialization here for iMX6SX PCIe. 371 * add the initialization here for iMX6SX PCIe.
372 */ 372 */
373 if (is_imx6sx_pcie(imx6_pcie)) { 373 if (is_imx6sx_pcie(imx6_pcie)) {
374 /* Force PCIe PHY reset */ 374 /* Force PCIe PHY reset */
375 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 375 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
376 BIT(19), 1 << 19); 376 BIT(19), 1 << 19);
377 377
378 ret = regulator_enable(imx6_pcie->pcie_reg); 378 ret = regulator_enable(imx6_pcie->pcie_reg);
379 if (ret) 379 if (ret)
380 dev_info(pp->dev, "failed to enable pcie reg.\n"); 380 dev_info(pp->dev, "failed to enable pcie reg.\n");
381 /* Power up PCIe PHY, ANATOP_REG_CORE offset 0x140, bit13-9 */ 381 /* Power up PCIe PHY, ANATOP_REG_CORE offset 0x140, bit13-9 */
382 regulator_set_voltage(imx6_pcie->pcie_phy_reg, 382 regulator_set_voltage(imx6_pcie->pcie_phy_reg,
383 1100000, 1100000); 383 1100000, 1100000);
384 ret = regulator_enable(imx6_pcie->pcie_phy_reg); 384 ret = regulator_enable(imx6_pcie->pcie_phy_reg);
385 if (ret) 385 if (ret)
386 dev_info(pp->dev, "failed to enable pcie phy reg.\n"); 386 dev_info(pp->dev, "failed to enable pcie phy reg.\n");
387 387
388 } 388 }
389 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 389 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
390 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 390 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
391 391
392 /* configure constant input signal to the pcie ctrl and phy */ 392 /* configure constant input signal to the pcie ctrl and phy */
393 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) 393 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS))
394 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 394 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
395 IMX6Q_GPR12_DEVICE_TYPE, 395 IMX6Q_GPR12_DEVICE_TYPE,
396 PCI_EXP_TYPE_ENDPOINT << 12); 396 PCI_EXP_TYPE_ENDPOINT << 12);
397 else 397 else
398 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 398 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
399 IMX6Q_GPR12_DEVICE_TYPE, 399 IMX6Q_GPR12_DEVICE_TYPE,
400 PCI_EXP_TYPE_ROOT_PORT << 12); 400 PCI_EXP_TYPE_ROOT_PORT << 12);
401 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 401 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
402 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 402 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
403 403
404 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 404 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
405 IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0); 405 IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
406 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 406 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
407 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6); 407 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
408 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 408 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
409 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); 409 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
410 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 410 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
411 IMX6Q_GPR8_TX_SWING_FULL, 127 << 18); 411 IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
412 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 412 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
413 IMX6Q_GPR8_TX_SWING_LOW, 127 << 25); 413 IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
414 } 414 }
415 415
416 static irqreturn_t imx_pcie_msi_irq_handler(int irq, void *arg) 416 static irqreturn_t imx_pcie_msi_irq_handler(int irq, void *arg)
417 { 417 {
418 struct pcie_port *pp = arg; 418 struct pcie_port *pp = arg;
419 419
420 dw_handle_msi_irq(pp); 420 dw_handle_msi_irq(pp);
421 421
422 return IRQ_HANDLED; 422 return IRQ_HANDLED;
423 } 423 }
424 424
425 static int imx6_pcie_host_init(struct pcie_port *pp) 425 static int imx6_pcie_host_init(struct pcie_port *pp)
426 { 426 {
427 int count = 0; 427 int count = 0;
428 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); 428 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
429 429
430 imx6_pcie_init_phy(pp); 430 imx6_pcie_init_phy(pp);
431 431
432 imx6_pcie_deassert_core_reset(pp); 432 imx6_pcie_deassert_core_reset(pp);
433 433
434 /* 434 /*
435 * iMX6SX PCIe has the stand-alone power domain. 435 * iMX6SX PCIe has the stand-alone power domain.
436 * refer to the initialization for iMX6SX PCIe, 436 * refer to the initialization for iMX6SX PCIe,
437 * release the PCIe PHY reset here, 437 * release the PCIe PHY reset here,
438 * before LTSSM enable is set. 438 * before LTSSM enable is set.
439 */ 439 */
440 if (is_imx6sx_pcie(imx6_pcie)) 440 if (is_imx6sx_pcie(imx6_pcie))
441 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 441 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
442 BIT(19), 0 << 19); 442 BIT(19), 0 << 19);
443 443
444 444
445 dw_pcie_setup_rc(pp); 445 dw_pcie_setup_rc(pp);
446 446
447 #ifdef DEBUG 447 #ifdef DEBUG
448 pcie_reg_dump(imx6_pcie); 448 pcie_reg_dump(imx6_pcie);
449 #endif 449 #endif
450 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 450 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
451 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); 451 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
452 452
453 while (!dw_pcie_link_up(pp)) { 453 while (!dw_pcie_link_up(pp)) {
454 usleep_range(100, 1000); 454 usleep_range(100, 1000);
455 count++; 455 count++;
456 if (count >= 200) { 456 if (count >= 200) {
457 dev_err(pp->dev, "phy link never came up\n"); 457 dev_err(pp->dev, "phy link never came up\n");
458 dev_dbg(pp->dev, 458 dev_dbg(pp->dev,
459 "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 459 "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
460 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), 460 readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
461 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); 461 readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
462 clk_disable_unprepare(imx6_pcie->pcie_axi); 462 clk_disable_unprepare(imx6_pcie->pcie_axi);
463 if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS) 463 if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
464 && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) 464 && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
465 clk_disable_unprepare(imx6_pcie->lvds_gate); 465 clk_disable_unprepare(imx6_pcie->lvds_gate);
466 clk_disable_unprepare(imx6_pcie->pcie_ref_125m); 466 clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
467 if (is_imx6sx_pcie(imx6_pcie)) { 467 if (is_imx6sx_pcie(imx6_pcie)) {
468 /* Disable clks and power down PCIe PHY */ 468 /* Disable clks and power down PCIe PHY */
469 clk_disable_unprepare(imx6_pcie->dis_axi); 469 clk_disable_unprepare(imx6_pcie->dis_axi);
470 release_bus_freq(BUS_FREQ_HIGH); 470 release_bus_freq(BUS_FREQ_HIGH);
471 471
472 /* Put PCIe PHY to be isolation */ 472 /* Put PCIe PHY to be isolation */
473 regmap_update_bits(imx6_pcie->iomuxc_gpr, 473 regmap_update_bits(imx6_pcie->iomuxc_gpr,
474 IOMUXC_GPR0, BIT(6), 1 << 6); 474 IOMUXC_GPR0, BIT(6), 1 << 6);
475 475
476 /* 476 /*
477 * Power down PCIe PHY. 477 * Power down PCIe PHY.
478 */ 478 */
479 regulator_disable(imx6_pcie->pcie_phy_reg); 479 regulator_disable(imx6_pcie->pcie_phy_reg);
480 regulator_disable(imx6_pcie->pcie_reg); 480 regulator_disable(imx6_pcie->pcie_reg);
481 } else { 481 } else {
482 clk_disable_unprepare(imx6_pcie->sata_ref_100m); 482 clk_disable_unprepare(imx6_pcie->sata_ref_100m);
483 release_bus_freq(BUS_FREQ_HIGH); 483 release_bus_freq(BUS_FREQ_HIGH);
484 } 484 }
485 return -ENODEV; 485 return -ENODEV;
486 } 486 }
487 } 487 }
488 488
489 if (IS_ENABLED(CONFIG_PCI_MSI)) 489 if (IS_ENABLED(CONFIG_PCI_MSI))
490 dw_pcie_msi_init(pp); 490 dw_pcie_msi_init(pp);
491 491
492 return 0; 492 return 0;
493 } 493 }
494 494
495 static int imx6_pcie_link_up(struct pcie_port *pp) 495 static int imx6_pcie_link_up(struct pcie_port *pp)
496 { 496 {
497 u32 rc, ltssm, rx_valid, temp; 497 u32 rc, ltssm, rx_valid, temp;
498 498
499 /* link is debug bit 36, debug register 1 starts at bit 32 */ 499 /* link is debug bit 36, debug register 1 starts at bit 32 */
500 rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); 500 rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
501 if (rc) 501 if (rc)
502 return -EAGAIN; 502 return -EAGAIN;
503 503
504 /* 504 /*
505 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. 505 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
506 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). 506 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
507 * If (MAC/LTSSM.state == Recovery.RcvrLock) 507 * If (MAC/LTSSM.state == Recovery.RcvrLock)
508 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition 508 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
509 * to gen2 is stuck 509 * to gen2 is stuck
510 */ 510 */
511 pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); 511 pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
512 ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F; 512 ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
513 513
514 if (rx_valid & 0x01) 514 if (rx_valid & 0x01)
515 return 0; 515 return 0;
516 516
517 if (ltssm != 0x0d) 517 if (ltssm != 0x0d)
518 return 0; 518 return 0;
519 519
520 dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); 520 dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
521 521
522 pcie_phy_read(pp->dbi_base, 522 pcie_phy_read(pp->dbi_base,
523 PHY_RX_OVRD_IN_LO, &temp); 523 PHY_RX_OVRD_IN_LO, &temp);
524 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN 524 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
525 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); 525 | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
526 pcie_phy_write(pp->dbi_base, 526 pcie_phy_write(pp->dbi_base,
527 PHY_RX_OVRD_IN_LO, temp); 527 PHY_RX_OVRD_IN_LO, temp);
528 528
529 usleep_range(2000, 3000); 529 usleep_range(2000, 3000);
530 530
531 pcie_phy_read(pp->dbi_base, 531 pcie_phy_read(pp->dbi_base,
532 PHY_RX_OVRD_IN_LO, &temp); 532 PHY_RX_OVRD_IN_LO, &temp);
533 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN 533 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
534 | PHY_RX_OVRD_IN_LO_RX_PLL_EN); 534 | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
535 pcie_phy_write(pp->dbi_base, 535 pcie_phy_write(pp->dbi_base,
536 PHY_RX_OVRD_IN_LO, temp); 536 PHY_RX_OVRD_IN_LO, temp);
537 537
538 return 0; 538 return 0;
539 } 539 }
540 540
541 static struct pcie_host_ops imx6_pcie_host_ops = { 541 static struct pcie_host_ops imx6_pcie_host_ops = {
542 .link_up = imx6_pcie_link_up, 542 .link_up = imx6_pcie_link_up,
543 .host_init = imx6_pcie_host_init, 543 .host_init = imx6_pcie_host_init,
544 }; 544 };
545 545
546 static int imx6_add_pcie_port(struct pcie_port *pp, 546 static int imx6_add_pcie_port(struct pcie_port *pp,
547 struct platform_device *pdev) 547 struct platform_device *pdev)
548 { 548 {
549 int ret; 549 int ret;
550 550
551 pp->irq = platform_get_irq(pdev, 0); 551 pp->irq = platform_get_irq(pdev, 0);
552 if (!pp->irq) { 552 if (!pp->irq) {
553 dev_err(&pdev->dev, "failed to get irq\n"); 553 dev_err(&pdev->dev, "failed to get irq\n");
554 return -ENODEV; 554 return -ENODEV;
555 } 555 }
556 556
557 if (IS_ENABLED(CONFIG_PCI_MSI)) { 557 if (IS_ENABLED(CONFIG_PCI_MSI)) {
558 pp->msi_irq = pp->irq - 3; 558 pp->msi_irq = pp->irq - 3;
559 if (!pp->msi_irq) { 559 if (!pp->msi_irq) {
560 dev_err(&pdev->dev, "failed to get msi irq\n"); 560 dev_err(&pdev->dev, "failed to get msi irq\n");
561 return -ENODEV; 561 return -ENODEV;
562 } 562 }
563 563
564 ret = devm_request_irq(&pdev->dev, pp->msi_irq, 564 ret = devm_request_irq(&pdev->dev, pp->msi_irq,
565 imx_pcie_msi_irq_handler, 565 imx_pcie_msi_irq_handler,
566 IRQF_SHARED, "imx6q-pcie", pp); 566 IRQF_SHARED, "imx6q-pcie", pp);
567 if (ret) { 567 if (ret) {
568 dev_err(&pdev->dev, "failed to request msi irq\n"); 568 dev_err(&pdev->dev, "failed to request msi irq\n");
569 return ret; 569 return ret;
570 } 570 }
571 } 571 }
572 572
573 pp->root_bus_nr = -1; 573 pp->root_bus_nr = -1;
574 pp->ops = &imx6_pcie_host_ops; 574 pp->ops = &imx6_pcie_host_ops;
575 575
576 spin_lock_init(&pp->conf_lock); 576 spin_lock_init(&pp->conf_lock);
577
578 usleep_range(25000, 30000);
579
577 ret = dw_pcie_host_init(pp); 580 ret = dw_pcie_host_init(pp);
578 if (ret) { 581 if (ret) {
579 dev_err(&pdev->dev, "failed to initialize host\n"); 582 dev_err(&pdev->dev, "failed to initialize host\n");
580 return ret; 583 return ret;
581 } 584 }
582 585
583 return 0; 586 return 0;
584 } 587 }
585 588
586 static ssize_t imx_pcie_bar0_addr_info(struct device *dev, 589 static ssize_t imx_pcie_bar0_addr_info(struct device *dev,
587 struct device_attribute *devattr, char *buf) 590 struct device_attribute *devattr, char *buf)
588 { 591 {
589 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 592 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
590 struct pcie_port *pp = &imx6_pcie->pp; 593 struct pcie_port *pp = &imx6_pcie->pp;
591 594
592 return sprintf(buf, "imx-pcie-bar0-addr-info start 0x%08x\n", 595 return sprintf(buf, "imx-pcie-bar0-addr-info start 0x%08x\n",
593 readl(pp->dbi_base + PCI_BASE_ADDRESS_0)); 596 readl(pp->dbi_base + PCI_BASE_ADDRESS_0));
594 } 597 }
595 598
596 static ssize_t imx_pcie_bar0_addr_start(struct device *dev, 599 static ssize_t imx_pcie_bar0_addr_start(struct device *dev,
597 struct device_attribute *attr, const char *buf, size_t count) 600 struct device_attribute *attr, const char *buf, size_t count)
598 { 601 {
599 u32 bar_start; 602 u32 bar_start;
600 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 603 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
601 struct pcie_port *pp = &imx6_pcie->pp; 604 struct pcie_port *pp = &imx6_pcie->pp;
602 605
603 sscanf(buf, "%x\n", &bar_start); 606 sscanf(buf, "%x\n", &bar_start);
604 writel(bar_start, pp->dbi_base + PCI_BASE_ADDRESS_0); 607 writel(bar_start, pp->dbi_base + PCI_BASE_ADDRESS_0);
605 608
606 return count; 609 return count;
607 } 610 }
608 611
609 static void imx_pcie_regions_setup(struct device *dev) 612 static void imx_pcie_regions_setup(struct device *dev)
610 { 613 {
611 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 614 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
612 struct pcie_port *pp = &imx6_pcie->pp; 615 struct pcie_port *pp = &imx6_pcie->pp;
613 616
614 if (is_imx6sx_pcie(imx6_pcie)) 617 if (is_imx6sx_pcie(imx6_pcie))
615 ddr_test_region = 0xb0000000; 618 ddr_test_region = 0xb0000000;
616 619
617 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) { 620 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
618 /* 621 /*
619 * region2 outbound used to access rc mem 622 * region2 outbound used to access rc mem
620 * in imx6 pcie ep/rc validation system 623 * in imx6 pcie ep/rc validation system
621 */ 624 */
622 writel(2, pp->dbi_base + PCIE_ATU_VIEWPORT); 625 writel(2, pp->dbi_base + PCIE_ATU_VIEWPORT);
623 writel(pp->mem_base, pp->dbi_base + PCIE_ATU_LOWER_BASE); 626 writel(pp->mem_base, pp->dbi_base + PCIE_ATU_LOWER_BASE);
624 writel(0, pp->dbi_base + PCIE_ATU_UPPER_BASE); 627 writel(0, pp->dbi_base + PCIE_ATU_UPPER_BASE);
625 writel(pp->mem_base + test_region_size, 628 writel(pp->mem_base + test_region_size,
626 pp->dbi_base + PCIE_ATU_LIMIT); 629 pp->dbi_base + PCIE_ATU_LIMIT);
627 630
628 writel(ddr_test_region, 631 writel(ddr_test_region,
629 pp->dbi_base + PCIE_ATU_LOWER_TARGET); 632 pp->dbi_base + PCIE_ATU_LOWER_TARGET);
630 writel(0, pp->dbi_base + PCIE_ATU_UPPER_TARGET); 633 writel(0, pp->dbi_base + PCIE_ATU_UPPER_TARGET);
631 writel(PCIE_ATU_TYPE_MEM, pp->dbi_base + PCIE_ATU_CR1); 634 writel(PCIE_ATU_TYPE_MEM, pp->dbi_base + PCIE_ATU_CR1);
632 writel(PCIE_ATU_ENABLE, pp->dbi_base + PCIE_ATU_CR2); 635 writel(PCIE_ATU_ENABLE, pp->dbi_base + PCIE_ATU_CR2);
633 } 636 }
634 637
635 if (IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) { 638 if (IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) {
636 /* 639 /*
637 * region2 outbound used to access ep mem 640 * region2 outbound used to access ep mem
638 * in imx6 pcie ep/rc validation system 641 * in imx6 pcie ep/rc validation system
639 */ 642 */
640 writel(2, pp->dbi_base + PCIE_ATU_VIEWPORT); 643 writel(2, pp->dbi_base + PCIE_ATU_VIEWPORT);
641 writel(pp->mem_base, pp->dbi_base + PCIE_ATU_LOWER_BASE); 644 writel(pp->mem_base, pp->dbi_base + PCIE_ATU_LOWER_BASE);
642 writel(0, pp->dbi_base + PCIE_ATU_UPPER_BASE); 645 writel(0, pp->dbi_base + PCIE_ATU_UPPER_BASE);
643 writel(pp->mem_base + test_region_size, 646 writel(pp->mem_base + test_region_size,
644 pp->dbi_base + PCIE_ATU_LIMIT); 647 pp->dbi_base + PCIE_ATU_LIMIT);
645 648
646 writel(ddr_test_region, 649 writel(ddr_test_region,
647 pp->dbi_base + PCIE_ATU_LOWER_TARGET); 650 pp->dbi_base + PCIE_ATU_LOWER_TARGET);
648 writel(0, pp->dbi_base + PCIE_ATU_UPPER_TARGET); 651 writel(0, pp->dbi_base + PCIE_ATU_UPPER_TARGET);
649 writel(PCIE_ATU_TYPE_MEM, pp->dbi_base + PCIE_ATU_CR1); 652 writel(PCIE_ATU_TYPE_MEM, pp->dbi_base + PCIE_ATU_CR1);
650 writel(PCIE_ATU_ENABLE, pp->dbi_base + PCIE_ATU_CR2); 653 writel(PCIE_ATU_ENABLE, pp->dbi_base + PCIE_ATU_CR2);
651 } 654 }
652 } 655 }
653 656
654 static ssize_t imx_pcie_memw_info(struct device *dev, 657 static ssize_t imx_pcie_memw_info(struct device *dev,
655 struct device_attribute *devattr, char *buf) 658 struct device_attribute *devattr, char *buf)
656 { 659 {
657 return sprintf(buf, "imx-pcie-rc-memw-info start 0x%08x, size 0x%08x\n", 660 return sprintf(buf, "imx-pcie-rc-memw-info start 0x%08x, size 0x%08x\n",
658 ddr_test_region, test_region_size); 661 ddr_test_region, test_region_size);
659 } 662 }
660 663
661 static ssize_t 664 static ssize_t
662 imx_pcie_memw_start(struct device *dev, struct device_attribute *attr, 665 imx_pcie_memw_start(struct device *dev, struct device_attribute *attr,
663 const char *buf, size_t count) 666 const char *buf, size_t count)
664 { 667 {
665 u32 memw_start; 668 u32 memw_start;
666 669
667 sscanf(buf, "%x\n", &memw_start); 670 sscanf(buf, "%x\n", &memw_start);
668 671
669 if (memw_start < 0x10000000) { 672 if (memw_start < 0x10000000) {
670 dev_err(dev, "Invalid memory start address.\n"); 673 dev_err(dev, "Invalid memory start address.\n");
671 dev_info(dev, "For example: echo 0x41000000 > /sys/..."); 674 dev_info(dev, "For example: echo 0x41000000 > /sys/...");
672 return -1; 675 return -1;
673 } 676 }
674 677
675 if (ddr_test_region != memw_start) { 678 if (ddr_test_region != memw_start) {
676 ddr_test_region = memw_start; 679 ddr_test_region = memw_start;
677 /* Re-setup the iATU */ 680 /* Re-setup the iATU */
678 imx_pcie_regions_setup(dev); 681 imx_pcie_regions_setup(dev);
679 } 682 }
680 683
681 return count; 684 return count;
682 } 685 }
683 686
684 static ssize_t 687 static ssize_t
685 imx_pcie_memw_size(struct device *dev, struct device_attribute *attr, 688 imx_pcie_memw_size(struct device *dev, struct device_attribute *attr,
686 const char *buf, size_t count) 689 const char *buf, size_t count)
687 { 690 {
688 u32 memw_size; 691 u32 memw_size;
689 692
690 sscanf(buf, "%x\n", &memw_size); 693 sscanf(buf, "%x\n", &memw_size);
691 694
692 if ((memw_size > (SZ_16M - SZ_1M)) || (memw_size < SZ_64K)) { 695 if ((memw_size > (SZ_16M - SZ_1M)) || (memw_size < SZ_64K)) {
693 dev_err(dev, "Invalid, should be [SZ_64K,SZ_16M - SZ_1MB].\n"); 696 dev_err(dev, "Invalid, should be [SZ_64K,SZ_16M - SZ_1MB].\n");
694 dev_info(dev, "For example: echo 0x800000 > /sys/..."); 697 dev_info(dev, "For example: echo 0x800000 > /sys/...");
695 return -1; 698 return -1;
696 } 699 }
697 700
698 if (test_region_size != memw_size) { 701 if (test_region_size != memw_size) {
699 test_region_size = memw_size; 702 test_region_size = memw_size;
700 /* Re-setup the iATU */ 703 /* Re-setup the iATU */
701 imx_pcie_regions_setup(dev); 704 imx_pcie_regions_setup(dev);
702 } 705 }
703 706
704 return count; 707 return count;
705 } 708 }
706 709
707 static DEVICE_ATTR(memw_info, S_IRUGO, imx_pcie_memw_info, NULL); 710 static DEVICE_ATTR(memw_info, S_IRUGO, imx_pcie_memw_info, NULL);
708 static DEVICE_ATTR(memw_start_set, S_IWUGO, NULL, imx_pcie_memw_start); 711 static DEVICE_ATTR(memw_start_set, S_IWUGO, NULL, imx_pcie_memw_start);
709 static DEVICE_ATTR(memw_size_set, S_IWUGO, NULL, imx_pcie_memw_size); 712 static DEVICE_ATTR(memw_size_set, S_IWUGO, NULL, imx_pcie_memw_size);
710 static DEVICE_ATTR(ep_bar0_addr, S_IRWXUGO, imx_pcie_bar0_addr_info, 713 static DEVICE_ATTR(ep_bar0_addr, S_IRWXUGO, imx_pcie_bar0_addr_info,
711 imx_pcie_bar0_addr_start); 714 imx_pcie_bar0_addr_start);
712 715
713 static struct attribute *imx_pcie_attrs[] = { 716 static struct attribute *imx_pcie_attrs[] = {
714 /* 717 /*
715 * The start address, and the limitation (64KB ~ (16MB - 1MB)) 718 * The start address, and the limitation (64KB ~ (16MB - 1MB))
716 * of the ddr mem window reserved by RC, and used for EP to access. 719 * of the ddr mem window reserved by RC, and used for EP to access.
717 * BTW, these attrs are only configured at EP side. 720 * BTW, these attrs are only configured at EP side.
718 */ 721 */
719 &dev_attr_memw_info.attr, 722 &dev_attr_memw_info.attr,
720 &dev_attr_memw_start_set.attr, 723 &dev_attr_memw_start_set.attr,
721 &dev_attr_memw_size_set.attr, 724 &dev_attr_memw_size_set.attr,
722 &dev_attr_ep_bar0_addr.attr, 725 &dev_attr_ep_bar0_addr.attr,
723 NULL 726 NULL
724 }; 727 };
725 728
726 static struct attribute_group imx_pcie_attrgroup = { 729 static struct attribute_group imx_pcie_attrgroup = {
727 .attrs = imx_pcie_attrs, 730 .attrs = imx_pcie_attrs,
728 }; 731 };
729 732
730 static const struct of_device_id imx6_pcie_of_match[] = { 733 static const struct of_device_id imx6_pcie_of_match[] = {
731 { .compatible = "fsl,imx6q-pcie", }, 734 { .compatible = "fsl,imx6q-pcie", },
732 { .compatible = "fsl,imx6sx-pcie", .data = &imx6sx_pcie_data}, 735 { .compatible = "fsl,imx6sx-pcie", .data = &imx6sx_pcie_data},
733 { /* sentinel */ } 736 { /* sentinel */ }
734 }; 737 };
735 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match); 738 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
736 739
737 static void imx6_pcie_setup_ep(struct pcie_port *pp) 740 static void imx6_pcie_setup_ep(struct pcie_port *pp)
738 { 741 {
739 /* CMD reg:I/O space, MEM space, and Bus Master Enable */ 742 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
740 writel(readl(pp->dbi_base + PCI_COMMAND) 743 writel(readl(pp->dbi_base + PCI_COMMAND)
741 | PCI_COMMAND_IO 744 | PCI_COMMAND_IO
742 | PCI_COMMAND_MEMORY 745 | PCI_COMMAND_MEMORY
743 | PCI_COMMAND_MASTER, 746 | PCI_COMMAND_MASTER,
744 pp->dbi_base + PCI_COMMAND); 747 pp->dbi_base + PCI_COMMAND);
745 748
746 /* 749 /*
747 * configure the class_rev(emaluate one memory ram ep device), 750 * configure the class_rev(emaluate one memory ram ep device),
748 * bar0 and bar1 of ep 751 * bar0 and bar1 of ep
749 */ 752 */
750 writel(0xdeadbeaf, pp->dbi_base + PCI_VENDOR_ID); 753 writel(0xdeadbeaf, pp->dbi_base + PCI_VENDOR_ID);
751 writel(readl(pp->dbi_base + PCI_CLASS_REVISION) 754 writel(readl(pp->dbi_base + PCI_CLASS_REVISION)
752 | (PCI_CLASS_MEMORY_RAM << 16), 755 | (PCI_CLASS_MEMORY_RAM << 16),
753 pp->dbi_base + PCI_CLASS_REVISION); 756 pp->dbi_base + PCI_CLASS_REVISION);
754 writel(0xdeadbeaf, pp->dbi_base 757 writel(0xdeadbeaf, pp->dbi_base
755 + PCI_SUBSYSTEM_VENDOR_ID); 758 + PCI_SUBSYSTEM_VENDOR_ID);
756 759
757 /* 32bit none-prefetchable 8M bytes memory on bar0 */ 760 /* 32bit none-prefetchable 8M bytes memory on bar0 */
758 writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_0); 761 writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_0);
759 writel(SZ_8M - 1, pp->dbi_base + (1 << 12) 762 writel(SZ_8M - 1, pp->dbi_base + (1 << 12)
760 + PCI_BASE_ADDRESS_0); 763 + PCI_BASE_ADDRESS_0);
761 764
762 /* None used bar1 */ 765 /* None used bar1 */
763 writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_1); 766 writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_1);
764 writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_1); 767 writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_1);
765 768
766 /* 4K bytes IO on bar2 */ 769 /* 4K bytes IO on bar2 */
767 writel(0x1, pp->dbi_base + PCI_BASE_ADDRESS_2); 770 writel(0x1, pp->dbi_base + PCI_BASE_ADDRESS_2);
768 writel(SZ_4K - 1, pp->dbi_base + (1 << 12) + 771 writel(SZ_4K - 1, pp->dbi_base + (1 << 12) +
769 PCI_BASE_ADDRESS_2); 772 PCI_BASE_ADDRESS_2);
770 773
771 /* 774 /*
772 * 32bit prefetchable 1M bytes memory on bar3 775 * 32bit prefetchable 1M bytes memory on bar3
773 * FIXME BAR MASK3 is not changable, the size 776 * FIXME BAR MASK3 is not changable, the size
774 * is fixed to 256 bytes. 777 * is fixed to 256 bytes.
775 */ 778 */
776 writel(0x8, pp->dbi_base + PCI_BASE_ADDRESS_3); 779 writel(0x8, pp->dbi_base + PCI_BASE_ADDRESS_3);
777 writel(SZ_1M - 1, pp->dbi_base + (1 << 12) 780 writel(SZ_1M - 1, pp->dbi_base + (1 << 12)
778 + PCI_BASE_ADDRESS_3); 781 + PCI_BASE_ADDRESS_3);
779 782
780 /* 783 /*
781 * 64bit prefetchable 1M bytes memory on bar4-5. 784 * 64bit prefetchable 1M bytes memory on bar4-5.
782 * FIXME BAR4,5 are not enabled yet 785 * FIXME BAR4,5 are not enabled yet
783 */ 786 */
784 writel(0xc, pp->dbi_base + PCI_BASE_ADDRESS_4); 787 writel(0xc, pp->dbi_base + PCI_BASE_ADDRESS_4);
785 writel(SZ_1M - 1, pp->dbi_base + (1 << 12) 788 writel(SZ_1M - 1, pp->dbi_base + (1 << 12)
786 + PCI_BASE_ADDRESS_4); 789 + PCI_BASE_ADDRESS_4);
787 writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_5); 790 writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_5);
788 } 791 }
789 792
790 #ifdef CONFIG_PM_SLEEP 793 #ifdef CONFIG_PM_SLEEP
791 static int pci_imx_suspend_noirq(struct device *dev) 794 static int pci_imx_suspend_noirq(struct device *dev)
792 { 795 {
793 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 796 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
794 struct pcie_port *pp = &imx6_pcie->pp; 797 struct pcie_port *pp = &imx6_pcie->pp;
795 798
796 if (is_imx6sx_pcie(imx6_pcie)) { 799 if (is_imx6sx_pcie(imx6_pcie)) {
797 if (IS_ENABLED(CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE)) { 800 if (IS_ENABLED(CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE)) {
798 if (IS_ENABLED(CONFIG_PCI_MSI)) 801 if (IS_ENABLED(CONFIG_PCI_MSI))
799 dw_pcie_msi_cfg_save(pp); 802 dw_pcie_msi_cfg_save(pp);
800 803
801 /* Disable clks and power down PCIe PHY */ 804 /* Disable clks and power down PCIe PHY */
802 clk_disable_unprepare(imx6_pcie->pcie_axi); 805 clk_disable_unprepare(imx6_pcie->pcie_axi);
803 if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS) 806 if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
804 && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) 807 && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
805 clk_disable_unprepare(imx6_pcie->lvds_gate); 808 clk_disable_unprepare(imx6_pcie->lvds_gate);
806 clk_disable_unprepare(imx6_pcie->pcie_ref_125m); 809 clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
807 clk_disable_unprepare(imx6_pcie->dis_axi); 810 clk_disable_unprepare(imx6_pcie->dis_axi);
808 release_bus_freq(BUS_FREQ_HIGH); 811 release_bus_freq(BUS_FREQ_HIGH);
809 812
810 /* Put PCIe PHY to be isolation */ 813 /* Put PCIe PHY to be isolation */
811 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR0, 814 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR0,
812 BIT(6), 1 << 6); 815 BIT(6), 1 << 6);
813 816
814 /* 817 /*
815 * Power down PCIe PHY. 818 * Power down PCIe PHY.
816 */ 819 */
817 regulator_disable(imx6_pcie->pcie_phy_reg); 820 regulator_disable(imx6_pcie->pcie_phy_reg);
818 regulator_disable(imx6_pcie->pcie_reg); 821 regulator_disable(imx6_pcie->pcie_reg);
819 } else { 822 } else {
820 if (IS_ENABLED(CONFIG_PCI_MSI)) 823 if (IS_ENABLED(CONFIG_PCI_MSI))
821 dw_pcie_msi_cfg_save(pp); 824 dw_pcie_msi_cfg_save(pp);
822 825
823 /* PM_TURN_OFF */ 826 /* PM_TURN_OFF */
824 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 827 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
825 BIT(16), 1 << 16); 828 BIT(16), 1 << 16);
826 udelay(10); 829 udelay(10);
827 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 830 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
828 BIT(16), 0 << 16); 831 BIT(16), 0 << 16);
829 clk_disable_unprepare(imx6_pcie->pcie_axi); 832 clk_disable_unprepare(imx6_pcie->pcie_axi);
830 clk_disable_unprepare(imx6_pcie->lvds_gate); 833 clk_disable_unprepare(imx6_pcie->lvds_gate);
831 clk_disable_unprepare(imx6_pcie->pcie_ref_125m); 834 clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
832 clk_disable_unprepare(imx6_pcie->dis_axi); 835 clk_disable_unprepare(imx6_pcie->dis_axi);
833 release_bus_freq(BUS_FREQ_HIGH); 836 release_bus_freq(BUS_FREQ_HIGH);
834 } 837 }
835 } 838 }
836 839
837 return 0; 840 return 0;
838 } 841 }
839 842
840 static int pci_imx_resume_noirq(struct device *dev) 843 static int pci_imx_resume_noirq(struct device *dev)
841 { 844 {
842 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 845 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
843 struct pcie_port *pp = &imx6_pcie->pp; 846 struct pcie_port *pp = &imx6_pcie->pp;
844 847
845 if (is_imx6sx_pcie(imx6_pcie)) { 848 if (is_imx6sx_pcie(imx6_pcie)) {
846 if (IS_ENABLED(CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE)) { 849 if (IS_ENABLED(CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE)) {
847 /* Power up PCIe PHY, and so on again */ 850 /* Power up PCIe PHY, and so on again */
848 imx6_pcie_init_phy(pp); 851 imx6_pcie_init_phy(pp);
849 imx6_pcie_deassert_core_reset(pp); 852 imx6_pcie_deassert_core_reset(pp);
850 853
851 /* 854 /*
852 * iMX6SX PCIe has the stand-alone power domain. 855 * iMX6SX PCIe has the stand-alone power domain.
853 * refer to the initialization for iMX6SX PCIe, 856 * refer to the initialization for iMX6SX PCIe,
854 * release the PCIe PHY reset here, 857 * release the PCIe PHY reset here,
855 * before LTSSM enable is set 858 * before LTSSM enable is set
856 * . 859 * .
857 */ 860 */
858 regmap_update_bits(imx6_pcie->iomuxc_gpr, 861 regmap_update_bits(imx6_pcie->iomuxc_gpr,
859 IOMUXC_GPR5, BIT(19), 0 << 19); 862 IOMUXC_GPR5, BIT(19), 0 << 19);
860 863
861 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) { 864 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
862 imx6_pcie_setup_ep(pp); 865 imx6_pcie_setup_ep(pp);
863 } else { 866 } else {
864 /* 867 /*
865 * CMD reg:I/O space, MEM space, 868 * CMD reg:I/O space, MEM space,
866 * and Bus Master 869 * and Bus Master
867 */ 870 */
868 writel(readl(pp->dbi_base + PCI_COMMAND) 871 writel(readl(pp->dbi_base + PCI_COMMAND)
869 | PCI_COMMAND_IO 872 | PCI_COMMAND_IO
870 | PCI_COMMAND_MEMORY 873 | PCI_COMMAND_MEMORY
871 | PCI_COMMAND_MASTER, 874 | PCI_COMMAND_MASTER,
872 pp->dbi_base + PCI_COMMAND); 875 pp->dbi_base + PCI_COMMAND);
873 /* 876 /*
874 * Set the CLASS_REV of RC CFG header to 877 * Set the CLASS_REV of RC CFG header to
875 * PCI_CLASS_BRIDGE_PCI 878 * PCI_CLASS_BRIDGE_PCI
876 */ 879 */
877 writel(readl(pp->dbi_base + PCI_CLASS_REVISION) 880 writel(readl(pp->dbi_base + PCI_CLASS_REVISION)
878 | (PCI_CLASS_BRIDGE_PCI << 16), 881 | (PCI_CLASS_BRIDGE_PCI << 16),
879 pp->dbi_base + PCI_CLASS_REVISION); 882 pp->dbi_base + PCI_CLASS_REVISION);
880 } 883 }
881 884
882 if (IS_ENABLED(CONFIG_PCI_MSI)) 885 if (IS_ENABLED(CONFIG_PCI_MSI))
883 dw_pcie_msi_cfg_restore(pp); 886 dw_pcie_msi_cfg_restore(pp);
884 887
885 /* assert LTSSM enable */ 888 /* assert LTSSM enable */
886 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 889 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
887 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); 890 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
888 } else { 891 } else {
889 request_bus_freq(BUS_FREQ_HIGH); 892 request_bus_freq(BUS_FREQ_HIGH);
890 clk_prepare_enable(imx6_pcie->dis_axi); 893 clk_prepare_enable(imx6_pcie->dis_axi);
891 clk_prepare_enable(imx6_pcie->lvds_gate); 894 clk_prepare_enable(imx6_pcie->lvds_gate);
892 clk_prepare_enable(imx6_pcie->pcie_ref_125m); 895 clk_prepare_enable(imx6_pcie->pcie_ref_125m);
893 clk_prepare_enable(imx6_pcie->pcie_axi); 896 clk_prepare_enable(imx6_pcie->pcie_axi);
894 897
895 /* Reset iMX6SX PCIe */ 898 /* Reset iMX6SX PCIe */
896 regmap_update_bits(imx6_pcie->iomuxc_gpr, 899 regmap_update_bits(imx6_pcie->iomuxc_gpr,
897 IOMUXC_GPR5, BIT(18), 1 << 18); 900 IOMUXC_GPR5, BIT(18), 1 << 18);
898 901
899 regmap_update_bits(imx6_pcie->iomuxc_gpr, 902 regmap_update_bits(imx6_pcie->iomuxc_gpr,
900 IOMUXC_GPR5, BIT(18), 0 << 18); 903 IOMUXC_GPR5, BIT(18), 0 << 18);
901 /* 904 /*
902 * controller maybe turn off, re-configure again 905 * controller maybe turn off, re-configure again
903 */ 906 */
904 writel(readl(pp->dbi_base + PCI_CLASS_REVISION) 907 writel(readl(pp->dbi_base + PCI_CLASS_REVISION)
905 | (PCI_CLASS_BRIDGE_PCI << 16), 908 | (PCI_CLASS_BRIDGE_PCI << 16),
906 pp->dbi_base + PCI_CLASS_REVISION); 909 pp->dbi_base + PCI_CLASS_REVISION);
907 dw_pcie_setup_rc(pp); 910 dw_pcie_setup_rc(pp);
908 911
909 if (IS_ENABLED(CONFIG_PCI_MSI)) 912 if (IS_ENABLED(CONFIG_PCI_MSI))
910 dw_pcie_msi_cfg_restore(pp); 913 dw_pcie_msi_cfg_restore(pp);
911 } 914 }
912 } 915 }
913 916
914 return 0; 917 return 0;
915 } 918 }
916 919
917 static const struct dev_pm_ops pci_imx_pm_ops = { 920 static const struct dev_pm_ops pci_imx_pm_ops = {
918 .suspend_noirq = pci_imx_suspend_noirq, 921 .suspend_noirq = pci_imx_suspend_noirq,
919 .resume_noirq = pci_imx_resume_noirq, 922 .resume_noirq = pci_imx_resume_noirq,
920 .freeze_noirq = pci_imx_suspend_noirq, 923 .freeze_noirq = pci_imx_suspend_noirq,
921 .thaw_noirq = pci_imx_resume_noirq, 924 .thaw_noirq = pci_imx_resume_noirq,
922 .poweroff_noirq = pci_imx_suspend_noirq, 925 .poweroff_noirq = pci_imx_suspend_noirq,
923 .restore_noirq = pci_imx_resume_noirq, }; 926 .restore_noirq = pci_imx_resume_noirq, };
924 #else 927 #else
925 static const struct dev_pm_ops pci_imx_pm_ops = { }; 928 static const struct dev_pm_ops pci_imx_pm_ops = { };
926 #endif 929 #endif
927 930
928 static int __init imx6_pcie_probe(struct platform_device *pdev) 931 static int __init imx6_pcie_probe(struct platform_device *pdev)
929 { 932 {
930 struct pcie_port *pp; 933 struct pcie_port *pp;
931 const struct of_device_id *of_id = 934 const struct of_device_id *of_id =
932 of_match_device(imx6_pcie_of_match, &pdev->dev); 935 of_match_device(imx6_pcie_of_match, &pdev->dev);
933 struct device_node *np = pdev->dev.of_node; 936 struct device_node *np = pdev->dev.of_node;
934 struct resource *dbi_base; 937 struct resource *dbi_base;
935 int ret, i; 938 int ret, i;
936 void *test_reg1, *test_reg2; 939 void *test_reg1, *test_reg2;
937 void __iomem *pcie_arb_base_addr; 940 void __iomem *pcie_arb_base_addr;
938 struct timeval tv1, tv2, tv3; 941 struct timeval tv1, tv2, tv3;
939 u32 tv_count1, tv_count2; 942 u32 tv_count1, tv_count2;
940 943
941 imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL); 944 imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
942 if (!imx6_pcie) 945 if (!imx6_pcie)
943 return -ENOMEM; 946 return -ENOMEM;
944 947
945 pp = &imx6_pcie->pp; 948 pp = &imx6_pcie->pp;
946 pp->dev = &pdev->dev; 949 pp->dev = &pdev->dev;
947 imx6_pcie->data = of_id->data; 950 imx6_pcie->data = of_id->data;
948 951
949 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) { 952 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
950 /* add attributes for device */ 953 /* add attributes for device */
951 ret = sysfs_create_group(&pdev->dev.kobj, &imx_pcie_attrgroup); 954 ret = sysfs_create_group(&pdev->dev.kobj, &imx_pcie_attrgroup);
952 if (ret) 955 if (ret)
953 return -EINVAL; 956 return -EINVAL;
954 } 957 }
955 958
956 /* Added for PCI abort handling */ 959 /* Added for PCI abort handling */
957 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, 960 hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
958 "imprecise external abort"); 961 "imprecise external abort");
959 962
960 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 963 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
961 if (!dbi_base) { 964 if (!dbi_base) {
962 dev_err(&pdev->dev, "dbi_base memory resource not found\n"); 965 dev_err(&pdev->dev, "dbi_base memory resource not found\n");
963 return -ENODEV; 966 return -ENODEV;
964 } 967 }
965 968
966 pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); 969 pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
967 if (IS_ERR(pp->dbi_base)) { 970 if (IS_ERR(pp->dbi_base)) {
968 ret = PTR_ERR(pp->dbi_base); 971 ret = PTR_ERR(pp->dbi_base);
969 goto err; 972 goto err;
970 } 973 }
971 974
972 /* Fetch GPIOs */ 975 /* Fetch GPIOs */
973 imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); 976 imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
974 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 977 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
975 ret = devm_gpio_request_one(&pdev->dev, 978 ret = devm_gpio_request_one(&pdev->dev,
976 imx6_pcie->reset_gpio, 979 imx6_pcie->reset_gpio,
977 GPIOF_OUT_INIT_LOW, 980 GPIOF_OUT_INIT_LOW,
978 "PCIe reset"); 981 "PCIe reset");
979 if (ret) { 982 if (ret) {
980 dev_err(&pdev->dev, "unable to get reset gpio\n"); 983 dev_err(&pdev->dev, "unable to get reset gpio\n");
981 goto err; 984 goto err;
982 } 985 }
983 } 986 }
984 987
985 imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0); 988 imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
986 if (gpio_is_valid(imx6_pcie->power_on_gpio)) { 989 if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
987 ret = devm_gpio_request_one(&pdev->dev, 990 ret = devm_gpio_request_one(&pdev->dev,
988 imx6_pcie->power_on_gpio, 991 imx6_pcie->power_on_gpio,
989 GPIOF_OUT_INIT_LOW, 992 GPIOF_OUT_INIT_LOW,
990 "PCIe power enable"); 993 "PCIe power enable");
991 if (ret) { 994 if (ret) {
992 dev_err(&pdev->dev, "unable to get power-on gpio\n"); 995 dev_err(&pdev->dev, "unable to get power-on gpio\n");
993 goto err; 996 goto err;
994 } 997 }
995 } 998 }
996 999
997 imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0); 1000 imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
998 if (gpio_is_valid(imx6_pcie->wake_up_gpio)) { 1001 if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
999 ret = devm_gpio_request_one(&pdev->dev, 1002 ret = devm_gpio_request_one(&pdev->dev,
1000 imx6_pcie->wake_up_gpio, 1003 imx6_pcie->wake_up_gpio,
1001 GPIOF_IN, 1004 GPIOF_IN,
1002 "PCIe wake up"); 1005 "PCIe wake up");
1003 if (ret) { 1006 if (ret) {
1004 dev_err(&pdev->dev, "unable to get wake-up gpio\n"); 1007 dev_err(&pdev->dev, "unable to get wake-up gpio\n");
1005 goto err; 1008 goto err;
1006 } 1009 }
1007 } 1010 }
1008 1011
1009 imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0); 1012 imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
1010 if (gpio_is_valid(imx6_pcie->disable_gpio)) { 1013 if (gpio_is_valid(imx6_pcie->disable_gpio)) {
1011 ret = devm_gpio_request_one(&pdev->dev, 1014 ret = devm_gpio_request_one(&pdev->dev,
1012 imx6_pcie->disable_gpio, 1015 imx6_pcie->disable_gpio,
1013 GPIOF_OUT_INIT_HIGH, 1016 GPIOF_OUT_INIT_HIGH,
1014 "PCIe disable endpoint"); 1017 "PCIe disable endpoint");
1015 if (ret) { 1018 if (ret) {
1016 dev_err(&pdev->dev, "unable to get disable-ep gpio\n"); 1019 dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
1017 goto err; 1020 goto err;
1018 } 1021 }
1019 } 1022 }
1020 1023
1021 /* Fetch clocks */ 1024 /* Fetch clocks */
1022 imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate"); 1025 imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
1023 if (IS_ERR(imx6_pcie->lvds_gate)) { 1026 if (IS_ERR(imx6_pcie->lvds_gate)) {
1024 dev_err(&pdev->dev, 1027 dev_err(&pdev->dev,
1025 "lvds_gate clock select missing or invalid\n"); 1028 "lvds_gate clock select missing or invalid\n");
1026 ret = PTR_ERR(imx6_pcie->lvds_gate); 1029 ret = PTR_ERR(imx6_pcie->lvds_gate);
1027 goto err; 1030 goto err;
1028 } 1031 }
1029 1032
1030 imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m"); 1033 imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
1031 if (IS_ERR(imx6_pcie->pcie_ref_125m)) { 1034 if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
1032 dev_err(&pdev->dev, 1035 dev_err(&pdev->dev,
1033 "pcie_ref_125m clock source missing or invalid\n"); 1036 "pcie_ref_125m clock source missing or invalid\n");
1034 ret = PTR_ERR(imx6_pcie->pcie_ref_125m); 1037 ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
1035 goto err; 1038 goto err;
1036 } 1039 }
1037 1040
1038 imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi"); 1041 imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
1039 if (IS_ERR(imx6_pcie->pcie_axi)) { 1042 if (IS_ERR(imx6_pcie->pcie_axi)) {
1040 dev_err(&pdev->dev, 1043 dev_err(&pdev->dev,
1041 "pcie_axi clock source missing or invalid\n"); 1044 "pcie_axi clock source missing or invalid\n");
1042 ret = PTR_ERR(imx6_pcie->pcie_axi); 1045 ret = PTR_ERR(imx6_pcie->pcie_axi);
1043 goto err; 1046 goto err;
1044 } 1047 }
1045 1048
1046 if (is_imx6sx_pcie(imx6_pcie)) { 1049 if (is_imx6sx_pcie(imx6_pcie)) {
1047 imx6_pcie->dis_axi = devm_clk_get(&pdev->dev, "display_axi"); 1050 imx6_pcie->dis_axi = devm_clk_get(&pdev->dev, "display_axi");
1048 if (IS_ERR(imx6_pcie->dis_axi)) { 1051 if (IS_ERR(imx6_pcie->dis_axi)) {
1049 dev_err(&pdev->dev, 1052 dev_err(&pdev->dev,
1050 "dis_axi clock source missing or invalid\n"); 1053 "dis_axi clock source missing or invalid\n");
1051 ret = PTR_ERR(imx6_pcie->dis_axi); 1054 ret = PTR_ERR(imx6_pcie->dis_axi);
1052 goto err; 1055 goto err;
1053 } 1056 }
1054 1057
1055 /* Get pcie regulator */ 1058 /* Get pcie regulator */
1056 imx6_pcie->pcie_reg = devm_regulator_get(pp->dev, "disp"); 1059 imx6_pcie->pcie_reg = devm_regulator_get(pp->dev, "disp");
1057 if (IS_ERR(imx6_pcie->pcie_reg)) { 1060 if (IS_ERR(imx6_pcie->pcie_reg)) {
1058 dev_err(&pdev->dev, "pcie regulator not ready\n"); 1061 dev_err(&pdev->dev, "pcie regulator not ready\n");
1059 imx6_pcie->pcie_reg = NULL; 1062 imx6_pcie->pcie_reg = NULL;
1060 } 1063 }
1061 imx6_pcie->pcie_phy_reg = devm_regulator_get(pp->dev, "pcie"); 1064 imx6_pcie->pcie_phy_reg = devm_regulator_get(pp->dev, "pcie");
1062 if (IS_ERR(imx6_pcie->pcie_phy_reg)) { 1065 if (IS_ERR(imx6_pcie->pcie_phy_reg)) {
1063 dev_err(&pdev->dev, "pcie phy regulator not ready\n"); 1066 dev_err(&pdev->dev, "pcie phy regulator not ready\n");
1064 imx6_pcie->pcie_phy_reg = NULL; 1067 imx6_pcie->pcie_phy_reg = NULL;
1065 } 1068 }
1066 1069
1067 /* Grab GPR config register range */ 1070 /* Grab GPR config register range */
1068 imx6_pcie->iomuxc_gpr = 1071 imx6_pcie->iomuxc_gpr =
1069 syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr"); 1072 syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
1070 } else { 1073 } else {
1071 /* sata_ref is not used by pcie on imx6sx */ 1074 /* sata_ref is not used by pcie on imx6sx */
1072 imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m"); 1075 imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
1073 if (IS_ERR(imx6_pcie->sata_ref_100m)) { 1076 if (IS_ERR(imx6_pcie->sata_ref_100m)) {
1074 dev_err(&pdev->dev, 1077 dev_err(&pdev->dev,
1075 "sata_ref_100m clock source missing or invalid\n"); 1078 "sata_ref_100m clock source missing or invalid\n");
1076 ret = PTR_ERR(imx6_pcie->sata_ref_100m); 1079 ret = PTR_ERR(imx6_pcie->sata_ref_100m);
1077 goto err; 1080 goto err;
1078 } 1081 }
1079 1082
1080 /* Grab GPR config register range */ 1083 /* Grab GPR config register range */
1081 imx6_pcie->iomuxc_gpr = 1084 imx6_pcie->iomuxc_gpr =
1082 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 1085 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1083 } 1086 }
1084 1087
1085 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { 1088 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1086 dev_err(&pdev->dev, "unable to find iomuxc registers\n"); 1089 dev_err(&pdev->dev, "unable to find iomuxc registers\n");
1087 ret = PTR_ERR(imx6_pcie->iomuxc_gpr); 1090 ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
1088 goto err; 1091 goto err;
1089 } 1092 }
1090 1093
1091 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) { 1094 if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
1092 struct device_node *np = pp->dev->of_node; 1095 struct device_node *np = pp->dev->of_node;
1093 struct of_pci_range range; 1096 struct of_pci_range range;
1094 struct of_pci_range_parser parser; 1097 struct of_pci_range_parser parser;
1095 unsigned long restype; 1098 unsigned long restype;
1096 1099
1097 if (of_pci_range_parser_init(&parser, np)) { 1100 if (of_pci_range_parser_init(&parser, np)) {
1098 dev_err(pp->dev, "missing ranges property\n"); 1101 dev_err(pp->dev, "missing ranges property\n");
1099 return -EINVAL; 1102 return -EINVAL;
1100 } 1103 }
1101 1104
1102 /* Get the memory ranges from DT */ 1105 /* Get the memory ranges from DT */
1103 for_each_of_pci_range(&parser, &range) { 1106 for_each_of_pci_range(&parser, &range) {
1104 restype = range.flags & IORESOURCE_TYPE_BITS; 1107 restype = range.flags & IORESOURCE_TYPE_BITS;
1105 if (restype == IORESOURCE_MEM) { 1108 if (restype == IORESOURCE_MEM) {
1106 of_pci_range_to_resource(&range, 1109 of_pci_range_to_resource(&range,
1107 np, &pp->mem); 1110 np, &pp->mem);
1108 pp->mem.name = "MEM"; 1111 pp->mem.name = "MEM";
1109 } 1112 }
1110 } 1113 }
1111 1114
1112 pp->mem_base = pp->mem.start; 1115 pp->mem_base = pp->mem.start;
1113 if (IS_ENABLED(CONFIG_EP_SELF_IO_TEST)) { 1116 if (IS_ENABLED(CONFIG_EP_SELF_IO_TEST)) {
1114 /* Prepare the test regions and data */ 1117 /* Prepare the test regions and data */
1115 test_reg1 = devm_kzalloc(&pdev->dev, 1118 test_reg1 = devm_kzalloc(&pdev->dev,
1116 test_region_size, GFP_KERNEL); 1119 test_region_size, GFP_KERNEL);
1117 if (!test_reg1) { 1120 if (!test_reg1) {
1118 pr_err("pcie ep: can't alloc the test reg1.\n"); 1121 pr_err("pcie ep: can't alloc the test reg1.\n");
1119 ret = PTR_ERR(test_reg1); 1122 ret = PTR_ERR(test_reg1);
1120 goto err; 1123 goto err;
1121 } 1124 }
1122 1125
1123 test_reg2 = devm_kzalloc(&pdev->dev, 1126 test_reg2 = devm_kzalloc(&pdev->dev,
1124 test_region_size, GFP_KERNEL); 1127 test_region_size, GFP_KERNEL);
1125 if (!test_reg2) { 1128 if (!test_reg2) {
1126 pr_err("pcie ep: can't alloc the test reg2.\n"); 1129 pr_err("pcie ep: can't alloc the test reg2.\n");
1127 ret = PTR_ERR(test_reg1); 1130 ret = PTR_ERR(test_reg1);
1128 goto err; 1131 goto err;
1129 } 1132 }
1130 1133
1131 pcie_arb_base_addr = ioremap_cached(pp->mem_base, 1134 pcie_arb_base_addr = ioremap_cached(pp->mem_base,
1132 test_region_size); 1135 test_region_size);
1133 1136
1134 if (!pcie_arb_base_addr) { 1137 if (!pcie_arb_base_addr) {
1135 pr_err("error with ioremap in ep selftest\n"); 1138 pr_err("error with ioremap in ep selftest\n");
1136 ret = PTR_ERR(pcie_arb_base_addr); 1139 ret = PTR_ERR(pcie_arb_base_addr);
1137 goto err; 1140 goto err;
1138 } 1141 }
1139 1142
1140 for (i = 0; i < test_region_size; i = i + 4) { 1143 for (i = 0; i < test_region_size; i = i + 4) {
1141 writel(0xE6600D00 + i, test_reg1 + i); 1144 writel(0xE6600D00 + i, test_reg1 + i);
1142 writel(0xDEADBEAF, test_reg2 + i); 1145 writel(0xDEADBEAF, test_reg2 + i);
1143 } 1146 }
1144 } 1147 }
1145 1148
1146 imx6_pcie_init_phy(pp); 1149 imx6_pcie_init_phy(pp);
1147 1150
1148 imx6_pcie_deassert_core_reset(pp); 1151 imx6_pcie_deassert_core_reset(pp);
1149 1152
1150 /* 1153 /*
1151 * iMX6SX PCIe has the stand-alone power domain. 1154 * iMX6SX PCIe has the stand-alone power domain.
1152 * refer to the initialization for iMX6SX PCIe, 1155 * refer to the initialization for iMX6SX PCIe,
1153 * release the PCIe PHY reset here, 1156 * release the PCIe PHY reset here,
1154 * before LTSSM enable is set 1157 * before LTSSM enable is set
1155 * . 1158 * .
1156 */ 1159 */
1157 if (is_imx6sx_pcie(imx6_pcie)) 1160 if (is_imx6sx_pcie(imx6_pcie))
1158 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 1161 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
1159 BIT(19), 0 << 19); 1162 BIT(19), 0 << 19);
1160 1163
1161 /* assert LTSSM enable */ 1164 /* assert LTSSM enable */
1162 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1165 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
1163 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); 1166 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
1164 1167
1165 dev_info(&pdev->dev, "PCIe EP: waiting for link up...\n"); 1168 dev_info(&pdev->dev, "PCIe EP: waiting for link up...\n");
1166 1169
1167 platform_set_drvdata(pdev, imx6_pcie); 1170 platform_set_drvdata(pdev, imx6_pcie);
1168 /* link is indicated by the bit4 of DB_R1 register */ 1171 /* link is indicated by the bit4 of DB_R1 register */
1169 do { 1172 do {
1170 usleep_range(10, 20); 1173 usleep_range(10, 20);
1171 } while ((readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & 0x10) == 0); 1174 } while ((readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & 0x10) == 0);
1172 1175
1173 imx6_pcie_setup_ep(pp); 1176 imx6_pcie_setup_ep(pp);
1174 1177
1175 /* Re-setup the iATU */ 1178 /* Re-setup the iATU */
1176 imx_pcie_regions_setup(&pdev->dev); 1179 imx_pcie_regions_setup(&pdev->dev);
1177 1180
1178 if (IS_ENABLED(CONFIG_EP_SELF_IO_TEST)) { 1181 if (IS_ENABLED(CONFIG_EP_SELF_IO_TEST)) {
1179 /* PCIe EP start the data transfer after link up */ 1182 /* PCIe EP start the data transfer after link up */
1180 pr_info("pcie ep: Starting data transfer...\n"); 1183 pr_info("pcie ep: Starting data transfer...\n");
1181 do_gettimeofday(&tv1); 1184 do_gettimeofday(&tv1);
1182 1185
1183 memcpy((unsigned long *)pcie_arb_base_addr, 1186 memcpy((unsigned long *)pcie_arb_base_addr,
1184 (unsigned long *)test_reg1, 1187 (unsigned long *)test_reg1,
1185 test_region_size); 1188 test_region_size);
1186 1189
1187 do_gettimeofday(&tv2); 1190 do_gettimeofday(&tv2);
1188 1191
1189 memcpy((unsigned long *)test_reg2, 1192 memcpy((unsigned long *)test_reg2,
1190 (unsigned long *)pcie_arb_base_addr, 1193 (unsigned long *)pcie_arb_base_addr,
1191 test_region_size); 1194 test_region_size);
1192 1195
1193 do_gettimeofday(&tv3); 1196 do_gettimeofday(&tv3);
1194 1197
1195 if (memcmp(test_reg2, test_reg1, test_region_size) == 0) { 1198 if (memcmp(test_reg2, test_reg1, test_region_size) == 0) {
1196 tv_count1 = (tv2.tv_sec - tv1.tv_sec) 1199 tv_count1 = (tv2.tv_sec - tv1.tv_sec)
1197 * USEC_PER_SEC 1200 * USEC_PER_SEC
1198 + tv2.tv_usec - tv1.tv_usec; 1201 + tv2.tv_usec - tv1.tv_usec;
1199 tv_count2 = (tv3.tv_sec - tv2.tv_sec) 1202 tv_count2 = (tv3.tv_sec - tv2.tv_sec)
1200 * USEC_PER_SEC 1203 * USEC_PER_SEC
1201 + tv3.tv_usec - tv2.tv_usec; 1204 + tv3.tv_usec - tv2.tv_usec;
1202 1205
1203 pr_info("pcie ep: Data transfer is successful." 1206 pr_info("pcie ep: Data transfer is successful."
1204 " tv_count1 %dus," 1207 " tv_count1 %dus,"
1205 " tv_count2 %dus.\n", 1208 " tv_count2 %dus.\n",
1206 tv_count1, tv_count2); 1209 tv_count1, tv_count2);
1207 pr_info("pcie ep: Data write speed:%ldMB/s.\n", 1210 pr_info("pcie ep: Data write speed:%ldMB/s.\n",
1208 ((test_region_size/1024) 1211 ((test_region_size/1024)
1209 * MSEC_PER_SEC) 1212 * MSEC_PER_SEC)
1210 /(tv_count1)); 1213 /(tv_count1));
1211 pr_info("pcie ep: Data read speed:%ldMB/s.\n", 1214 pr_info("pcie ep: Data read speed:%ldMB/s.\n",
1212 ((test_region_size/1024) 1215 ((test_region_size/1024)
1213 * MSEC_PER_SEC) 1216 * MSEC_PER_SEC)
1214 /(tv_count2)); 1217 /(tv_count2));
1215 } else { 1218 } else {
1216 pr_info("pcie ep: Data transfer is failed.\n"); 1219 pr_info("pcie ep: Data transfer is failed.\n");
1217 } 1220 }
1218 } 1221 }
1219 } else { 1222 } else {
1220 ret = imx6_add_pcie_port(pp, pdev); 1223 ret = imx6_add_pcie_port(pp, pdev);
1221 if (ret < 0) 1224 if (ret < 0)
1222 goto err; 1225 goto err;
1223 1226
1224 platform_set_drvdata(pdev, imx6_pcie); 1227 platform_set_drvdata(pdev, imx6_pcie);
1225 1228
1226 /* Re-setup the iATU */ 1229 /* Re-setup the iATU */
1227 imx_pcie_regions_setup(&pdev->dev); 1230 imx_pcie_regions_setup(&pdev->dev);
1228 } 1231 }
1229 1232
1230 return 0; 1233 return 0;
1231 1234
1232 err: 1235 err:
1233 return ret; 1236 return ret;
1234 } 1237 }
1235 1238
1236 static struct platform_driver imx6_pcie_driver = { 1239 static struct platform_driver imx6_pcie_driver = {
1237 .driver = { 1240 .driver = {
1238 .name = "imx6q-pcie", 1241 .name = "imx6q-pcie",
1239 .owner = THIS_MODULE, 1242 .owner = THIS_MODULE,
1240 .of_match_table = imx6_pcie_of_match, 1243 .of_match_table = imx6_pcie_of_match,
1241 .pm = &pci_imx_pm_ops, 1244 .pm = &pci_imx_pm_ops,
1242 }, 1245 },
1243 }; 1246 };
1244 1247
1245 /* Freescale PCIe driver does not allow module unload */ 1248 /* Freescale PCIe driver does not allow module unload */
1246 1249
1247 static int __init imx6_pcie_init(void) 1250 static int __init imx6_pcie_init(void)
1248 { 1251 {
1249 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); 1252 return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
1250 } 1253 }
1251 fs_initcall(imx6_pcie_init); 1254 fs_initcall(imx6_pcie_init);
1252 1255
1253 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); 1256 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
1254 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); 1257 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
1255 MODULE_LICENSE("GPL v2"); 1258 MODULE_LICENSE("GPL v2");
1256 1259
drivers/power/Kconfig
Diff comments   View file @ 8f7b130
1 menuconfig POWER_SUPPLY 1 menuconfig POWER_SUPPLY
2 bool "Power supply class support" 2 bool "Power supply class support"
3 help 3 help
4 Say Y here to enable power supply class support. This allows 4 Say Y here to enable power supply class support. This allows
5 power supply (batteries, AC, USB) monitoring by userspace 5 power supply (batteries, AC, USB) monitoring by userspace
6 via sysfs and uevent (if available) and/or APM kernel interface 6 via sysfs and uevent (if available) and/or APM kernel interface
7 (if selected below). 7 (if selected below).
8 8
9 if POWER_SUPPLY 9 if POWER_SUPPLY
10 10
11 config POWER_SUPPLY_DEBUG 11 config POWER_SUPPLY_DEBUG
12 bool "Power supply debug" 12 bool "Power supply debug"
13 help 13 help
14 Say Y here to enable debugging messages for power supply class 14 Say Y here to enable debugging messages for power supply class
15 and drivers. 15 and drivers.
16 16
17 config PDA_POWER 17 config PDA_POWER
18 tristate "Generic PDA/phone power driver" 18 tristate "Generic PDA/phone power driver"
19 depends on !S390 19 depends on !S390
20 help 20 help
21 Say Y here to enable generic power driver for PDAs and phones with 21 Say Y here to enable generic power driver for PDAs and phones with
22 one or two external power supplies (AC/USB) connected to main and 22 one or two external power supplies (AC/USB) connected to main and
23 backup batteries, and optional builtin charger. 23 backup batteries, and optional builtin charger.
24 24
25 config APM_POWER 25 config APM_POWER
26 tristate "APM emulation for class batteries" 26 tristate "APM emulation for class batteries"
27 depends on APM_EMULATION 27 depends on APM_EMULATION
28 help 28 help
29 Say Y here to enable support APM status emulation using 29 Say Y here to enable support APM status emulation using
30 battery class devices. 30 battery class devices.
31 31
32 config GENERIC_ADC_BATTERY 32 config GENERIC_ADC_BATTERY
33 tristate "Generic battery support using IIO" 33 tristate "Generic battery support using IIO"
34 depends on IIO 34 depends on IIO
35 help 35 help
36 Say Y here to enable support for the generic battery driver 36 Say Y here to enable support for the generic battery driver
37 which uses IIO framework to read adc. 37 which uses IIO framework to read adc.
38 38
39 config MAX8925_POWER 39 config MAX8925_POWER
40 tristate "MAX8925 battery charger support" 40 tristate "MAX8925 battery charger support"
41 depends on MFD_MAX8925 41 depends on MFD_MAX8925
42 help 42 help
43 Say Y here to enable support for the battery charger in the Maxim 43 Say Y here to enable support for the battery charger in the Maxim
44 MAX8925 PMIC. 44 MAX8925 PMIC.
45 45
46 config WM831X_BACKUP 46 config WM831X_BACKUP
47 tristate "WM831X backup battery charger support" 47 tristate "WM831X backup battery charger support"
48 depends on MFD_WM831X 48 depends on MFD_WM831X
49 help 49 help
50 Say Y here to enable support for the backup battery charger 50 Say Y here to enable support for the backup battery charger
51 in the Wolfson Microelectronics WM831x PMICs. 51 in the Wolfson Microelectronics WM831x PMICs.
52 52
53 config WM831X_POWER 53 config WM831X_POWER
54 tristate "WM831X PMU support" 54 tristate "WM831X PMU support"
55 depends on MFD_WM831X 55 depends on MFD_WM831X
56 help 56 help
57 Say Y here to enable support for the power management unit 57 Say Y here to enable support for the power management unit
58 provided by Wolfson Microelectronics WM831x PMICs. 58 provided by Wolfson Microelectronics WM831x PMICs.
59 59
60 config WM8350_POWER 60 config WM8350_POWER
61 tristate "WM8350 PMU support" 61 tristate "WM8350 PMU support"
62 depends on MFD_WM8350 62 depends on MFD_WM8350
63 help 63 help
64 Say Y here to enable support for the power management unit 64 Say Y here to enable support for the power management unit
65 provided by the Wolfson Microelectronics WM8350 PMIC. 65 provided by the Wolfson Microelectronics WM8350 PMIC.
66 66
67 config TEST_POWER 67 config TEST_POWER
68 tristate "Test power driver" 68 tristate "Test power driver"
69 help 69 help
70 This driver is used for testing. It's safe to say M here. 70 This driver is used for testing. It's safe to say M here.
71 71
72 config BATTERY_88PM860X 72 config BATTERY_88PM860X
73 tristate "Marvell 88PM860x battery driver" 73 tristate "Marvell 88PM860x battery driver"
74 depends on MFD_88PM860X 74 depends on MFD_88PM860X
75 help 75 help
76 Say Y here to enable battery monitor for Marvell 88PM860x chip. 76 Say Y here to enable battery monitor for Marvell 88PM860x chip.
77 77
78 config BATTERY_DS2760 78 config BATTERY_DS2760
79 tristate "DS2760 battery driver (HP iPAQ & others)" 79 tristate "DS2760 battery driver (HP iPAQ & others)"
80 depends on W1 && W1_SLAVE_DS2760 80 depends on W1 && W1_SLAVE_DS2760
81 help 81 help
82 Say Y here to enable support for batteries with ds2760 chip. 82 Say Y here to enable support for batteries with ds2760 chip.
83 83
84 config BATTERY_DS2780 84 config BATTERY_DS2780
85 tristate "DS2780 battery driver" 85 tristate "DS2780 battery driver"
86 depends on HAS_IOMEM 86 depends on HAS_IOMEM
87 select W1 87 select W1
88 select W1_SLAVE_DS2780 88 select W1_SLAVE_DS2780
89 help 89 help
90 Say Y here to enable support for batteries with ds2780 chip. 90 Say Y here to enable support for batteries with ds2780 chip.
91 91
92 config BATTERY_DS2781 92 config BATTERY_DS2781
93 tristate "DS2781 battery driver" 93 tristate "DS2781 battery driver"
94 depends on HAS_IOMEM 94 depends on HAS_IOMEM
95 select W1 95 select W1
96 select W1_SLAVE_DS2781 96 select W1_SLAVE_DS2781
97 help 97 help
98 If you enable this you will have the DS2781 battery driver support. 98 If you enable this you will have the DS2781 battery driver support.
99 99
100 The battery monitor chip is used in many batteries/devices 100 The battery monitor chip is used in many batteries/devices
101 as the one who is responsible for charging/discharging/monitoring 101 as the one who is responsible for charging/discharging/monitoring
102 Li+ batteries. 102 Li+ batteries.
103 103
104 If you are unsure, say N. 104 If you are unsure, say N.
105 105
106 config BATTERY_DS2782 106 config BATTERY_DS2782
107 tristate "DS2782/DS2786 standalone gas-gauge" 107 tristate "DS2782/DS2786 standalone gas-gauge"
108 depends on I2C 108 depends on I2C
109 help 109 help
110 Say Y here to enable support for the DS2782/DS2786 standalone battery 110 Say Y here to enable support for the DS2782/DS2786 standalone battery
111 gas-gauge. 111 gas-gauge.
112 112
113 config BATTERY_PMU 113 config BATTERY_PMU
114 tristate "Apple PMU battery" 114 tristate "Apple PMU battery"
115 depends on PPC32 && ADB_PMU 115 depends on PPC32 && ADB_PMU
116 help 116 help
117 Say Y here to expose battery information on Apple machines 117 Say Y here to expose battery information on Apple machines
118 through the generic battery class. 118 through the generic battery class.
119 119
120 config BATTERY_OLPC 120 config BATTERY_OLPC
121 tristate "One Laptop Per Child battery" 121 tristate "One Laptop Per Child battery"
122 depends on X86_32 && OLPC 122 depends on X86_32 && OLPC
123 help 123 help
124 Say Y to enable support for the battery on the OLPC laptop. 124 Say Y to enable support for the battery on the OLPC laptop.
125 125
126 config BATTERY_TOSA 126 config BATTERY_TOSA
127 tristate "Sharp SL-6000 (tosa) battery" 127 tristate "Sharp SL-6000 (tosa) battery"
128 depends on MACH_TOSA && MFD_TC6393XB && TOUCHSCREEN_WM97XX 128 depends on MACH_TOSA && MFD_TC6393XB && TOUCHSCREEN_WM97XX
129 help 129 help
130 Say Y to enable support for the battery on the Sharp Zaurus 130 Say Y to enable support for the battery on the Sharp Zaurus
131 SL-6000 (tosa) models. 131 SL-6000 (tosa) models.
132 132
133 config BATTERY_COLLIE 133 config BATTERY_COLLIE
134 tristate "Sharp SL-5500 (collie) battery" 134 tristate "Sharp SL-5500 (collie) battery"
135 depends on SA1100_COLLIE && MCP_UCB1200 135 depends on SA1100_COLLIE && MCP_UCB1200
136 help 136 help
137 Say Y to enable support for the battery on the Sharp Zaurus 137 Say Y to enable support for the battery on the Sharp Zaurus
138 SL-5500 (collie) models. 138 SL-5500 (collie) models.
139 139
140 config BATTERY_WM97XX 140 config BATTERY_WM97XX
141 bool "WM97xx generic battery driver" 141 bool "WM97xx generic battery driver"
142 depends on TOUCHSCREEN_WM97XX=y 142 depends on TOUCHSCREEN_WM97XX=y
143 help 143 help
144 Say Y to enable support for battery measured by WM97xx aux port. 144 Say Y to enable support for battery measured by WM97xx aux port.
145 145
146 config BATTERY_SBS 146 config BATTERY_SBS
147 tristate "SBS Compliant gas gauge" 147 tristate "SBS Compliant gas gauge"
148 depends on I2C 148 depends on I2C
149 help 149 help
150 Say Y to include support for SBS battery driver for SBS-compliant 150 Say Y to include support for SBS battery driver for SBS-compliant
151 gas gauges. 151 gas gauges.
152 152
153 config BATTERY_BQ27x00 153 config BATTERY_BQ27x00
154 tristate "BQ27x00 battery driver" 154 tristate "BQ27x00 battery driver"
155 depends on I2C || I2C=n 155 depends on I2C || I2C=n
156 help 156 help
157 Say Y here to enable support for batteries with BQ27x00 (I2C/HDQ) chips. 157 Say Y here to enable support for batteries with BQ27x00 (I2C/HDQ) chips.
158 158
159 config BATTERY_BQ27X00_I2C 159 config BATTERY_BQ27X00_I2C
160 bool "BQ27200/BQ27500 support" 160 bool "BQ27200/BQ27500 support"
161 depends on BATTERY_BQ27x00 161 depends on BATTERY_BQ27x00
162 depends on I2C 162 depends on I2C
163 default y 163 default y
164 help 164 help
165 Say Y here to enable support for batteries with BQ27x00 (I2C) chips. 165 Say Y here to enable support for batteries with BQ27x00 (I2C) chips.
166 166
167 config BATTERY_BQ27X00_PLATFORM 167 config BATTERY_BQ27X00_PLATFORM
168 bool "BQ27000 support" 168 bool "BQ27000 support"
169 depends on BATTERY_BQ27x00 169 depends on BATTERY_BQ27x00
170 default y 170 default y
171 help 171 help
172 Say Y here to enable support for batteries with BQ27000 (HDQ) chips. 172 Say Y here to enable support for batteries with BQ27000 (HDQ) chips.
173 173
174 config BATTERY_DA9030 174 config BATTERY_DA9030
175 tristate "DA9030 battery driver" 175 tristate "DA9030 battery driver"
176 depends on PMIC_DA903X 176 depends on PMIC_DA903X
177 help 177 help
178 Say Y here to enable support for batteries charger integrated into 178 Say Y here to enable support for batteries charger integrated into
179 DA9030 PMIC. 179 DA9030 PMIC.
180 180
181 config BATTERY_DA9052 181 config BATTERY_DA9052
182 tristate "Dialog DA9052 Battery" 182 tristate "Dialog DA9052 Battery"
183 depends on PMIC_DA9052 183 depends on PMIC_DA9052
184 help 184 help
185 Say Y here to enable support for batteries charger integrated into 185 Say Y here to enable support for batteries charger integrated into
186 DA9052 PMIC. 186 DA9052 PMIC.
187 187
188 config BATTERY_MAX17040 188 config BATTERY_MAX17040
189 tristate "Maxim MAX17040 Fuel Gauge" 189 tristate "Maxim MAX17040 Fuel Gauge"
190 depends on I2C 190 depends on I2C
191 help 191 help
192 MAX17040 is fuel-gauge systems for lithium-ion (Li+) batteries 192 MAX17040 is fuel-gauge systems for lithium-ion (Li+) batteries
193 in handheld and portable equipment. The MAX17040 is configured 193 in handheld and portable equipment. The MAX17040 is configured
194 to operate with a single lithium cell 194 to operate with a single lithium cell
195 195
196 config BATTERY_MAX17042 196 config BATTERY_MAX17042
197 tristate "Maxim MAX17042/17047/17050/8997/8966 Fuel Gauge" 197 tristate "Maxim MAX17042/17047/17050/8997/8966 Fuel Gauge"
198 depends on I2C 198 depends on I2C
199 help 199 help
200 MAX17042 is fuel-gauge systems for lithium-ion (Li+) batteries 200 MAX17042 is fuel-gauge systems for lithium-ion (Li+) batteries
201 in handheld and portable equipment. The MAX17042 is configured 201 in handheld and portable equipment. The MAX17042 is configured
202 to operate with a single lithium cell. MAX8997 and MAX8966 are 202 to operate with a single lithium cell. MAX8997 and MAX8966 are
203 multi-function devices that include fuel gauages that are compatible 203 multi-function devices that include fuel gauages that are compatible
204 with MAX17042. This driver also supports max17047/50 chips which are 204 with MAX17042. This driver also supports max17047/50 chips which are
205 improved version of max17042. 205 improved version of max17042.
206 206
207 config BATTERY_Z2 207 config BATTERY_Z2
208 tristate "Z2 battery driver" 208 tristate "Z2 battery driver"
209 depends on I2C && MACH_ZIPIT2 209 depends on I2C && MACH_ZIPIT2
210 help 210 help
211 Say Y to include support for the battery on the Zipit Z2. 211 Say Y to include support for the battery on the Zipit Z2.
212 212
213 config BATTERY_S3C_ADC 213 config BATTERY_S3C_ADC
214 tristate "Battery driver for Samsung ADC based monitoring" 214 tristate "Battery driver for Samsung ADC based monitoring"
215 depends on S3C_ADC 215 depends on S3C_ADC
216 help 216 help
217 Say Y here to enable support for iPAQ h1930/h1940/rx1950 battery 217 Say Y here to enable support for iPAQ h1930/h1940/rx1950 battery
218 218
219 config CHARGER_88PM860X 219 config CHARGER_88PM860X
220 tristate "Marvell 88PM860x Charger driver" 220 tristate "Marvell 88PM860x Charger driver"
221 depends on MFD_88PM860X && BATTERY_88PM860X 221 depends on MFD_88PM860X && BATTERY_88PM860X
222 help 222 help
223 Say Y here to enable charger for Marvell 88PM860x chip. 223 Say Y here to enable charger for Marvell 88PM860x chip.
224 224
225 config CHARGER_PCF50633 225 config CHARGER_PCF50633
226 tristate "NXP PCF50633 MBC" 226 tristate "NXP PCF50633 MBC"
227 depends on MFD_PCF50633 227 depends on MFD_PCF50633
228 help 228 help
229 Say Y to include support for NXP PCF50633 Main Battery Charger. 229 Say Y to include support for NXP PCF50633 Main Battery Charger.
230 230
231 config BATTERY_JZ4740 231 config BATTERY_JZ4740
232 tristate "Ingenic JZ4740 battery" 232 tristate "Ingenic JZ4740 battery"
233 depends on MACH_JZ4740 233 depends on MACH_JZ4740
234 depends on MFD_JZ4740_ADC 234 depends on MFD_JZ4740_ADC
235 help 235 help
236 Say Y to enable support for the battery on Ingenic JZ4740 based 236 Say Y to enable support for the battery on Ingenic JZ4740 based
237 boards. 237 boards.
238 238
239 This driver can be build as a module. If so, the module will be 239 This driver can be build as a module. If so, the module will be
240 called jz4740-battery. 240 called jz4740-battery.
241 241
242 config BATTERY_INTEL_MID 242 config BATTERY_INTEL_MID
243 tristate "Battery driver for Intel MID platforms" 243 tristate "Battery driver for Intel MID platforms"
244 depends on INTEL_SCU_IPC && SPI 244 depends on INTEL_SCU_IPC && SPI
245 help 245 help
246 Say Y here to enable the battery driver on Intel MID 246 Say Y here to enable the battery driver on Intel MID
247 platforms. 247 platforms.
248 248
249 config BATTERY_RX51 249 config BATTERY_RX51
250 tristate "Nokia RX-51 (N900) battery driver" 250 tristate "Nokia RX-51 (N900) battery driver"
251 depends on TWL4030_MADC 251 depends on TWL4030_MADC
252 help 252 help
253 Say Y here to enable support for battery information on Nokia 253 Say Y here to enable support for battery information on Nokia
254 RX-51, also known as N900 tablet. 254 RX-51, also known as N900 tablet.
255 255
256 config CHARGER_ISP1704 256 config CHARGER_ISP1704
257 tristate "ISP1704 USB Charger Detection" 257 tristate "ISP1704 USB Charger Detection"
258 depends on USB_PHY 258 depends on USB_PHY
259 help 259 help
260 Say Y to enable support for USB Charger Detection with 260 Say Y to enable support for USB Charger Detection with
261 ISP1707/ISP1704 USB transceivers. 261 ISP1707/ISP1704 USB transceivers.
262 262
263 config CHARGER_MAX8903 263 config CHARGER_MAX8903
264 tristate "MAX8903 Battery DC-DC Charger for USB and Adapter Power" 264 tristate "MAX8903 Battery DC-DC Charger for USB and Adapter Power"
265 depends on GENERIC_HARDIRQS 265 depends on GENERIC_HARDIRQS
266 help 266 help
267 Say Y to enable support for the MAX8903 DC-DC charger and sysfs. 267 Say Y to enable support for the MAX8903 DC-DC charger and sysfs.
268 The driver supports controlling charger-enable and current-limit 268 The driver supports controlling charger-enable and current-limit
269 pins based on the status of charger connections with interrupt 269 pins based on the status of charger connections with interrupt
270 handlers. 270 handlers.
271 271
272 config SABRESD_MAX8903 272 config SABRESD_MAX8903
273 tristate "Sabresd Board Battery DC-DC Charger for USB and Adapter Power" 273 tristate "Sabresd Board Battery DC-DC Charger for USB and Adapter Power"
274 depends on GENERIC_HARDIRQS && TOUCHSCREEN_MAX11801 274 depends on GENERIC_HARDIRQS && TOUCHSCREEN_MAX11801
275 help 275 help
276 Say Y to enable support for the MAX8903 DC-DC charger and sysfs on 276 Say Y to enable support for the MAX8903 DC-DC charger and sysfs on
277 sabresd board.The driver supports controlling charger and battery 277 sabresd board.The driver supports controlling charger and battery
278 based on the status of charger connections with interrupt handlers. 278 based on the status of charger connections with interrupt handlers.
279 279
280 config CHARGER_TWL4030 280 config CHARGER_TWL4030
281 tristate "OMAP TWL4030 BCI charger driver" 281 tristate "OMAP TWL4030 BCI charger driver"
282 depends on TWL4030_CORE 282 depends on TWL4030_CORE
283 help 283 help
284 Say Y here to enable support for TWL4030 Battery Charge Interface. 284 Say Y here to enable support for TWL4030 Battery Charge Interface.
285 285
286 config CHARGER_LP8727 286 config CHARGER_LP8727
287 tristate "TI/National Semiconductor LP8727 charger driver" 287 tristate "TI/National Semiconductor LP8727 charger driver"
288 depends on I2C 288 depends on I2C
289 help 289 help
290 Say Y here to enable support for LP8727 Charger Driver. 290 Say Y here to enable support for LP8727 Charger Driver.
291 291
292 config CHARGER_LP8788 292 config CHARGER_LP8788
293 tristate "TI LP8788 charger driver" 293 tristate "TI LP8788 charger driver"
294 depends on MFD_LP8788 294 depends on MFD_LP8788
295 depends on LP8788_ADC 295 depends on LP8788_ADC
296 depends on IIO 296 depends on IIO
297 help 297 help
298 Say Y to enable support for the LP8788 linear charger. 298 Say Y to enable support for the LP8788 linear charger.
299 299
300 config CHARGER_GPIO 300 config CHARGER_GPIO
301 tristate "GPIO charger" 301 tristate "GPIO charger"
302 depends on GPIOLIB 302 depends on GPIOLIB
303 help 303 help
304 Say Y to include support for chargers which report their online status 304 Say Y to include support for chargers which report their online status
305 through a GPIO pin. 305 through a GPIO pin.
306 306
307 This driver can be build as a module. If so, the module will be 307 This driver can be build as a module. If so, the module will be
308 called gpio-charger. 308 called gpio-charger.
309 309
310 config CHARGER_MANAGER 310 config CHARGER_MANAGER
311 bool "Battery charger manager for multiple chargers" 311 bool "Battery charger manager for multiple chargers"
312 depends on REGULATOR && RTC_CLASS 312 depends on REGULATOR && RTC_CLASS
313 select EXTCON 313 select EXTCON
314 help 314 help
315 Say Y to enable charger-manager support, which allows multiple 315 Say Y to enable charger-manager support, which allows multiple
316 chargers attached to a battery and multiple batteries attached to a 316 chargers attached to a battery and multiple batteries attached to a
317 system. The charger-manager also can monitor charging status in 317 system. The charger-manager also can monitor charging status in
318 runtime and in suspend-to-RAM by waking up the system periodically 318 runtime and in suspend-to-RAM by waking up the system periodically
319 with help of suspend_again support. 319 with help of suspend_again support.
320 320
321 config CHARGER_MAX8997 321 config CHARGER_MAX8997
322 tristate "Maxim MAX8997/MAX8966 PMIC battery charger driver" 322 tristate "Maxim MAX8997/MAX8966 PMIC battery charger driver"
323 depends on MFD_MAX8997 && REGULATOR_MAX8997 323 depends on MFD_MAX8997 && REGULATOR_MAX8997
324 help 324 help
325 Say Y to enable support for the battery charger control sysfs and 325 Say Y to enable support for the battery charger control sysfs and
326 platform data of MAX8997/LP3974 PMICs. 326 platform data of MAX8997/LP3974 PMICs.
327 327
328 config CHARGER_MAX8998 328 config CHARGER_MAX8998
329 tristate "Maxim MAX8998/LP3974 PMIC battery charger driver" 329 tristate "Maxim MAX8998/LP3974 PMIC battery charger driver"
330 depends on MFD_MAX8998 && REGULATOR_MAX8998 330 depends on MFD_MAX8998 && REGULATOR_MAX8998
331 help 331 help
332 Say Y to enable support for the battery charger control sysfs and 332 Say Y to enable support for the battery charger control sysfs and
333 platform data of MAX8998/LP3974 PMICs. 333 platform data of MAX8998/LP3974 PMICs.
334 334
335 config CHARGER_BQ2415X 335 config CHARGER_BQ2415X
336 tristate "TI BQ2415x battery charger driver" 336 tristate "TI BQ2415x battery charger driver"
337 depends on I2C 337 depends on I2C
338 help 338 help
339 Say Y to enable support for the TI BQ2415x battery charger 339 Say Y to enable support for the TI BQ2415x battery charger
340 PMICs. 340 PMICs.
341 341
342 You'll need this driver to charge batteries on e.g. Nokia 342 You'll need this driver to charge batteries on e.g. Nokia
343 RX-51/N900. 343 RX-51/N900.
344 344
345 config CHARGER_BQ2477X
346 tristate "BQ24770/BQ24773 Charger driver support"
347 depends on I2C
348 help
349 BQ2477X is a companion pmic for smartphones and tablets
350 which supports battery charging feature.
351 Say Y here to enable driver support for TI BQ24770/
352 BQ24773 Battery Charger.
353
345 config CHARGER_SMB347 354 config CHARGER_SMB347
346 tristate "Summit Microelectronics SMB347 Battery Charger" 355 tristate "Summit Microelectronics SMB347 Battery Charger"
347 depends on I2C 356 depends on I2C
348 select REGMAP_I2C 357 select REGMAP_I2C
349 help 358 help
350 Say Y to include support for Summit Microelectronics SMB347 359 Say Y to include support for Summit Microelectronics SMB347
351 Battery Charger. 360 Battery Charger.
352 361
353 config CHARGER_TPS65090 362 config CHARGER_TPS65090
354 tristate "TPS65090 battery charger driver" 363 tristate "TPS65090 battery charger driver"
355 depends on MFD_TPS65090 364 depends on MFD_TPS65090
356 help 365 help
357 Say Y here to enable support for battery charging with TPS65090 366 Say Y here to enable support for battery charging with TPS65090
358 PMIC chips. 367 PMIC chips.
359 368
360 config AB8500_BM 369 config AB8500_BM
361 bool "AB8500 Battery Management Driver" 370 bool "AB8500 Battery Management Driver"
362 depends on AB8500_CORE && AB8500_GPADC 371 depends on AB8500_CORE && AB8500_GPADC
363 help 372 help
364 Say Y to include support for AB8500 battery management. 373 Say Y to include support for AB8500 battery management.
365 374
366 config BATTERY_GOLDFISH 375 config BATTERY_GOLDFISH
367 tristate "Goldfish battery driver" 376 tristate "Goldfish battery driver"
368 depends on GENERIC_HARDIRQS 377 depends on GENERIC_HARDIRQS
369 help 378 help
370 Say Y to enable support for the battery and AC power in the 379 Say Y to enable support for the battery and AC power in the
371 Goldfish emulator. 380 Goldfish emulator.
372 381
373 config IMX6_USB_CHARGER 382 config IMX6_USB_CHARGER
374 bool "Freescale imx6 USB Charger" 383 bool "Freescale imx6 USB Charger"
375 depends on SOC_IMX6Q || SOC_IMX6SL 384 depends on SOC_IMX6Q || SOC_IMX6SL
376 help 385 help
377 Say Y to enable Freescale imx6 USB Charger Detect. 386 Say Y to enable Freescale imx6 USB Charger Detect.
378 387
379 source "drivers/power/reset/Kconfig" 388 source "drivers/power/reset/Kconfig"
380 389
381 endif # POWER_SUPPLY 390 endif # POWER_SUPPLY
382 391
383 source "drivers/power/avs/Kconfig" 392 source "drivers/power/avs/Kconfig"
384 393
drivers/power/Makefile
Diff comments   View file @ 8f7b130
1 ccflags-$(CONFIG_POWER_SUPPLY_DEBUG) := -DDEBUG 1 ccflags-$(CONFIG_POWER_SUPPLY_DEBUG) := -DDEBUG
2 2
3 power_supply-y := power_supply_core.o 3 power_supply-y := power_supply_core.o
4 power_supply-$(CONFIG_SYSFS) += power_supply_sysfs.o 4 power_supply-$(CONFIG_SYSFS) += power_supply_sysfs.o
5 power_supply-$(CONFIG_LEDS_TRIGGERS) += power_supply_leds.o 5 power_supply-$(CONFIG_LEDS_TRIGGERS) += power_supply_leds.o
6 6
7 obj-$(CONFIG_POWER_SUPPLY) += power_supply.o 7 obj-$(CONFIG_POWER_SUPPLY) += power_supply.o
8 obj-$(CONFIG_GENERIC_ADC_BATTERY) += generic-adc-battery.o 8 obj-$(CONFIG_GENERIC_ADC_BATTERY) += generic-adc-battery.o
9 9
10 obj-$(CONFIG_PDA_POWER) += pda_power.o 10 obj-$(CONFIG_PDA_POWER) += pda_power.o
11 obj-$(CONFIG_APM_POWER) += apm_power.o 11 obj-$(CONFIG_APM_POWER) += apm_power.o
12 obj-$(CONFIG_MAX8925_POWER) += max8925_power.o 12 obj-$(CONFIG_MAX8925_POWER) += max8925_power.o
13 obj-$(CONFIG_WM831X_BACKUP) += wm831x_backup.o 13 obj-$(CONFIG_WM831X_BACKUP) += wm831x_backup.o
14 obj-$(CONFIG_WM831X_POWER) += wm831x_power.o 14 obj-$(CONFIG_WM831X_POWER) += wm831x_power.o
15 obj-$(CONFIG_WM8350_POWER) += wm8350_power.o 15 obj-$(CONFIG_WM8350_POWER) += wm8350_power.o
16 obj-$(CONFIG_TEST_POWER) += test_power.o 16 obj-$(CONFIG_TEST_POWER) += test_power.o
17 17
18 obj-$(CONFIG_BATTERY_88PM860X) += 88pm860x_battery.o 18 obj-$(CONFIG_BATTERY_88PM860X) += 88pm860x_battery.o
19 obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o 19 obj-$(CONFIG_BATTERY_DS2760) += ds2760_battery.o
20 obj-$(CONFIG_BATTERY_DS2780) += ds2780_battery.o 20 obj-$(CONFIG_BATTERY_DS2780) += ds2780_battery.o
21 obj-$(CONFIG_BATTERY_DS2781) += ds2781_battery.o 21 obj-$(CONFIG_BATTERY_DS2781) += ds2781_battery.o
22 obj-$(CONFIG_BATTERY_DS2782) += ds2782_battery.o 22 obj-$(CONFIG_BATTERY_DS2782) += ds2782_battery.o
23 obj-$(CONFIG_BATTERY_GOLDFISH) += goldfish_battery.o 23 obj-$(CONFIG_BATTERY_GOLDFISH) += goldfish_battery.o
24 obj-$(CONFIG_BATTERY_PMU) += pmu_battery.o 24 obj-$(CONFIG_BATTERY_PMU) += pmu_battery.o
25 obj-$(CONFIG_BATTERY_OLPC) += olpc_battery.o 25 obj-$(CONFIG_BATTERY_OLPC) += olpc_battery.o
26 obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o 26 obj-$(CONFIG_BATTERY_TOSA) += tosa_battery.o
27 obj-$(CONFIG_BATTERY_COLLIE) += collie_battery.o 27 obj-$(CONFIG_BATTERY_COLLIE) += collie_battery.o
28 obj-$(CONFIG_BATTERY_WM97XX) += wm97xx_battery.o 28 obj-$(CONFIG_BATTERY_WM97XX) += wm97xx_battery.o
29 obj-$(CONFIG_BATTERY_SBS) += sbs-battery.o 29 obj-$(CONFIG_BATTERY_SBS) += sbs-battery.o
30 obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o 30 obj-$(CONFIG_BATTERY_BQ27x00) += bq27x00_battery.o
31 obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o 31 obj-$(CONFIG_BATTERY_DA9030) += da9030_battery.o
32 obj-$(CONFIG_BATTERY_DA9052) += da9052-battery.o 32 obj-$(CONFIG_BATTERY_DA9052) += da9052-battery.o
33 obj-$(CONFIG_BATTERY_MAX17040) += max17040_battery.o 33 obj-$(CONFIG_BATTERY_MAX17040) += max17040_battery.o
34 obj-$(CONFIG_BATTERY_MAX17042) += max17042_battery.o 34 obj-$(CONFIG_BATTERY_MAX17042) += max17042_battery.o
35 obj-$(CONFIG_BATTERY_Z2) += z2_battery.o 35 obj-$(CONFIG_BATTERY_Z2) += z2_battery.o
36 obj-$(CONFIG_BATTERY_S3C_ADC) += s3c_adc_battery.o 36 obj-$(CONFIG_BATTERY_S3C_ADC) += s3c_adc_battery.o
37 obj-$(CONFIG_CHARGER_88PM860X) += 88pm860x_charger.o 37 obj-$(CONFIG_CHARGER_88PM860X) += 88pm860x_charger.o
38 obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o 38 obj-$(CONFIG_CHARGER_PCF50633) += pcf50633-charger.o
39 obj-$(CONFIG_BATTERY_JZ4740) += jz4740-battery.o 39 obj-$(CONFIG_BATTERY_JZ4740) += jz4740-battery.o
40 obj-$(CONFIG_BATTERY_INTEL_MID) += intel_mid_battery.o 40 obj-$(CONFIG_BATTERY_INTEL_MID) += intel_mid_battery.o
41 obj-$(CONFIG_BATTERY_RX51) += rx51_battery.o 41 obj-$(CONFIG_BATTERY_RX51) += rx51_battery.o
42 obj-$(CONFIG_AB8500_BM) += ab8500_bmdata.o ab8500_charger.o ab8500_fg.o ab8500_btemp.o abx500_chargalg.o pm2301_charger.o 42 obj-$(CONFIG_AB8500_BM) += ab8500_bmdata.o ab8500_charger.o ab8500_fg.o ab8500_btemp.o abx500_chargalg.o pm2301_charger.o
43 obj-$(CONFIG_CHARGER_ISP1704) += isp1704_charger.o 43 obj-$(CONFIG_CHARGER_ISP1704) += isp1704_charger.o
44 obj-$(CONFIG_CHARGER_MAX8903) += max8903_charger.o 44 obj-$(CONFIG_CHARGER_MAX8903) += max8903_charger.o
45 obj-$(CONFIG_SABRESD_MAX8903) += sabresd_battery.o 45 obj-$(CONFIG_SABRESD_MAX8903) += sabresd_battery.o
46 obj-$(CONFIG_CHARGER_TWL4030) += twl4030_charger.o 46 obj-$(CONFIG_CHARGER_TWL4030) += twl4030_charger.o
47 obj-$(CONFIG_CHARGER_LP8727) += lp8727_charger.o 47 obj-$(CONFIG_CHARGER_LP8727) += lp8727_charger.o
48 obj-$(CONFIG_CHARGER_LP8788) += lp8788-charger.o 48 obj-$(CONFIG_CHARGER_LP8788) += lp8788-charger.o
49 obj-$(CONFIG_CHARGER_GPIO) += gpio-charger.o 49 obj-$(CONFIG_CHARGER_GPIO) += gpio-charger.o
50 obj-$(CONFIG_CHARGER_MANAGER) += charger-manager.o 50 obj-$(CONFIG_CHARGER_MANAGER) += charger-manager.o
51 obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o 51 obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o
52 obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o 52 obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o
53 obj-$(CONFIG_CHARGER_BQ2415X) += bq2415x_charger.o 53 obj-$(CONFIG_CHARGER_BQ2415X) += bq2415x_charger.o
54 obj-$(CONFIG_CHARGER_BQ2477X) += bq2477x-charger.o
54 obj-$(CONFIG_POWER_AVS) += avs/ 55 obj-$(CONFIG_POWER_AVS) += avs/
55 obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o 56 obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o
56 obj-$(CONFIG_CHARGER_TPS65090) += tps65090-charger.o 57 obj-$(CONFIG_CHARGER_TPS65090) += tps65090-charger.o
57 obj-$(CONFIG_POWER_RESET) += reset/ 58 obj-$(CONFIG_POWER_RESET) += reset/
58 obj-$(CONFIG_IMX6_USB_CHARGER) += imx6_usb_charger.o 59 obj-$(CONFIG_IMX6_USB_CHARGER) += imx6_usb_charger.o
59 60
drivers/power/bq2477x-charger.c
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * bq2477x-charger.c -- BQ24770/3 Charger driver
3 *
4 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author: Andy Park <an...@nvidia.com>
7 * Author: Syed Rafiuddin <srafi...@nvidia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
14 * whether express or implied; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
21 * 02111-1307, USA
22 */
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/i2c.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/kthread.h>
29 #include <linux/sched.h>
30 #include <linux/time.h>
31 #include <linux/timer.h>
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/power/bq2477x-charger.h>
35 #include <linux/power_supply.h>
36 #include <linux/regmap.h>
37 #include <linux/regulator/driver.h>
38 #include <linux/regulator/machine.h>
39 #include <linux/slab.h>
40 #include <linux/rtc.h>
41 #include <linux/alarmtimer.h>
42 #include <linux/sched/rt.h>
43 #include <linux/gpio.h>
44 #include <linux/of_gpio.h>
45
46 enum bq2477x_chip_id { BQ24770, BQ24773};
47
48 struct bq2477x_chip {
49 struct device *dev;
50 struct power_supply ac;
51 struct regmap *regmap;
52 struct regmap *regmap_word;
53 struct mutex mutex;
54 int irq;
55 int charger_detect_gpio;
56 int charger_detect_gpio_active_low;
57 int ac_online;
58 int dac_ichg;
59 int dac_v;
60 int dac_minsv;
61 int dac_iin;
62 int suspended;
63 int wdt_refresh_timeout;
64 struct kthread_worker bq_kworker;
65 struct task_struct *bq_kworker_task;
66 struct kthread_work bq_wdt_work;
67 };
68
69 /* Kthread scheduling parameters */
70 struct sched_param bq2477x_param = {
71 .sched_priority = MAX_RT_PRIO - 1,
72 };
73
74 static const struct regmap_config bq2477x_regmap_config = {
75 .name = "bq2477x",
76 .reg_bits = 8,
77 .val_bits = 8,
78 .max_register = BQ2477X_MAX_REGS,
79 };
80
81 static const struct regmap_config bq2477x_regmap_word_config = {
82 .name = "bq2477x_word",
83 .reg_bits = 8,
84 .val_bits = 16,
85 .max_register = BQ2477X_MAX_REGS,
86 };
87
88 static int bq2477x_read(struct bq2477x_chip *bq2477x,
89 unsigned int reg, unsigned int *val)
90 {
91 return regmap_read(bq2477x->regmap, reg, val);
92 }
93
94 static int bq2477x_write(struct bq2477x_chip *bq2477x,
95 unsigned int reg, unsigned int val)
96 {
97 return regmap_write(bq2477x->regmap, reg, val);
98 }
99
100 static int bq2477x_write_word(struct bq2477x_chip *bq2477x,
101 unsigned int reg, unsigned int val)
102 {
103 return regmap_write(bq2477x->regmap_word, reg, val);
104 }
105
106 static int bq2477x_update_bits(struct bq2477x_chip *bq2477x,
107 unsigned int reg, unsigned int mask, unsigned int val)
108 {
109 return regmap_update_bits(bq2477x->regmap, reg, mask, val);
110 }
111
112 static enum power_supply_property bq2477x_psy_props[] = {
113 POWER_SUPPLY_PROP_ONLINE,
114 };
115
116 static int bq2477x_ac_get_property(struct power_supply *psy,
117 enum power_supply_property psp, union power_supply_propval *val)
118 {
119 struct bq2477x_chip *bq2477x;
120
121 bq2477x = container_of(psy, struct bq2477x_chip, ac);
122 if (psp == POWER_SUPPLY_PROP_ONLINE)
123 val->intval = bq2477x->ac_online;
124 else
125 return -EINVAL;
126 return 0;
127 }
128
129 static int bq2477x_show_chip_version(struct bq2477x_chip *bq2477x)
130 {
131 int ret;
132 unsigned int val;
133
134 ret = bq2477x_read(bq2477x, BQ2477X_DEVICE_ID_REG, &val);
135 if (ret < 0) {
136 dev_err(bq2477x->dev, "DEVICE_ID_REG read failed: %d\n", ret);
137 return ret;
138 }
139
140 if (val == BQ24770_DEVICE_ID)
141 dev_info(bq2477x->dev, "chip type BQ24770 detected\n");
142 else if (val == BQ24773_DEVICE_ID)
143 dev_info(bq2477x->dev, "chip type BQ24773 detected\n");
144 else {
145 dev_info(bq2477x->dev, "unrecognized chip type: 0x%4x\n", val);
146 return -EINVAL;
147 }
148 return 0;
149 }
150
151 static int bq2477x_hw_init(struct bq2477x_chip *bq2477x)
152 {
153 int ret = 0;
154
155 /* Configure control */
156 ret = bq2477x_write(bq2477x, BQ2477X_CHARGE_OPTION_0_MSB,
157 BQ2477X_CHARGE_OPTION_POR_MSB);
158 if (ret < 0) {
159 dev_err(bq2477x->dev, "CHARGE_OPTION_0 write failed %d\n", ret);
160 return ret;
161 }
162 ret = bq2477x_write(bq2477x, BQ2477X_CHARGE_OPTION_0_LSB,
163 BQ2477X_CHARGE_OPTION_POR_LSB);
164 if (ret < 0) {
165 dev_err(bq2477x->dev, "CHARGE_OPTION_0 write failed %d\n", ret);
166 return ret;
167 }
168
169 ret = bq2477x_write_word(bq2477x, BQ2477X_MAX_CHARGE_VOLTAGE_LSB,
170 (bq2477x->dac_v >> 8) | (bq2477x->dac_v << 8));
171 if (ret < 0) {
172 dev_err(bq2477x->dev, "CHARGE_VOLTAGE write failed %d\n", ret);
173 return ret;
174 }
175
176 ret = bq2477x_write(bq2477x, BQ2477X_MIN_SYS_VOLTAGE,
177 bq2477x->dac_minsv >> BQ2477X_MIN_SYS_VOLTAGE_SHIFT);
178 if (ret < 0) {
179 dev_err(bq2477x->dev, "MIN_SYS_VOLTAGE write failed %d\n", ret);
180 return ret;
181 }
182
183 /* Configure setting input current */
184 ret = bq2477x_write(bq2477x, BQ2477X_INPUT_CURRENT,
185 bq2477x->dac_iin >> BQ2477X_INPUT_CURRENT_SHIFT);
186 if (ret < 0) {
187 dev_err(bq2477x->dev, "INPUT_CURRENT write failed %d\n", ret);
188 return ret;
189 }
190
191 ret = bq2477x_write_word(bq2477x, BQ2477X_CHARGE_CURRENT_LSB,
192 (bq2477x->dac_ichg >> 8) | (bq2477x->dac_ichg << 8));
193 if (ret < 0) {
194 dev_err(bq2477x->dev, "CHARGE_CURRENT write failed %d\n", ret);
195 return ret;
196 }
197
198 return ret;
199 }
200
201 static void bq2477x_work_thread(struct kthread_work *work)
202 {
203 struct bq2477x_chip *bq2477x = container_of(work,
204 struct bq2477x_chip, bq_wdt_work);
205 int ret;
206
207 for (;;) {
208 ret = bq2477x_hw_init(bq2477x);
209 if (ret < 0) {
210 dev_err(bq2477x->dev, "Hardware init failed %d\n", ret);
211 return;
212 }
213
214 ret = bq2477x_update_bits(bq2477x, BQ2477X_CHARGE_OPTION_0_MSB,
215 BQ2477X_WATCHDOG_TIMER, 0x60);
216 if (ret < 0) {
217 dev_err(bq2477x->dev,
218 "CHARGE_OPTION write failed %d\n", ret);
219 return;
220 }
221
222 msleep(bq2477x->wdt_refresh_timeout * 1000);
223 }
224 }
225
226 static void of_bq2477x_parse_platform_data(struct i2c_client *client,
227 struct bq2477x_platform_data *pdata)
228 {
229 struct device_node *np = client->dev.of_node;
230 enum of_gpio_flags flags;
231 u32 pval;
232 int ret;
233
234 ret = of_property_read_u32(np, "ti,dac-ichg", &pval);
235 if (!ret)
236 pdata->dac_ichg = pval;
237 else
238 dev_warn(&client->dev, "dac-ichg not provided\n");
239
240 ret = of_property_read_u32(np, "ti,dac-v", &pval);
241 if (!ret)
242 pdata->dac_v = pval;
243 else
244 dev_warn(&client->dev, "dac-v not provided\n");
245
246 ret = of_property_read_u32(np, "ti,dac-minsv", &pval);
247 if (!ret)
248 pdata->dac_minsv = pval;
249 else
250 dev_warn(&client->dev, "dac-minsv not provided\n");
251
252 ret = of_property_read_u32(np, "ti,dac-iin", &pval);
253 if (!ret)
254 pdata->dac_iin = pval;
255 else
256 dev_warn(&client->dev, "dac-iin not provided\n");
257
258 ret = of_property_read_u32(np, "ti,wdt-refresh-timeout", &pval);
259 if (!ret)
260 pdata->wdt_refresh_timeout = pval;
261 else
262 dev_warn(&client->dev, "wdt-refresh-timeout not provided\n");
263
264 pdata->charger_detect_gpio = of_get_named_gpio_flags(np,
265 "ti,charger-detect-gpio",
266 0, &flags);
267 if (pdata->charger_detect_gpio >= 0)
268 pdata->charger_detect_gpio_active_low = flags &
269 OF_GPIO_ACTIVE_LOW;
270 else
271 dev_warn(&client->dev, "invalid charger_detect_gpio\n");
272 }
273
274 static irqreturn_t bq2477x_charger_detect_irq(int irq, void *data)
275 {
276 struct bq2477x_chip *bq2477x = data;
277 bq2477x->ac_online =
278 gpio_get_value_cansleep(bq2477x->charger_detect_gpio);
279 bq2477x->ac_online ^= bq2477x->charger_detect_gpio_active_low;
280
281 if (bq2477x->ac_online == 1)
282 bq2477x_hw_init(bq2477x);
283
284 power_supply_changed(&bq2477x->ac);
285 return IRQ_HANDLED;
286 }
287
288 static int bq2477x_probe(struct i2c_client *client,
289 const struct i2c_device_id *id)
290 {
291 struct bq2477x_chip *bq2477x = NULL;
292 struct bq2477x_platform_data *pdata;
293 int ret = 0;
294
295 if (client->dev.of_node) {
296 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
297 if (!pdata)
298 return -ENOMEM;
299 of_bq2477x_parse_platform_data(client, pdata);
300 } else {
301 pdata = client->dev.platform_data;
302 }
303
304 if (!pdata) {
305 dev_err(&client->dev, "No Platform data");
306 return -EINVAL;
307 }
308
309 bq2477x = devm_kzalloc(&client->dev, sizeof(*bq2477x), GFP_KERNEL);
310 if (!bq2477x) {
311 dev_err(&client->dev, "Memory allocation failed\n");
312 ret = -ENOMEM;
313 return ret;
314 }
315 bq2477x->dev = &client->dev;
316
317 bq2477x->dac_ichg = pdata->dac_ichg;
318 bq2477x->dac_v = pdata->dac_v;
319 bq2477x->dac_minsv = pdata->dac_minsv;
320 bq2477x->dac_iin = pdata->dac_iin;
321 bq2477x->wdt_refresh_timeout = pdata->wdt_refresh_timeout;
322 bq2477x->charger_detect_gpio = pdata->charger_detect_gpio;
323 bq2477x->charger_detect_gpio_active_low =
324 pdata->charger_detect_gpio_active_low;
325
326 i2c_set_clientdata(client, bq2477x);
327 mutex_init(&bq2477x->mutex);
328
329 bq2477x->ac_online = 0;
330
331 bq2477x->regmap = devm_regmap_init_i2c(client, &bq2477x_regmap_config);
332 if (IS_ERR(bq2477x->regmap)) {
333 ret = PTR_ERR(bq2477x->regmap);
334 dev_err(&client->dev, "regmap init failed with err %d\n", ret);
335 return ret;
336 }
337
338 bq2477x->regmap_word = devm_regmap_init_i2c(client,
339 &bq2477x_regmap_word_config);
340 if (IS_ERR(bq2477x->regmap_word)) {
341 ret = PTR_ERR(bq2477x->regmap_word);
342 dev_err(&client->dev,
343 "regmap_word init failed with err %d\n", ret);
344 return ret;
345 }
346
347 ret = bq2477x_show_chip_version(bq2477x);
348 if (ret < 0) {
349 dev_err(bq2477x->dev, "version read failed %d\n", ret);
350 return ret;
351 }
352
353 bq2477x->ac.name = "bq2477x-ac";
354 bq2477x->ac.type = POWER_SUPPLY_TYPE_MAINS;
355 bq2477x->ac.get_property = bq2477x_ac_get_property;
356 bq2477x->ac.properties = bq2477x_psy_props;
357 bq2477x->ac.num_properties = ARRAY_SIZE(bq2477x_psy_props);
358
359 ret = power_supply_register(bq2477x->dev, &bq2477x->ac);
360 if (ret < 0) {
361 dev_err(bq2477x->dev,
362 "AC power supply register failed %d\n", ret);
363 return ret;
364 }
365
366 if (gpio_is_valid(bq2477x->charger_detect_gpio)) {
367 ret = devm_gpio_request_one(bq2477x->dev,
368 bq2477x->charger_detect_gpio, GPIOF_IN,
369 "bq2477x-charger-detect");
370 if (ret) {
371 dev_err(bq2477x->dev, "gpio request failed %d\n", ret);
372 goto psy_err;
373 }
374
375 bq2477x->irq = gpio_to_irq(bq2477x->charger_detect_gpio);
376 bq2477x->ac_online =
377 gpio_get_value_cansleep(bq2477x->charger_detect_gpio);
378 bq2477x->ac_online ^= bq2477x->charger_detect_gpio_active_low;
379
380 ret = devm_request_threaded_irq(bq2477x->dev, bq2477x->irq,
381 NULL, bq2477x_charger_detect_irq,
382 IRQF_ONESHOT | IRQF_TRIGGER_RISING
383 | IRQF_TRIGGER_FALLING, dev_name(bq2477x->dev),
384 bq2477x);
385 if (ret < 0) {
386 dev_err(bq2477x->dev,
387 "Failed to request irq %d\n", ret);
388 goto psy_err;
389 }
390 }
391
392 ret = bq2477x_hw_init(bq2477x);
393 if (ret < 0) {
394 dev_err(bq2477x->dev, "Hardware init failed %d\n", ret);
395 goto psy_err;
396 }
397
398 init_kthread_worker(&bq2477x->bq_kworker);
399 bq2477x->bq_kworker_task = kthread_run(kthread_worker_fn,
400 &bq2477x->bq_kworker,
401 dev_name(bq2477x->dev));
402 if (IS_ERR(bq2477x->bq_kworker_task)) {
403 ret = PTR_ERR(bq2477x->bq_kworker_task);
404 dev_err(&client->dev, "Kworker task creation failed %d\n", ret);
405 goto psy_err;
406 }
407
408 init_kthread_work(&bq2477x->bq_wdt_work, bq2477x_work_thread);
409 sched_setscheduler(bq2477x->bq_kworker_task,
410 SCHED_FIFO, &bq2477x_param);
411 queue_kthread_work(&bq2477x->bq_kworker, &bq2477x->bq_wdt_work);
412
413 dev_info(bq2477x->dev, "bq2477x charger registerd\n");
414
415 return ret;
416
417 psy_err:
418 power_supply_unregister(&bq2477x->ac);
419 return ret;
420 }
421
422 static int bq2477x_remove(struct i2c_client *client)
423 {
424 struct bq2477x_chip *bq2477x = i2c_get_clientdata(client);
425 flush_kthread_worker(&bq2477x->bq_kworker);
426 kthread_stop(bq2477x->bq_kworker_task);
427 power_supply_unregister(&bq2477x->ac);
428 return 0;
429 }
430
431 static const struct i2c_device_id bq2477x_id[] = {
432 { "bq24770", BQ24770 },
433 { "bq24773", BQ24773 },
434 {},
435 };
436 MODULE_DEVICE_TABLE(i2c, bq2477x_id);
437
438 static struct i2c_driver bq2477x_i2c_driver = {
439 .driver = {
440 .name = "bq2477x-charger",
441 .owner = THIS_MODULE,
442 },
443 .probe = bq2477x_probe,
444 .remove = bq2477x_remove,
445 .id_table = bq2477x_id,
446 };
447
448 static int __init bq2477x_module_init(void)
449 {
450 return i2c_add_driver(&bq2477x_i2c_driver);
451 }
452 module_init(bq2477x_module_init);
453
454 static void __exit bq2477x_cleanup(void)
455 {
456 i2c_del_driver(&bq2477x_i2c_driver);
457 }
458 module_exit(bq2477x_cleanup);
459
460 MODULE_DESCRIPTION("BQ24770/BQ24773 battery charger driver");
461 MODULE_AUTHOR("Andy Park <an...@nvidia.com>");
462 MODULE_AUTHOR("Syed Rafiuddin <srafi...@nvidia.com");
463 MODULE_LICENSE("GPL v2");
464
include/linux/power/bq2477x-charger.h
Diff comments   View file @ 8f7b130
File was created 1 /*
2 * bq2477x-charger.h -- BQ2477X Charger driver
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author: Andy Park <an...@nvidia.com>
7 * Author: Syed Rafiuddin <srafi...@nvidia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 *
23 */
24
25 #ifndef __LINUX_POWER_BQ2477X_CHARGER_H
26 #define __LINUX_POWER_BQ2477X_CHARGER_H
27
28 /* Register definitions */
29 #define BQ2477X_CHARGE_OPTION_0_LSB 0x00
30 #define BQ2477X_CHARGE_OPTION_0_MSB 0x01
31 #define BQ2477X_CHARGE_OPTION_1_LSB 0x02
32 #define BQ2477X_CHARGE_OPTION_1_MSB 0x03
33 #define BQ2477X_PROCHOT_OPTION_0_LSB 0x04
34 #define BQ2477X_PROCHOT_OPTION_0_MSB 0x05
35 #define BQ2477X_PROCHOT_OPTION_1_LSB 0x06
36 #define BQ2477X_PROCHOT_OPTION_1_MSB 0x07
37 #define BQ2477X_DEVICE_ID_REG 0x09
38 #define BQ2477X_CHARGE_CURRENT_LSB 0x0A
39 #define BQ2477X_CHARGE_CURRENT_MSB 0x0B
40 #define BQ2477X_MAX_CHARGE_VOLTAGE_LSB 0x0C
41 #define BQ2477X_MAX_CHARGE_VOLTAGE_MSB 0x0D
42 #define BQ2477X_MIN_SYS_VOLTAGE 0x0E
43 #define BQ2477X_INPUT_CURRENT 0x0F
44
45 #define BQ24770_DEVICE_ID 0x14
46 #define BQ24773_DEVICE_ID 0x41
47
48 #define BQ2477X_CHARGE_OPTION_POR_LSB 0x0E
49 #define BQ2477X_CHARGE_OPTION_POR_MSB 0x81
50
51 #define BQ2477X_CHARGE_CURRENT_SHIFT 6
52 #define BQ2477X_MAX_CHARGE_VOLTAGE_SHIFT 4
53 #define BQ2477X_MIN_SYS_VOLTAGE_SHIFT 8
54 #define BQ2477X_INPUT_CURRENT_SHIFT 6
55
56 #define BQ2477X_ENABLE_CHARGE_MASK BIT(0)
57 #define BQ2477X_WATCHDOG_TIMER 0x60
58
59 #define BQ2477X_MAX_REGS (BQ2477X_INPUT_CURRENT + 1)
60
61 struct bq2477x_platform_data {
62 int irq;
63 int dac_ctrl;
64 int dac_ichg;
65 int dac_v;
66 int dac_minsv;
67 int dac_iin;
68 int wdt_refresh_timeout;
69 int gpio;
70 int charger_detect_gpio;
71 int charger_detect_gpio_active_low;
72 };
73 #endif /* __LINUX_POWER_BQ2477X_CHARGER_H */
74