Doug / smarc-fsl-linux-kernel

05 Apr, 2013

1 commit

  • adb378926   MIPS: Fix ISA level which causes secondary cache init bypassing and more ... Browse Code »

    The commit a96102be70 introduced set_isa() where compatible ISA info is
    also set aside from the one gets passed in. It means, for example, 1004K
    will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
    the following inappropriate:

    if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

    This patch fixes it.

    Signed-off-by: Deng-Cheng Zhu
    Cc: Steven J. Hill
    Cc: linux-mips@linux-mips.org
    Signed-off-by: Ralf Baechle

    Deng-Cheng Zhu
     

21 Feb, 2013

1 commit

17 Feb, 2013

1 commit

01 Feb, 2013

1 commit

  • 703422879   MIPS: Whitespace cleanup. ... Browse Code »

    Having received another series of whitespace patches I decided to do this
    once and for all rather than dealing with this kind of patches trickling
    in forever.

    Signed-off-by: Ralf Baechle

    Ralf Baechle
     

14 Dec, 2012

3 commits

09 Nov, 2012

1 commit

  • b5b64f2ba   MIPS: Move processing of coherency kernel parameters earlier ... Browse Code »

    Commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize
    jump-label subsystem much earlier) caused MIPS to break, so this was
    resolved with commit 6650df3c380e0db558dbfec63ed860402c6afb2a (MIPS:
    Move cache setup to setup_arch().). Unfortunately, after this commit,
    the coherency kernel parameters, cca and coherentio, are no longer
    processed before their values are used.

    This patch fixes this problem by marking them as early_param, which
    results in them being processed before they are needed.

    Signed-off-by: Shane McDonald
    Acked-by: David Daney
    Cc: Ralf Baechle
    Patchwork: http://patchwork.linux-mips.org/patch/3961
    Signed-off-by: John Crispin

    Shane McDonald
     

14 Sep, 2012

1 commit

19 Jul, 2012

1 commit

07 Jul, 2012

1 commit

17 May, 2012

1 commit

29 Mar, 2012

1 commit

20 Mar, 2012

1 commit

08 Dec, 2011

1 commit

  • a3d4fb2d2   MIPS: Netlogic: XLP CPU support. ... Browse Code »

    Add support for Netlogic's XLP MIPS SoC. This patch adds:
    * XLP processor ID in cpu_probe.c and asm/cpu.h
    * XLP case to asm/module.h
    * CPU_XLP case to mm/tlbex.c
    * minor change to r4k cache handling to ignore XLP secondary cache
    * XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h

    Signed-off-by: Jayachandran C
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/2966/
    Signed-off-by: Ralf Baechle

    Jayachandran C
     

20 Oct, 2011

1 commit

  • d9cdc901a   MIPS: cache: Provide cache flush operations for XFS ... Browse Code »

    Until now flush_kernel_vmap_range() and invalidate_kernel_vmap_range() did
    not exist on MIPS resulting in heavy cache corruption on XFS filesystems.

    Left for the post-3.0 time: optimization and make this work with highmem,
    too. Since the combination of highmem + cache aliases atm doesn't work
    this isn't a regression.

    Signed-off-by: Ralf Baechle
    Patchwork: https://patchwork.linux-mips.org/patch/2505/

    Ralf Baechle
     

26 Jul, 2011

1 commit

  • d0023c4a0   MIPS: Add SYNC after cacheflush ... Browse Code »

    On processors with deep write buffers, it is likely that many cycles
    will pass between a CACHE instruction and the time the data actually
    gets written out to DRAM. Add a SYNC instruction to ensure that the
    buffers get emptied before the flush functions return.

    Actual problem seen in the wild:

    1) dma_alloc_coherent() allocates cached memory

    2) memset() is called to clear the new pages

    3) dma_cache_wback_inv() is called to flush the zero data out to memory

    4) dma_alloc_coherent() returns an uncached (kseg1) pointer to the
    freshly allocated pages

    5) Caller writes data through the kseg1 pointer

    6) Buffered writeback data finally gets flushed out to DRAM

    7) Part of caller's data is inexplicably zeroed out

    This patch adds SYNC between steps 3 and 4, which fixed the problem.

    Signed-off-by: Kevin Cernekee
    Cc: linux-mips@linux-mips.org
    Cc: linux-kernel@vger.kernel.org
    Patchwork:
    Signed-off-by: Ralf Baechle

    Kevin Cernekee
     

24 May, 2011

1 commit

  • 57d19e80f   Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial ... Browse Code »

    * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (39 commits)
    b43: fix comment typo reqest -> request
    Haavard Skinnemoen has left Atmel
    cris: typo in mach-fs Makefile
    Kconfig: fix copy/paste-ism for dell-wmi-aio driver
    doc: timers-howto: fix a typo ("unsgined")
    perf: Only include annotate.h once in tools/perf/util/ui/browsers/annotate.c
    md, raid5: Fix spelling error in comment ('Ofcourse' --> 'Of course').
    treewide: fix a few typos in comments
    regulator: change debug statement be consistent with the style of the rest
    Revert "arm: mach-u300/gpio: Fix mem_region resource size miscalculations"
    audit: acquire creds selectively to reduce atomic op overhead
    rtlwifi: don't touch with treewide double semicolon removal
    treewide: cleanup continuations and remove logging message whitespace
    ath9k_hw: don't touch with treewide double semicolon removal
    include/linux/leds-regulator.h: fix syntax in example code
    tty: fix typo in descripton of tty_termios_encode_baud_rate
    xtensa: remove obsolete BKL kernel option from defconfig
    m68k: fix comment typo 'occcured'
    arch:Kconfig.locks Remove unused config option.
    treewide: remove extra semicolons
    ...

    Linus Torvalds
     

19 May, 2011

1 commit

11 May, 2011

1 commit

  • 71271aab8   MIPS: c-r4k: Fix GCC 4.6.0 build error ... Browse Code »

    CC arch/mips/mm/c-r4k.o
    arch/mips/mm/c-r4k.c: In function 'probe_scache':
    arch/mips/mm/c-r4k.c:1078:6: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable]
    cc1: all warnings being treated as errors

    Older GCC versions didn't warn about the unused variable tmp because it was
    getting initialized.

    Signed-off-by: Ralf Baechle

    Ralf Baechle
     

06 Apr, 2011

1 commit

30 Oct, 2010

2 commits

25 Jun, 2009

1 commit

17 Jun, 2009

1 commit

14 May, 2009

1 commit

30 Mar, 2009

1 commit

  • 270717a8a   MIPS: Alchemy: unify CPU model constants. ... Browse Code »

    This patch removes the various CPU_AU1??? model constants in favor of
    a single CPU_ALCHEMY one.

    All currently existing Alchemy models are identical in terms of cpu
    core and cache size/organization. The parts of the mips kernel which
    need to know the exact CPU revision extract it from the c0_prid register
    already; and finally nothing else in-tree depends on those any more.

    Should a new variant with slightly different "company options" and/or
    "processor revision" bits in c0_prid appear, it will be supported
    immediately (minus an exact model string in cpuinfo).

    Signed-off-by: Manuel Lauss
    Signed-off-by: Ralf Baechle

    Manuel Lauss
     

24 Mar, 2009

1 commit

31 Jan, 2009

1 commit

06 Sep, 2008

1 commit

  • e0cee3eea   [MIPS] Fix WARNING: at kernel/smp.c:290 ... Browse Code »

    trap_init issues flush_icache_range(), which uses ipi functions to
    get icache flushing done on all cpus. But this is done before interrupts
    are enabled and caused WARN_ON messages. This changeset introduces
    a new local_flush_icache_range() and uses it before interrupts (and
    additional CPUs) are enabled to avoid this problem.

    Signed-off-by: Thomas Bogendoerfer
    Signed-off-by: Ralf Baechle

    Thomas Bogendoerfer
     

26 Jun, 2008

1 commit

16 Jun, 2008

2 commits

29 Apr, 2008

2 commits

08 Apr, 2008

1 commit

12 Mar, 2008

1 commit

20 Feb, 2008

1 commit

  • 2eaa7ec28   [MIPS] Handle I-cache coherency in flush_cache_range() ... Browse Code »

    So far flush_cache_range() did't consider the I-cache largely because it
    did rarely ever matter to real world code. This was working primarily
    because normally code and data are don't share the same pages - with the
    exception of MIPS16 code which uses address constants embedded between
    the code. The following sequence of events may break the code:

    o MIPS16 executable being loaded
    o dynamic linker relocates the address constants embedded into the code:
    o Uses mprotect(2) to make code pages PROT_READ|PROT_WRITE
    o Performs the actual relocations by writing to the pages which likely
    are COW. Because no PROT_EXEC is set I-cache coherence will not be
    considered.
    o Uses mprotect(2) to switch code pages back to PROT_READ|PROT_EXEC.
    This results in a call to flush_cache_range() which also does not
    consider I-caches.
    o => executing the page just having been relocated may now result in the
    I-cache getting refilled with stale data from memory.

    Signed-off-by: Ralf Baechle

    Ralf Baechle
     

03 Feb, 2008

1 commit

29 Jan, 2008

1 commit

  • 237cfee1d   [MIPS] Alchemy: Au1210/Au1250 CPU support ... Browse Code »

    This patch adds IDs for new Au1200 variants: Au1210 and Au1250.
    They are essentially identical to the Au1200 except for the Au1210
    which has a different SoC-ID in the PRId register [bits 31:24].
    The Au1250 is a "Au1200 V0.2".

    Signed-off-by: Manuel Lauss
    Signed-off-by: Ralf Baechle

    Manuel Lauss