Doug / smarc-fsl-linux-kernel

17 Feb, 2013

1 commit

  • a69ba6293   MIPS: Netlogic: Split XLP L1 i-cache among threads ... Browse Code »

    Since we now use r4k cache code for Netlogic XLP, it is
    better to split L1 icache among the active threads, so that
    threads won't step on each other while flushing icache.

    The L1 dcache is already split among the threads in the core.

    Signed-off-by: Jayachandran C
    Patchwork: http://patchwork.linux-mips.org/patch/4787/
    Signed-off-by: John Crispin

    Jayachandran C
     

24 Jul, 2012

1 commit

  • 51d1eac0c   MIPS: Netlogic: SMP wakeup code update ... Browse Code »

    Update for core intialization code. Initialize status register
    after receiving NMI for CPU wakeup. Add the low level L1D flush
    code before enabling threads in core.

    Also convert the ehb to _ehb so that it works under more GCC
    versions.

    Signed-off-by: Jayachandran C
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/3755/
    Patchwork: https://patchwork.linux-mips.org/patch/4095/
    Signed-off-by: Ralf Baechle

    Jayachandran C
     

08 Dec, 2011

1 commit

  • 65040e224   MIPS: Netlogic: Add XLP platform files for XLP SoC ... Browse Code »

    - Update common files to support XLP.
    - Add arch/mips/include/asm/netlogic/xlp-hal for register definitions
    and access macros
    - Add arch/mips/netlogic/xlp/ for XLP specific files.

    Signed-off-by: Jayachandran C
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/2967/
    Signed-off-by: Ralf Baechle

    Jayachandran C