15 May, 2012
1 commit
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The maxburst/chunk size was taken from the private slave DMA data structure.
Use the common API provided by DMA_SLAVE_CONFIG to setup src/dst maxburst
values.
The ctrla field is not needed anymore in the slave private structure nor the
header constants that were located in an architecture specific directory.
The at91sam9g45_devices.c file that was using this platform data is also
modified to remove this now useless data.Signed-off-by: Nicolas Ferre
Signed-off-by: Vinod Koul
21 Mar, 2012
1 commit
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This patch introduces DMA_SLAVE_CONFIG to at_hdmac Atmel DMA driver.
It is needed to fix a regression in the use of atmel-mci.c driver on Atmel
AT91 platforms brouth by e2b35f3:
"dmaengine/dw_dmac: Fix dw_dmac user drivers to adapt to slave_config changes"We remove some parts of the private structure "at_dma_slave" and use the
information provided by "struct dma_slave_config": source/destination
peripheral registers and access width.AT_DMA_SLAVE_WIDTH_* values used previously are not needed anymore as we
now use the standard ones. Although some conversion functions are needed to
match register expected values.Some AT91 sub-architecture specific files are slightly touched by this patch
but it cannot be split because it can break compilation.Signed-off-by: Nicolas Ferre
Signed-off-by: Vinod Koul
13 Mar, 2012
1 commit
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Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures. This is pointless, and
forces driver specific code. Move this out into the common dma_chan
structure.Signed-off-by: Russell King
Tested-by: Linus Walleij
Reviewed-by: Linus Walleij
Acked-by: Jassi Brar
[imx-sdma.c & mxs-dma.c]
Tested-by: Shawn Guo
Signed-off-by: Vinod Koul
31 Jan, 2012
1 commit
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commit 463894705e4089d0ff69e7d877312d496ac70e5b deleted redundant
chan_id and chancnt initialization in dma drivers as this is done
in dma_async_device_register().However, atc_enable_irq() relied on chan_id set before registering
the device, what left only channel 0 functional for this driver.This patch introduces atc_enable/disable_chan_irq() as a variant
of atc_enable/disable_irq() with the channel as explicit argument.Signed-off-by: Nikolaus Voss
Signed-off-by: Nicolas Ferre
Cc: stable
Signed-off-by: Vinod Koul
28 Nov, 2011
1 commit
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Using a configuration structure simplify the finding of SoC
dependent parameters. Both platform data and device tree ids are
using these structures.
This will separate data from code and remove the need for an enum.Idea from Grant Likely.
Signed-off-by: Nicolas Ferre
Signed-off-by: Vinod Koul
10 Nov, 2011
1 commit
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We remove the use of platform data from DMA controller driver.
We now use of .id_table to distinguish between compatible
types. The two implementations allow to determine the
number of channels and the capabilities of the controller.Signed-off-by: Nicolas Ferre
Acked-by: Grant Likely
Signed-off-by: Vinod Koul
19 Aug, 2011
2 commits
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Cyclic property and paused state are encoded as bits in the channel status
bitfield. Tests of those bits are wrapped in convenient helper functions.Signed-off-by: Nicolas Ferre
Signed-off-by: Vinod Koul -
Save/restore dma controller state across a suspend-resume sequence.
The prepare() function will wait for the non-cyclic channels to become idle.
It also deals with cyclic operations with the start at next period while
resuming.Signed-off-by: Nicolas Ferre
Signed-off-by: Uwe Kleine-König
Signed-off-by: Vinod Koul
09 May, 2011
1 commit
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Pause and resume controls are useful for audio devices. This also returns
correct status from atc_tx_status() in case chan is paused.Idea from dw_dmac patch by Linus Walleij.
Signed-off-by: Nicolas Ferre
Acked-by: Linus Walleij
Signed-off-by: Vinod Koul
02 May, 2011
3 commits
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DMA controller has two AHB interfaces on the SOC internal
matrix.
It is more efficient to specialize each interface as the
access to memory can introduce latencies that are not compatible
with peripheral accesses requirements.Signed-off-by: Nicolas Ferre
Signed-off-by: Vinod Koul -
Signed-off-by: Nicolas Ferre
Signed-off-by: Vinod Koul -
Now we use Buffer Transfer Completed interrupts. If we
want a chained buffer completed information, we setup the
ATC_IEN bit in CTRLB register in the lli.
This is done by set_desc_eol() function and used by
memcpy/slave_sg functions.Signed-off-by: Nicolas Ferre
Signed-off-by: Vinod Koul
09 Sep, 2009
1 commit
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Drop at_hdmac's use of tx_list from struct dma_async_tx_descriptor in
preparation for removal of this field.Cc: Nicolas Ferre
Signed-off-by: Dan Williams
23 Jul, 2009
2 commits
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This patch for at_hdmac adds the slave transfers capability to the Atmel DMA
controller available on some AT91 SOCs. This allow peripheral to memory and
memory to peripheral transfers with hardware handshaking.Slave structure for controller specific information is passed through channel
private data. This at_dma_slave structure is defined in at_hdmac.h header file
and relative hardware definition are moved to this file from at_hdmac_regs.h.
Doing this we allow the channel configuration from platform definition code.This work is intensively based on dw_dmac and several slave implementations.
Signed-off-by: Nicolas Ferre
Signed-off-by: Dan Williams -
This AHB DMA Controller (aka HDMA or DMAC on AT91 systems) is availlable on
at91sam9rl chip. It will be used on other products in the future.This first release covers only the memory-to-memory tranfer type. This is the
only tranfer type supported by this chip. On other products, it will be used
also for peripheral DMA transfer (slave API support to come).I used dmatest client without problem in different configurations to test it.
Full documentation for this controller can be found in the SAM9RL datasheet:
http://www.atmel.com/dyn/products/product_card.asp?part_id=4243Signed-off-by: Nicolas Ferre
Acked-by: Maciej Sosnowski
Signed-off-by: Dan Williams