14 Oct, 2011
2 commits
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Add ioctl to Freescale hypervisor management driver for 32-bit user-space
applications running on 64-bit guests.Signed-off-by: Mihai Caraman
Acked-by: Timur Tabi
Signed-off-by: Kumar Gala -
Add support for the msi-address-64 property of a PCI node. This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly. These fields are replace with a single field, msiir_offset,
to reflect the new meaning.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
13 Oct, 2011
2 commits
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Normally logical and hard cpu ID are the same, however in same cases like
on the P3060 they may differ. Where the logical is 0..5, the hard id
goes 0,1,4..7. This can causes issues for places we utilize PIR to index
into array like in debug exception handlers for finding the exception
stack.Move to setting up PIR with hard_smp_processor_id fixes the issue.
Signed-off-by: Kumar Gala
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Currently, it does a cntlzd on the size and then subtracts it from
21.... this doesn't take into account the varying size of a "long".
Just use __ilog instead (and subtract the 10 we have to subtract
to get to the tsize encoding).Also correct the comment about page sizes supported.
Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala
12 Oct, 2011
11 commits
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Adding new device tree binding file for the DCSR node. Modifying device
tree dtsi files to add DCSR node for P2041, P3041, P4080, & P5020.Signed-off-by: Stephen George
Signed-off-by: Kumar Gala -
Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards. There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis". Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed. This means that older kernels are
not compatible with newer device trees. This is not a real problem, however,
since that particular function doesn't work anyway. When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
Remove wrong CONFIG_ prefix in Kconfig file.
Signed-off-by: Anatolij Gustschin
Signed-off-by: Kumar Gala -
On FSL Book-E devices we support multiple large TLB sizes and so we can
get into situations in which the initial 1G TLB size is too big and
we're asked for a size that is not mappable by a single entry (like
512M). The single entry is important because when we bring up secondary
cores they need to ensure any data structure they need to access (eg
PACA or stack) is always mapped.So we really need to determine what size will actually be mapped by the
first TLB entry to ensure we limit early memory references to that
region. We refactor the map_mem_in_cams() code to provider a helper
function that we can utilize to determine the size of the first TLB
entry while taking into account size and alignment constraints.Signed-off-by: Kumar Gala
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For those MMUs that have some form of bolt'd linear mapping (TLB)
required its rare that one ever sets mem= smaller than the size of that
mapping.However, on Book-E 64 parts the initial linear mapping is quite large
(1G) so its quite reasonable that mem= is set smaller than that.We need to parse the command line for mem= limit and constrain the
amount of memory we map initially by it if need be.Signed-off-by: Kumar Gala
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Updates from make savedefconfig.
Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala -
Results from updates via make savedefconfig.
Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala -
Commit 765342526246c97600e5344c0949824d94bb51c3 made some small changes to
IPI, message_pass in smp_ops was initialized to NULL for other platforms
but not for 85xx which causes us to always use the mpic for IPI's even
if we support doorbells in HW.Signed-off-by: Matthew McClintock
Signed-off-by: Kumar Gala -
It is wrongly using undefined CONFIG_E500MC.
Signed-off-by: Bharat Bhushan
Signed-off-by: Kumar Gala -
Commit 6820fead ("powerpc/fsl_msi: Handle msi-available-ranges better") added
support for multiple ranges in the msi-available-ranges property, but it
miscalculated the MSIR index when multiple ranges are used.Signed-off-by: Timur Tabi
Acked-by: Scott Wood
Signed-off-by: Kumar Gala -
Add:
- Setup dts node for USB
- pin description and setup for SMC1 (serial interface)Update and cleanup mgcoge_defconfig:
- enable: TIPC, UBIFS, USB_GADGET driver, SQUASHFS, HIGHRES timers
POSIX_MQUEUE, EMBEDDED
- disable: EXT3, PPC_PMACSigned-off-by: Holger Brunck
Acked-by: Heiko Schocher
cc: Kumar Gala
Signed-off-by: Kumar Gala
07 Oct, 2011
10 commits
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If the L1 D-Cache is in write shadow mode the HW will auto-recover the
error. However we might still log the error and cause a machine check
(if L1CSR0[CPE] - Cache error checking enable). We should only treat
the non-write shadow case as non-recoverable.Signed-off-by: Kumar Gala
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We already have cpu a005 errata handler when instruction cannot be
recognized. Before we lookup the inst, there's type checking, and we also
need to handle it in errata handler when the type checking failed.Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala -
Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala -
Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala -
There's only p2041rdb board for official release, but the p2041 silicon
on the board can be converted to p2040 silicon without XAUI and L2 cache
function, then the board becomes p2040rdb board. so we use the file name
p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also
consistent with the board name under U-Boot.During the rename we make few other minor changes to the device tree:
* Move USB phy setting into p2041si.dtsi as its SoC not board defined
* Convert PCI clock-frequency to decimal to be more readableSigned-off-by: Mingkai Hu
Signed-off-by: Kumar Gala -
The P4080 silicon device tree was using PowerPC,4080 while the other
e500mc based SoCs used PowerPC,e500mc. Use the core name to be
consistent going forward.Signed-off-by: Kumar Gala
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Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
If CONFIG_PHYS_ADDR_T_64BIT is set, compilation of sbc8560 fails with
the following error:arch/powerpc/platforms/85xx/sbc8560.c: In function ‘sbc8560_bdrstcr_init’:
arch/powerpc/platforms/85xx/sbc8560.c:286: error: format ‘%x’ expects type ‘unsigned int’, but argument 2 has type ‘resource_size_t’Fix that by using %pR format instead of just printing the start of
resource.Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala
29 Sep, 2011
4 commits
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The firmware on old 970 blades supports some kind of takeover called
"TNK takeover" which will crash if we try to probe for OPAL takeover,
so don't do it.Signed-off-by: Benjamin Herrenschmidt
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The current L1 cache read event code 0x80082 only counts for thread 0. The
event code 0x280030 should be used to count events on thread 0 and 1. The
patch fixes the event code for the L1 cache read.The current L1 cache write event code 0x80086 only counts for thread 0. The
event code 0x180032 should be used to count events on thread 0 and 1. The
patch fixes the event code for the L1 cache write.FYI, the documentation lists three event codes for the L1 cache read event
and three event codes for the L1 cache write event. The event description
for the event codes is as follows:L1 cache read requests 0x80082 LSU 0 only
L1 cache read requests 0x8008A LSU 1 only
L1 cache read requests 0x80030 LSU 1 or LSU 0, counter 2 only.L1 cache store requests 0x80086 LSU 0 only
L1 cache store requests 0x8008E LSU 1 only
L1 cache store requests 0x80032 LSU 0 or LSU 1, counter 1 only.There can only be one request from either LSU 0 or 1 active at a time.
Signed-off-by: Carl Love
Acked-by: Paul Mackerras
Signed-off-by: Benjamin Herrenschmidt -
gcc (rightfully) complains that we are accessing beyond the
end of the fpr array (we do, to access the fpscr).The only sane thing to do (whether anything in that code can be
called remotely sane is debatable) is to special case fpscr and
handle it as a separate statement.I initially tried to do it it by making the array access conditional
to index < PT_FPSCR and using a 3rd else leg but for some reason gcc
was unable to understand it and still spewed the warning.So I ended up with something a tad more intricated but it seems to
build on 32-bit and on 64-bit with and without VSX.Signed-off-by: Benjamin Herrenschmidt
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Based on patch by David Gibson
xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit. In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
Book3e processors to the mix.Signed-off-by: Jimi Xenidis
Signed-off-by: Benjamin Herrenschmidt
26 Sep, 2011
1 commit
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We don't want to configure PCI Express Max Payload Size or
Max Read Request Size on systems that set that flag. The
firmware will have done it for us, and under hypervisors such
as pHyp we don't even see the parent switches and bridges and
thus can make no assumption on what values are safe to use.Signed-off-by: Benjamin Herrenschmidt
23 Sep, 2011
9 commits
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Some devices have a dma-window that starts at the address 0. This allows
DMA addresses to be mapped to this address and returned to drivers as a
valid DMA address. Some drivers may not behave well in this case, since
the address 0 is considered an error or not allocated.The solution to avoid this kind of error from happening is reserve the
page addressed as 0 so it cannot be allocated for a DMA mapping.Signed-off-by: Thadeu Lima de Souza Cascardo
Signed-off-by: Benjamin Herrenschmidt -
Commit 41151e77a4 ("powerpc: Hugetlb for BookE") added some
#ifdef CONFIG_MM_SLICES conditionals to hugetlb_get_unmapped_area()
and vma_mmu_pagesize(). Unfortunately this is not the correct config
symbol; it should be CONFIG_PPC_MM_SLICES. The result is that
attempting to use hugetlbfs on 64-bit Power server processors results
in an infinite stack recursion between get_unmapped_area() and
hugetlb_get_unmapped_area().This fixes it by changing the #ifdef to use CONFIG_PPC_MM_SLICES
in those functions and also in book3e_hugetlb_preload().Signed-off-by: Paul Mackerras
Signed-off-by: Benjamin Herrenschmidt -
Activate all MPC512x related boards. Also enable GPIO-driver, SPI driver
and at25 to test SPI. Enable DEVTMPFS. Bump to 3.1-rc6.Signed-off-by: Wolfram Sang
Cc: Anatolij Gustschin
Cc: Benjamin Herrenschmidt
Signed-off-by: Anatolij Gustschin -
Move the driver to the place where it is expected to be nowadays. Also
rename its CONFIG-name to match the rest and adapt the defconfigs.
Finally, move selection of REQUIRE_GPIOLIB or WANTS_OPTIONAL_GPIOLIB to
the platforms, because this option is per-platform and not per-driver.Signed-off-by: Wolfram Sang
Cc: Anatolij Gustschin
Cc: Grant Likely
Cc: Benjamin Herrenschmidt
Acked-by: Grant Likely
Signed-off-by: Anatolij Gustschin -
Audio support for the MPC5200 exists, so enable it by default.
Signed-off-by: Timur Tabi
Acked-by: Wolfram Sang
Signed-off-by: Anatolij Gustschin -
We use both MSCAN controllers on this board, so do not disable
them in the device tree.Signed-off-by: Anatolij Gustschin
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timer0 and timer1 pins are used as simple GPIO on this board.
Add gpio-controller and #gpio-cells properties to timer nodes
so that we can control gpio lines using available MPC52xx
GPT driver.Signed-off-by: Anatolij Gustschin
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Add new nodes to describe more hardware the board is
equipped with:
- two can nodes for SJA1000 on localbus
- pci node to support Coral-PA graphics controller
- serial node for SC28L92 DUART on localbus
- spi node for MSP430 deviceAlso correct i2c eeprom node name.
Signed-off-by: Heiko Schocher
Signed-off-by: Anatolij Gustschin -
Both, #address-cells and #size-cells properties are required
for spi bus node, so add them.Signed-off-by: Anatolij Gustschin
20 Sep, 2011
1 commit
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perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
Extent the POWER7 PMU driver with definitions for generic front-end and back-end
stall events.As explained in Ingo's original comment(8f62242246351b5a4bc0c1f00c0c7003edea128a
), the exact definitions of the stall events are very much processor specific asdifferent things mean different in their respective instruction pipeline. These
two Power7 raw events are the closest approximation to the concept detailed in
Ingo's comment.[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */
It means cycles when the Global Completion Table has no slots from this thread[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */
It means no groups completed and GCT not empty for this threadSigned-off-by: Anshuman Khandual
Signed-off-by: Benjamin Herrenschmidt
