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arch/arm/mach-omap2/board-am335xevm.c
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/* * Code for AM335X EVM. * * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/init.h> |
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#include <linux/i2c.h> |
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#include <linux/i2c/at24.h> |
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#include <linux/phy.h> |
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#include <linux/gpio.h> |
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#include <linux/spi/spi.h> #include <linux/spi/flash.h> |
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#include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/platform_device.h> |
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#include <linux/clk.h> #include <linux/err.h> |
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#include <linux/wl12xx.h> |
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#include <linux/ethtool.h> |
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/* LCD controller is similar to DA850 */ #include <video/da8xx-fb.h> |
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#include <mach/hardware.h> |
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#include <mach/board-am335xevm.h> |
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#include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> |
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#include <asm/hardware/asp.h> |
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#include <plat/irqs.h> #include <plat/board.h> #include <plat/common.h> |
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#include <plat/lcdc.h> |
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#include <plat/usb.h> |
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#include <plat/mmc.h> |
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#include "board-flash.h" #include "mux.h" #include "devices.h" |
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#include "hsmmc.h" |
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/* TLK PHY IDs */ #define TLK110_PHY_ID 0x2000A201 #define TLK110_PHY_MASK 0xfffffff0 |
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/* BBB PHY IDs */ #define BBB_PHY_ID 0x7c0f1 #define BBB_PHY_MASK 0xfffffffe |
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/* TLK110 PHY register offsets */ #define TLK110_COARSEGAIN_REG 0x00A3 #define TLK110_LPFHPF_REG 0x00AC #define TLK110_SPAREANALOG_REG 0x00B9 #define TLK110_VRCR_REG 0x00D0 #define TLK110_SETFFE_REG 0x0107 #define TLK110_FTSP_REG 0x0154 #define TLK110_ALFATPIDL_REG 0x002A #define TLK110_PSCOEF21_REG 0x0096 #define TLK110_PSCOEF3_REG 0x0097 #define TLK110_ALFAFACTOR1_REG 0x002C #define TLK110_ALFAFACTOR2_REG 0x0023 #define TLK110_CFGPS_REG 0x0095 #define TLK110_FTSPTXGAIN_REG 0x0150 #define TLK110_SWSCR3_REG 0x000B #define TLK110_SCFALLBACK_REG 0x0040 #define TLK110_PHYRCR_REG 0x001F /* TLK110 register writes values */ #define TLK110_COARSEGAIN_VAL 0x0000 #define TLK110_LPFHPF_VAL 0x8000 #define TLK110_SPANALOG_VAL 0x0000 #define TLK110_VRCR_VAL 0x0008 #define TLK110_SETFFE_VAL 0x0605 #define TLK110_FTSP_VAL 0x0255 #define TLK110_ALFATPIDL_VAL 0x7998 #define TLK110_PSCOEF21_VAL 0x3A20 #define TLK110_PSCOEF3_VAL 0x003F #define TLK110_ALFACTOR1_VAL 0xFF80 #define TLK110_ALFACTOR2_VAL 0x021C #define TLK110_CFGPS_VAL 0x0000 #define TLK110_FTSPTXGAIN_VAL 0x6A88 #define TLK110_SWSCR3_VAL 0x0000 #define TLK110_SCFALLBACK_VAL 0xC11D #define TLK110_PHYRCR_VAL 0x4000 #ifdef CONFIG_TLK110_WORKAROUND #define am335x_tlk110_phy_init()\ do { \ phy_register_fixup_for_uid(TLK110_PHY_ID,\ TLK110_PHY_MASK,\ am335x_tlk110_phy_fixup);\ } while (0); #else #define am335x_tlk110_phy_init() do { } while (0); #endif |
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/* Convert GPIO signal to GPIO pin number */ #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) |
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static const struct display_panel disp_panel = { WVGA, 32, 32, COLOR_ACTIVE, }; static struct lcd_ctrl_config lcd_cfg = { &disp_panel, .ac_bias = 255, .ac_bias_intrpt = 0, .dma_burst_sz = 16, .bpp = 32, .fdd = 0x80, .tft_alt_mode = 0, .stn_565_mode = 0, .mono_8bit_mode = 0, .invert_line_clock = 1, .invert_frm_clock = 1, .sync_edge = 0, .sync_ctrl = 1, .raster_order = 0, }; struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = { .manu_name = "ThreeFive", .controller_data = &lcd_cfg, .type = "TFC_S9700RTWV35TR_01B", }; |
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/* TSc controller */ #include <linux/input/ti_tscadc.h> static struct resource tsc_resources[] = { [0] = { .start = AM33XX_TSC_BASE, .end = AM33XX_TSC_BASE + SZ_8K - 1, .flags = IORESOURCE_MEM, }, [1] = { .start = AM33XX_IRQ_ADC_GEN, .end = AM33XX_IRQ_ADC_GEN, .flags = IORESOURCE_IRQ, }, }; static struct tsc_data am335x_touchscreen_data = { .wires = 4, }; static struct platform_device tsc_device = { .name = "tsc", .id = -1, .dev = { .platform_data = &am335x_touchscreen_data, }, .num_resources = ARRAY_SIZE(tsc_resources), .resource = tsc_resources, }; |
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static u8 am335x_iis_serializer_direction1[] = { INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, }; static struct snd_platform_data am335x_evm_snd_data1 = { .tx_dma_offset = 0x46400000, /* McASP1 */ .rx_dma_offset = 0x46400000, .op_mode = DAVINCI_MCASP_IIS_MODE, .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1), .tdm_slots = 2, .serial_dir = am335x_iis_serializer_direction1, .asp_chan_q = EVENTQ_2, .version = MCASP_VERSION_3, .txnumevt = 1, .rxnumevt = 1, }; |
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static struct omap2_hsmmc_info am335x_mmc[] __initdata = { { .mmc = 1, .caps = MMC_CAP_4_BIT_DATA, |
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.gpio_cd = GPIO_TO_PIN(0, 6), .gpio_wp = GPIO_TO_PIN(3, 18), |
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.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */ }, { .mmc = 0, /* will be set at runtime */ }, { .mmc = 0, /* will be set at runtime */ }, {} /* Terminator */ }; |
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#ifdef CONFIG_OMAP_MUX static struct omap_board_mux board_mux[] __initdata = { AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW | AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT), { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else #define board_mux NULL #endif /* module pin mux structure */ struct pinmux_config { const char *string_name; /* signal name format */ int val; /* Options for the mux register value */ }; |
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struct evm_dev_cfg { void (*device_init)(int evm_id, int profile); |
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/* |
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* If the device is required on both baseboard & daughter board (ex i2c), * specify DEV_ON_BASEBOARD |
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*/ |
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#define DEV_ON_BASEBOARD 0 #define DEV_ON_DGHTR_BRD 1 u32 device_on; |
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u32 profile; /* Profiles (0-7) in which the module is present */ }; |
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/* AM335X - CPLD Register Offsets */ #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */ #define CPLD_DEVICE_ID 0x04 /* CPLD identification */ #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */ #define CPLD_CFG_REG 0x10 /* Configuration Register */ static struct i2c_client *cpld_client; static u32 am335x_evm_id; |
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static struct omap_board_config_kernel am335x_evm_config[] __initdata = { }; |
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/* * EVM Config held in On-Board eeprom device. * * Header Format * * Name Size Contents * (Bytes) *------------------------------------------------------------- * Header 4 0xAA, 0x55, 0x33, 0xEE * * Board Name 8 Name for board in ASCII. * example "A33515BB" = "AM335X Low Cost EVM board" * * Version 4 Hardware version code for board in * in ASCII. "1.0A" = rev.01.0A * * Serial Number 12 Serial number of the board. This is a 12 * character string which is WWYY4P16nnnn, where * WW = 2 digit week of the year of production * YY = 2 digit year of production * nnnn = incrementing board number * * Configuration option 32 Codes(TBD) to show the configuration * setup on this board. * * Available 32720 Available space for other non-volatile * data. */ struct am335x_evm_eeprom_config { u32 header; u8 name[8]; |
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char version[4]; |
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u8 serial[12]; u8 opt[32]; }; static struct am335x_evm_eeprom_config config; static bool daughter_brd_detected; |
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#define GP_EVM_REV_IS_1_0A 0x1 #define GP_EVM_REV_IS_1_1A 0x2 #define GP_EVM_REV_IS_UNKNOWN 0xFF static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN; |
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unsigned int gigabit_enable = 1; |
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#define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */ #define EEPROM_NO_OF_MAC_ADDR 3 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN]; |
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#define AM335X_EEPROM_HEADER 0xEE3355AA |
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/* current profile if exists else PROFILE_0 on error */ static u32 am335x_get_profile_selection(void) { int val = 0; if (!cpld_client) /* error checking is not done in func's calling this routine. so return profile 0 on error */ return 0; val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG); if (val < 0) return 0; /* default to Profile 0 on Error */ else return val & 0x7; } |
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/* Module pin mux for LCDC */ static struct pinmux_config lcdc_pin_mux[] = { {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA}, {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {NULL, 0}, }; |
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static struct pinmux_config tsc_pin_mux[] = { {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN}, {NULL, 0}, }; |
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/* Pin mux for nand flash module */ static struct pinmux_config nand_pin_mux[] = { {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA}, {NULL, 0}, }; |
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/* Module pin mux for SPI fash */ static struct pinmux_config spi0_pin_mux[] = { {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP | AM33XX_INPUT_EN}, {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP | AM33XX_INPUT_EN}, {NULL, 0}, }; /* Module pin mux for SPI flash */ static struct pinmux_config spi1_pin_mux[] = { {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | AM33XX_PULL_UP | AM33XX_INPUT_EN}, {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL | AM33XX_PULL_UP | AM33XX_INPUT_EN}, {NULL, 0}, }; |
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/* Module pin mux for rgmii1 */ static struct pinmux_config rgmii1_pin_mux[] = { {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, {NULL, 0}, }; /* Module pin mux for rgmii2 */ static struct pinmux_config rgmii2_pin_mux[] = { {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT}, {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN}, {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, {NULL, 0}, }; /* Module pin mux for mii1 */ static struct pinmux_config mii1_pin_mux[] = { {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, {NULL, 0}, }; |
f1e12bb92 arm:omap:am33xx: ... |
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/* Module pin mux for rmii1 */ static struct pinmux_config rmii1_pin_mux[] = { {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT}, {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN}, {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP}, {NULL, 0}, }; |
b5c4f8f49 arm:omap:am33xx: ... |
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static struct pinmux_config i2c1_pin_mux[] = { {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW | AM33XX_PULL_ENBL | AM33XX_INPUT_EN}, {NULL, 0}, }; |
3fd0e971c AM335X: NAND: NAN... |
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|
a83ee205d arm:omap:am33xx: ... |
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/* Module pin mux for mcasp1 */ static struct pinmux_config mcasp1_pin_mux[] = { {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, {NULL, 0}, }; |
9ba3872ab arm:omap:am33xx: ... |
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/* Module pin mux for mmc0 */ static struct pinmux_config mmc0_pin_mux[] = { {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
f80ad5875 ARM:omaP:am33xx; ... |
508 509 |
{"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, |
9ba3872ab arm:omap:am33xx: ... |
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{NULL, 0}, }; static struct pinmux_config mmc0_no_cd_pin_mux[] = { {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, {NULL, 0}, }; /* Module pin mux for mmc1 */ static struct pinmux_config mmc1_pin_mux[] = { {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, |
f375e5d52 ARM: OMAP: AM335x... |
536 537 |
{"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, |
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538 539 |
{NULL, 0}, }; |
06b9f00bc arm:omap:am33xx: ... |
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/* Module pin mux for uart3 */ static struct pinmux_config uart3_pin_mux[] = { {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP}, {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL}, {NULL, 0}, }; |
609691c19 ARM:omap:am33xx: ... |
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/* * @pin_mux - single module pin-mux structure which defines pin-mux * details for all its pins. */ static void setup_pin_mux(struct pinmux_config *pin_mux) { int i; for (i = 0; pin_mux->string_name != NULL; pin_mux++) omap_mux_init_signal(pin_mux->string_name, pin_mux->val); } /* * @evm_id - evm id which needs to be configured * @dev_cfg - single evm structure which includes * all module inits, pin-mux defines * @profile - if present, else PROFILE_NONE * @dghtr_brd_flg - Whether Daughter board is present or not */ static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg, int profile) { int i; /* * Only General Purpose & Industrial Auto Motro Control * EVM has profiles. So check if this evm has profile. * If not, ignore the profile comparison */ /* * If the device is on baseboard, directly configure it. Else (device on * Daughter board), check if the daughter card is detected. */ if (profile == PROFILE_NONE) { for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { if (dev_cfg->device_on == DEV_ON_BASEBOARD) dev_cfg->device_init(evm_id, profile); else if (daughter_brd_detected == true) dev_cfg->device_init(evm_id, profile); } } else { for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) { if (dev_cfg->profile & profile) { if (dev_cfg->device_on == DEV_ON_BASEBOARD) dev_cfg->device_init(evm_id, profile); else if (daughter_brd_detected == true) dev_cfg->device_init(evm_id, profile); } } } } |
6de8f7503 ARM:omap:am33xx: ... |
599 |
#define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7) |
eb3dad1ce am335x: add musb ... |
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/* pinmux for usb0 drvvbus */ static struct pinmux_config usb0_pin_mux[] = { {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {NULL, 0}, }; /* pinmux for usb1 drvvbus */ static struct pinmux_config usb1_pin_mux[] = { {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {NULL, 0}, }; |
6de8f7503 ARM:omap:am33xx: ... |
611 612 613 614 615 |
/* Module pin mux for eCAP0 */ static struct pinmux_config ecap0_pin_mux[] = { {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT}, {NULL, 0}, }; |
9d01c45e9 board-am335xevm: ... |
616 617 618 |
#define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30) #define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17) #define AM335XEVM_BT_ENABLE_GPIO GPIO_TO_PIN(1, 31) |
ff56fdbc6 arm:omap:am33xx:F... |
619 |
struct wl12xx_platform_data am335xevm_wlan_data = { |
9d01c45e9 board-am335xevm: ... |
620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 |
.irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO), .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */ .board_tcxo_clock = WL12XX_REFCLOCK_26, /* 26 MHz */ }; /* Module pin mux for wlan and bluetooth */ static struct pinmux_config mmc2_wl12xx_pin_mux[] = { {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, {NULL, 0}, }; static struct pinmux_config uart1_wl12xx_pin_mux[] = { {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT}, {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT}, {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL}, {NULL, 0}, }; static struct pinmux_config wl12xx_pin_mux[] = { {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT}, {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT}, {NULL, 0}, }; |
d88fde8d0 AM335x: Backlight... |
650 651 652 |
static int backlight_enable = false; static void enable_ecap0(int evm_id, int profile) |
6de8f7503 ARM:omap:am33xx: ... |
653 |
{ |
d88fde8d0 AM335x: Backlight... |
654 655 |
backlight_enable = true; } |
6de8f7503 ARM:omap:am33xx: ... |
656 |
|
d88fde8d0 AM335x: Backlight... |
657 658 659 |
static int __init ecap0_init(void) { int status = 0; |
6de8f7503 ARM:omap:am33xx: ... |
660 |
|
d88fde8d0 AM335x: Backlight... |
661 662 |
if (backlight_enable) { setup_pin_mux(ecap0_pin_mux); |
6de8f7503 ARM:omap:am33xx: ... |
663 |
|
d88fde8d0 AM335x: Backlight... |
664 665 666 667 668 669 670 671 672 |
status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl "); if (status < 0) pr_warn("Failed to request gpio for LCD backlight "); gpio_direction_output(AM335X_LCD_BL_PIN, 1); } return status; |
6de8f7503 ARM:omap:am33xx: ... |
673 |
} |
d88fde8d0 AM335x: Backlight... |
674 |
late_initcall(ecap0_init); |
6de8f7503 ARM:omap:am33xx: ... |
675 |
|
b2471dff7 AM335X: Enable LC... |
676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 |
static int __init conf_disp_pll(int rate) { struct clk *disp_pll; int ret = -EINVAL; disp_pll = clk_get(NULL, "dpll_disp_ck"); if (IS_ERR(disp_pll)) { pr_err("Cannot clk_get disp_pll "); goto out; } ret = clk_set_rate(disp_pll, rate); clk_put(disp_pll); out: return ret; } static void lcdc_init(int evm_id, int profile) { setup_pin_mux(lcdc_pin_mux); if (conf_disp_pll(300000000)) { pr_info("Failed configure display PLL, not attempting to" "register LCDC "); return; } if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata)) pr_info("Failed to register LCDC device "); return; } |
1da3d8fa1 arm:omap:am33xx: ... |
711 712 713 714 715 716 717 718 719 |
static void tsc_init(int evm_id, int profile) { int err; setup_pin_mux(tsc_pin_mux); err = platform_device_register(&tsc_device); if (err) pr_err("failed to register touchscreen device "); } |
2b2bcf286 AM335X: CPSW pinm... |
720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 |
static void rgmii1_init(int evm_id, int profile) { setup_pin_mux(rgmii1_pin_mux); return; } static void rgmii2_init(int evm_id, int profile) { setup_pin_mux(rgmii2_pin_mux); return; } static void mii1_init(int evm_id, int profile) { setup_pin_mux(mii1_pin_mux); return; } |
b2471dff7 AM335X: Enable LC... |
737 |
|
f1e12bb92 arm:omap:am33xx: ... |
738 739 740 741 742 |
static void rmii1_init(int evm_id, int profile) { setup_pin_mux(rmii1_pin_mux); return; } |
eb3dad1ce am335x: add musb ... |
743 744 745 746 747 748 749 750 751 752 753 |
static void usb0_init(int evm_id, int profile) { setup_pin_mux(usb0_pin_mux); return; } static void usb1_init(int evm_id, int profile) { setup_pin_mux(usb1_pin_mux); return; } |
06b9f00bc arm:omap:am33xx: ... |
754 755 756 757 758 759 |
/* setup uart3 */ static void uart3_init(int evm_id, int profile) { setup_pin_mux(uart3_pin_mux); return; } |
3fd0e971c AM335X: NAND: NAN... |
760 761 762 763 |
/* NAND partition information */ static struct mtd_partition am335x_nand_partitions[] = { /* All the partition sizes are listed in terms of NAND block size */ { |
d69e113a9 arm:omap:am335x: ... |
764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 |
.name = "SPL", .offset = 0, /* Offset = 0x0 */ .size = SZ_128K, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "SPL.backup1", .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */ .size = SZ_128K, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "SPL.backup2", .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */ .size = SZ_128K, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "SPL.backup3", .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */ .size = SZ_128K, |
3fd0e971c AM335X: NAND: NAN... |
785 786 787 788 |
.mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "U-Boot", |
d69e113a9 arm:omap:am335x: ... |
789 790 |
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ .size = 15 * SZ_128K, |
3fd0e971c AM335X: NAND: NAN... |
791 792 793 794 |
.mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "U-Boot Env", |
d69e113a9 arm:omap:am335x: ... |
795 |
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ |
3fd0e971c AM335X: NAND: NAN... |
796 797 798 799 |
.size = 1 * SZ_128K, }, { .name = "Kernel", |
d69e113a9 arm:omap:am335x: ... |
800 801 |
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ .size = 40 * SZ_128K, |
3fd0e971c AM335X: NAND: NAN... |
802 803 804 |
}, { .name = "File System", |
d69e113a9 arm:omap:am335x: ... |
805 |
.offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ |
3fd0e971c AM335X: NAND: NAN... |
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.size = MTDPART_SIZ_FULL, }, }; |
636a1595c AM335x: SPI devic... |
809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 |
/* SPI 0/1 Platform Data */ /* SPI flash information */ static struct mtd_partition am335x_spi_partitions[] = { /* All the partition sizes are listed in terms of erase size */ { .name = "U-Boot-min", .offset = 0, .size = SZ_128K, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "U-Boot", .offset = MTDPART_OFS_APPEND, .size = 2 * SZ_128K, .mask_flags = MTD_WRITEABLE, /* force read-only */ }, { .name = "U-Boot Env", .offset = MTDPART_OFS_APPEND, .size = 2 * SZ_4K, }, { .name = "Kernel", .offset = MTDPART_OFS_APPEND, .size = 20 * SZ_128K, }, { .name = "File System", .offset = MTDPART_OFS_APPEND, .size = MTDPART_SIZ_FULL, /* size ~= 1.1 MiB */ } }; static const struct flash_platform_data am335x_spi_flash = { .type = "w25q64", .name = "spi_flash", .parts = am335x_spi_partitions, .nr_parts = ARRAY_SIZE(am335x_spi_partitions), }; /* * SPI Flash works at 80Mhz however SPI Controller works at 48MHz. * So setup Max speed to be less than that of Controller speed */ static struct spi_board_info am335x_spi0_slave_info[] = { { .modalias = "m25p80", .platform_data = &am335x_spi_flash, .irq = -1, .max_speed_hz = 12000000, .bus_num = 1, .chip_select = 0, }, }; static struct spi_board_info am335x_spi1_slave_info[] = { { .modalias = "m25p80", .platform_data = &am335x_spi_flash, .irq = -1, .max_speed_hz = 12000000, .bus_num = 2, .chip_select = 0, }, }; |
3fd0e971c AM335X: NAND: NAN... |
874 875 876 877 878 879 |
static void evm_nand_init(int evm_id, int profile) { setup_pin_mux(nand_pin_mux); board_nand_init(am335x_nand_partitions, ARRAY_SIZE(am335x_nand_partitions), 0, 0); } |
ff56fdbc6 arm:omap:am33xx:F... |
880 |
static struct i2c_board_info am335x_i2c_boardinfo1[] = { |
b5c4f8f49 arm:omap:am33xx: ... |
881 |
{ |
a83ee205d arm:omap:am33xx: ... |
882 |
I2C_BOARD_INFO("tlv320aic3x", 0x1b), |
ff56fdbc6 arm:omap:am33xx:F... |
883 |
}, |
b5c4f8f49 arm:omap:am33xx: ... |
884 885 886 887 888 889 890 891 892 |
}; static void i2c1_init(int evm_id, int profile) { setup_pin_mux(i2c1_pin_mux); omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1, ARRAY_SIZE(am335x_i2c_boardinfo1)); return; } |
a83ee205d arm:omap:am33xx: ... |
893 894 895 896 897 898 899 900 |
/* Setup McASP 1 */ static void mcasp1_init(int evm_id, int profile) { /* Configure McASP */ setup_pin_mux(mcasp1_pin_mux); am335x_register_mcasp1(&am335x_evm_snd_data1); return; } |
9ba3872ab arm:omap:am33xx: ... |
901 902 903 904 905 906 |
static void mmc1_init(int evm_id, int profile) { setup_pin_mux(mmc1_pin_mux); am335x_mmc[1].mmc = 2; am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; |
f80ad5875 ARM:omaP:am33xx; ... |
907 908 |
am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15); am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14); |
9ba3872ab arm:omap:am33xx: ... |
909 910 911 912 913 |
am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ /* mmc will be initialized when mmc0_init is called */ return; } |
9d01c45e9 board-am335xevm: ... |
914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 |
static void mmc2_wl12xx_init(int evm_id, int profile) { setup_pin_mux(mmc2_wl12xx_pin_mux); am335x_mmc[1].mmc = 3; am335x_mmc[1].name = "wl1271"; am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD | MMC_PM_KEEP_POWER; am335x_mmc[1].nonremovable = true; am335x_mmc[1].gpio_cd = -EINVAL; am335x_mmc[1].gpio_wp = -EINVAL; am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ /* mmc will be initialized when mmc0_init is called */ return; } static void uart1_wl12xx_init(int evm_id, int profile) { setup_pin_mux(uart1_wl12xx_pin_mux); } static void wl12xx_bluetooth_enable(void) { int status = gpio_request(AM335XEVM_BT_ENABLE_GPIO, "bt_en "); if (status < 0) pr_err("Failed to request gpio for bt_enable"); pr_info("Enable bluetooth... "); gpio_direction_output(AM335XEVM_BT_ENABLE_GPIO, 0); msleep(1); gpio_set_value(AM335XEVM_BT_ENABLE_GPIO, 1); } static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd) { if (on) gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 1); else gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 0); return 0; } static void wl12xx_init(int evm_id, int profile) { struct device *dev; struct omap_mmc_platform_data *pdata; int ret; wl12xx_bluetooth_enable(); if (wl12xx_set_platform_data(&am335xevm_wlan_data)) pr_err("error setting wl12xx data "); dev = am335x_mmc[1].dev; if (!dev) { pr_err("wl12xx mmc device initialization failed "); goto out; } pdata = dev->platform_data; if (!pdata) { pr_err("Platfrom data of wl12xx device not set "); goto out; } ret = gpio_request_one(AM335XEVM_WLAN_PMENA_GPIO, GPIOF_OUT_INIT_LOW, "wlan_en"); if (ret) { pr_err("Error requesting wlan enable gpio: %d ", ret); goto out; } setup_pin_mux(wl12xx_pin_mux); pdata->slots[0].set_power = wl12xx_set_power; out: return; } |
9ba3872ab arm:omap:am33xx: ... |
1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 |
static void mmc0_init(int evm_id, int profile) { setup_pin_mux(mmc0_pin_mux); omap2_hsmmc_init(am335x_mmc); return; } static void mmc0_no_cd_init(int evm_id, int profile) { setup_pin_mux(mmc0_no_cd_pin_mux); omap2_hsmmc_init(am335x_mmc); return; } |
636a1595c AM335x: SPI devic... |
1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 |
/* setup spi0 */ static void spi0_init(int evm_id, int profile) { setup_pin_mux(spi0_pin_mux); spi_register_board_info(am335x_spi0_slave_info, ARRAY_SIZE(am335x_spi0_slave_info)); return; } /* setup spi1 */ static void spi1_init(int evm_id, int profile) { setup_pin_mux(spi1_pin_mux); spi_register_board_info(am335x_spi1_slave_info, ARRAY_SIZE(am335x_spi1_slave_info)); return; } |
72e9d5232 ARM:omap:am335x: ... |
1032 1033 1034 1035 1036 1037 1038 1039 |
static int beaglebone_phy_fixup(struct phy_device *phydev) { phydev->supported &= ~(SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full); return 0; } |
17bd4260b arm:omap:am33xx: ... |
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 |
#ifdef CONFIG_TLK110_WORKAROUND static int am335x_tlk110_phy_fixup(struct phy_device *phydev) { unsigned int val; /* This is done as a workaround to support TLK110 rev1.0 phy */ val = phy_read(phydev, TLK110_COARSEGAIN_REG); phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL)); val = phy_read(phydev, TLK110_LPFHPF_REG); phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL)); val = phy_read(phydev, TLK110_SPAREANALOG_REG); phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL)); val = phy_read(phydev, TLK110_VRCR_REG); phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL)); val = phy_read(phydev, TLK110_SETFFE_REG); phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL)); val = phy_read(phydev, TLK110_FTSP_REG); phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL)); val = phy_read(phydev, TLK110_ALFATPIDL_REG); phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL)); val = phy_read(phydev, TLK110_PSCOEF21_REG); phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL)); val = phy_read(phydev, TLK110_PSCOEF3_REG); phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL)); val = phy_read(phydev, TLK110_ALFAFACTOR1_REG); phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL)); val = phy_read(phydev, TLK110_ALFAFACTOR2_REG); phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL)); val = phy_read(phydev, TLK110_CFGPS_REG); phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL)); val = phy_read(phydev, TLK110_FTSPTXGAIN_REG); phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL)); val = phy_read(phydev, TLK110_SWSCR3_REG); phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL)); val = phy_read(phydev, TLK110_SCFALLBACK_REG); phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL)); val = phy_read(phydev, TLK110_PHYRCR_REG); phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL)); return 0; } #endif |
609691c19 ARM:omap:am33xx: ... |
1097 1098 |
/* Low-Cost EVM */ static struct evm_dev_cfg low_cost_evm_dev_cfg[] = { |
2b2bcf286 AM335X: CPSW pinm... |
1099 |
{rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
eb3dad1ce am335x: add musb ... |
1100 1101 |
{usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
3fd0e971c AM335X: NAND: NAN... |
1102 |
{evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
609691c19 ARM:omap:am33xx: ... |
1103 1104 1105 1106 1107 |
{NULL, 0, 0}, }; /* General Purpose EVM */ static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = { |
d88fde8d0 AM335x: Backlight... |
1108 |
{enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | |
6de8f7503 ARM:omap:am33xx: ... |
1109 |
PROFILE_2 | PROFILE_7) }, |
b2471dff7 AM335X: Enable LC... |
1110 1111 |
{lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | PROFILE_2 | PROFILE_7) }, |
1da3d8fa1 arm:omap:am33xx: ... |
1112 1113 |
{tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 | PROFILE_2 | PROFILE_7) }, |
2b2bcf286 AM335X: CPSW pinm... |
1114 1115 1116 |
{rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 | PROFILE_4 | PROFILE_6) }, |
eb3dad1ce am335x: add musb ... |
1117 1118 |
{usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
3fd0e971c AM335X: NAND: NAN... |
1119 1120 |
{evm_nand_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)}, |
b5c4f8f49 arm:omap:am33xx: ... |
1121 |
{i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)}, |
f375e5d52 ARM: OMAP: AM335x... |
1122 |
{mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7) }, |
9ba3872ab arm:omap:am33xx: ... |
1123 |
{mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2}, |
fba07502c arm:omap:am33xx: ... |
1124 |
{mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | |
2753ad8ee ARM:omap:am33xx: ... |
1125 |
PROFILE_5)}, |
9ba3872ab arm:omap:am33xx: ... |
1126 1127 |
{mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)}, {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5}, |
636a1595c AM335x: SPI devic... |
1128 |
{spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2}, |
fba07502c arm:omap:am33xx: ... |
1129 |
{uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | |
2753ad8ee ARM:omap:am33xx: ... |
1130 1131 |
PROFILE_5)}, {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)}, |
609691c19 ARM:omap:am33xx: ... |
1132 1133 1134 1135 1136 |
{NULL, 0, 0}, }; /* Industrial Auto Motor Control EVM */ static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = { |
2b2bcf286 AM335X: CPSW pinm... |
1137 |
{mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
eb3dad1ce am335x: add musb ... |
1138 1139 |
{usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL}, {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
3fd0e971c AM335X: NAND: NAN... |
1140 |
{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
636a1595c AM335x: SPI devic... |
1141 |
{spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
06b9f00bc arm:omap:am33xx: ... |
1142 |
{uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL}, |
62704725a arm:omap:am33xx: ... |
1143 1144 |
{i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL}, |
609691c19 ARM:omap:am33xx: ... |
1145 1146 1147 1148 1149 |
{NULL, 0, 0}, }; /* IP-Phone EVM */ static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = { |
d88fde8d0 AM335x: Backlight... |
1150 |
{enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
b2471dff7 AM335X: Enable LC... |
1151 |
{lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
1da3d8fa1 arm:omap:am33xx: ... |
1152 |
{tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
2b2bcf286 AM335X: CPSW pinm... |
1153 1154 |
{rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
eb3dad1ce am335x: add musb ... |
1155 1156 |
{usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
3fd0e971c AM335X: NAND: NAN... |
1157 |
{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
b5c4f8f49 arm:omap:am33xx: ... |
1158 |
{i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
a83ee205d arm:omap:am33xx: ... |
1159 |
{mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE}, |
9ba3872ab arm:omap:am33xx: ... |
1160 |
{mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
609691c19 ARM:omap:am33xx: ... |
1161 1162 |
{NULL, 0, 0}, }; |
c8f997ab0 ARM:omap:am335x: ... |
1163 1164 |
/* Beaglebone < Rev A3 */ static struct evm_dev_cfg beaglebone_old_dev_cfg[] = { |
f1e12bb92 arm:omap:am33xx: ... |
1165 1166 1167 1168 |
{rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, |
f1e12bb92 arm:omap:am33xx: ... |
1169 1170 |
{NULL, 0, 0}, }; |
c8f997ab0 ARM:omap:am335x: ... |
1171 1172 1173 1174 1175 1176 1177 1178 |
/* Beaglebone Rev A3 and after */ static struct evm_dev_cfg beaglebone_dev_cfg[] = { {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE}, {NULL, 0, 0}, }; |
609691c19 ARM:omap:am33xx: ... |
1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 |
static void setup_low_cost_evm(void) { pr_info("The board is a AM335x Low Cost EVM. "); _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE); } static void setup_general_purpose_evm(void) { u32 prof_sel = am335x_get_profile_selection(); |
609691c19 ARM:omap:am33xx: ... |
1190 1191 |
pr_info("The board is general purpose EVM in profile %d ", prof_sel); |
f375e5d52 ARM: OMAP: AM335x... |
1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 |
if (!strncmp("1.1A", config.version, 4)) { pr_info("EVM version is %s ", config.version); gp_evm_revision = GP_EVM_REV_IS_1_1A; } else if (!strncmp("1.0A", config.version, 4)) { pr_info("EVM version is %s ", config.version); gp_evm_revision = GP_EVM_REV_IS_1_0A; } else { pr_err("EVM version read fail, falling back to Rev1.1A"); gp_evm_revision = GP_EVM_REV_IS_1_1A; } |
dfb4c854f arm:omap:cpsw: En... |
1204 1205 1206 1207 |
if (gp_evm_revision == GP_EVM_REV_IS_1_0A) gigabit_enable = 0; else if (gp_evm_revision == GP_EVM_REV_IS_1_1A) gigabit_enable = 1; |
609691c19 ARM:omap:am33xx: ... |
1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 |
_configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel)); } static void setup_ind_auto_motor_ctrl_evm(void) { u32 prof_sel = am335x_get_profile_selection(); pr_info("The board is an industrial automation EVM in profile %d ", prof_sel); /* Only Profile 0 is supported */ if ((1L << prof_sel) != PROFILE_0) { pr_err("AM335X: Only Profile 0 is supported "); pr_err("Assuming profile 0 & continuing "); prof_sel = PROFILE_0; } _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg, PROFILE_0); |
17bd4260b arm:omap:am33xx: ... |
1230 1231 1232 1233 1234 |
/* Fillup global evmid */ am33xx_evmid_fillup(IND_AUT_MTR_EVM); /* Initialize TLK110 PHY registers for phy version 1.0 */ am335x_tlk110_phy_init(); |
609691c19 ARM:omap:am33xx: ... |
1235 1236 1237 1238 1239 1240 1241 1242 1243 |
} static void setup_ip_phone_evm(void) { pr_info("The board is an IP phone EVM "); _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE); } |
c8f997ab0 ARM:omap:am335x: ... |
1244 1245 |
/* BeagleBone < Rev A3 */ static void setup_beaglebone_old(void) |
f1e12bb92 arm:omap:am33xx: ... |
1246 |
{ |
c8f997ab0 ARM:omap:am335x: ... |
1247 1248 |
pr_info("The board is a AM335x Beaglebone < Rev A3. "); |
f1e12bb92 arm:omap:am33xx: ... |
1249 |
|
c8f997ab0 ARM:omap:am335x: ... |
1250 |
/* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ |
49bf9b22b ARM:omap:am33xx: ... |
1251 |
am335x_mmc[0].gpio_wp = -EINVAL; |
c8f997ab0 ARM:omap:am335x: ... |
1252 |
_configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE); |
72e9d5232 ARM:omap:am335x: ... |
1253 1254 1255 |
phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK, beaglebone_phy_fixup); |
f1e12bb92 arm:omap:am33xx: ... |
1256 |
} |
c8f997ab0 ARM:omap:am335x: ... |
1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 |
/* BeagleBone after Rev A3 */ static void setup_beaglebone(void) { pr_info("The board is a AM335x Beaglebone. "); /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */ am335x_mmc[0].gpio_wp = -EINVAL; _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE); } |
1ca8aed50 arm:omap:am33xx: ... |
1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 |
static void am335x_setup_daughter_board(struct memory_accessor *m, void *c) { u8 tmp; int ret; /* * try reading a byte from the EEPROM to see if it is * present. We could read a lot more, but that would * just slow the boot process and we have all the information * we need from the EEPROM on the base board anyway. */ ret = m->read(m, &tmp, 0, sizeof(u8)); if (ret == sizeof(u8)) { pr_info("Detected a daughter card on AM335x EVM.."); daughter_brd_detected = true; } else { pr_info("No daughter card found "); daughter_brd_detected = false; } } static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context) { int ret; char tmp[10]; |
17bd4260b arm:omap:am33xx: ... |
1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 |
/* 1st get the MAC address from EEPROM */ ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr, EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr)); if (ret != sizeof(am335x_mac_addr)) { pr_warning("AM335X: EVM Config read fail: %d ", ret); return; } /* Fillup global mac id */ am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0], &am335x_mac_addr[1][0]); |
1ca8aed50 arm:omap:am33xx: ... |
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 |
/* get board specific data */ ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config)); if (ret != sizeof(config)) { pr_warning("AM335X EVM config read fail, read %d bytes ", ret); return; } if (config.header != AM335X_EEPROM_HEADER) { pr_warning("AM335X: wrong header 0x%x, expected 0x%x ", config.header, AM335X_EEPROM_HEADER); |
609691c19 ARM:omap:am33xx: ... |
1319 |
goto out; |
1ca8aed50 arm:omap:am33xx: ... |
1320 1321 1322 1323 1324 1325 |
} if (strncmp("A335", config.name, 4)) { pr_err("Board %s doesn't look like an AM335x board ", config.name); |
609691c19 ARM:omap:am33xx: ... |
1326 |
goto out; |
1ca8aed50 arm:omap:am33xx: ... |
1327 |
} |
c8f997ab0 ARM:omap:am335x: ... |
1328 |
snprintf(tmp, sizeof(config.name) + 1, "%s", config.name); |
1ca8aed50 arm:omap:am33xx: ... |
1329 1330 |
pr_info("Board name: %s ", tmp); |
c8f997ab0 ARM:omap:am335x: ... |
1331 1332 1333 |
snprintf(tmp, sizeof(config.version) + 1, "%s", config.version); pr_info("Board version: %s ", tmp); |
f1e12bb92 arm:omap:am33xx: ... |
1334 1335 |
if (!strncmp("A335BONE", config.name, 8)) { daughter_brd_detected = false; |
c8f997ab0 ARM:omap:am335x: ... |
1336 1337 1338 1339 1340 |
if(!strncmp("00A1", config.version, 4) || !strncmp("00A2", config.version, 4)) setup_beaglebone_old(); else setup_beaglebone(); |
f1e12bb92 arm:omap:am33xx: ... |
1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 |
} else { /* only 6 characters of options string used for now */ snprintf(tmp, 7, "%s", config.opt); pr_info("SKU: %s ", tmp); if (!strncmp("SKU#00", config.opt, 6)) setup_low_cost_evm(); else if (!strncmp("SKU#01", config.opt, 6)) setup_general_purpose_evm(); else if (!strncmp("SKU#02", config.opt, 6)) setup_ind_auto_motor_ctrl_evm(); else if (!strncmp("SKU#03", config.opt, 6)) setup_ip_phone_evm(); else goto out; } |
2b2bcf286 AM335X: CPSW pinm... |
1358 1359 1360 1361 |
/* Initialize cpsw after board detection is completed as board * information is required for configuring phy address and hence * should be call only after board detection */ |
dfb4c854f arm:omap:cpsw: En... |
1362 |
am33xx_cpsw_init(gigabit_enable); |
2b2bcf286 AM335X: CPSW pinm... |
1363 |
|
1ca8aed50 arm:omap:am33xx: ... |
1364 |
return; |
609691c19 ARM:omap:am33xx: ... |
1365 1366 |
out: /* |
f1e12bb92 arm:omap:am33xx: ... |
1367 |
* If the EEPROM hasn't been programed or an incorrect header |
c8f997ab0 ARM:omap:am335x: ... |
1368 1369 |
* or board name are read, assume this is an old beaglebone board * (< Rev A3) |
609691c19 ARM:omap:am33xx: ... |
1370 1371 |
*/ pr_err("Could not detect any board, falling back to: " |
c8f997ab0 ARM:omap:am335x: ... |
1372 1373 |
"Beaglebone (< Rev A3) with no daughter card connected "); |
f1e12bb92 arm:omap:am33xx: ... |
1374 |
daughter_brd_detected = false; |
c8f997ab0 ARM:omap:am335x: ... |
1375 |
setup_beaglebone_old(); |
609691c19 ARM:omap:am33xx: ... |
1376 |
|
2b2bcf286 AM335X: CPSW pinm... |
1377 1378 1379 1380 |
/* Initialize cpsw after board detection is completed as board * information is required for configuring phy address and hence * should be call only after board detection */ |
dfb4c854f arm:omap:cpsw: En... |
1381 1382 |
am33xx_cpsw_init(gigabit_enable); |
1ca8aed50 arm:omap:am33xx: ... |
1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 |
} static struct at24_platform_data am335x_daughter_board_eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, .flags = AT24_FLAG_ADDR16, .setup = am335x_setup_daughter_board, .context = (void *)NULL, }; static struct at24_platform_data am335x_baseboard_eeprom_info = { .byte_len = (256*1024) / 8, .page_size = 64, .flags = AT24_FLAG_ADDR16, .setup = am335x_evm_setup, .context = (void *)NULL, }; /* * Daughter board Detection. * Every board has a ID memory (EEPROM) on board. We probe these devices at * machine init, starting from daughter board and ending with baseboard. * Assumptions : * 1. probe for i2c devices are called in the order they are included in * the below struct. Daughter boards eeprom are probed 1st. Baseboard * eeprom probe is called last. */ static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = { { /* Daughter Board EEPROM */ I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR), .platform_data = &am335x_daughter_board_eeprom_info, }, { /* Baseboard board EEPROM */ I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR), .platform_data = &am335x_baseboard_eeprom_info, }, { I2C_BOARD_INFO("cpld_reg", 0x35), }, { I2C_BOARD_INFO("tlc59108", 0x40), }, }; |
eb3dad1ce am335x: add musb ... |
1429 1430 1431 1432 1433 1434 |
static struct omap_musb_board_data musb_board_data = { .interface_type = MUSB_INTERFACE_ULPI, .mode = MUSB_OTG, .power = 500, .instances = 1, }; |
609691c19 ARM:omap:am33xx: ... |
1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 |
static int cpld_reg_probe(struct i2c_client *client, const struct i2c_device_id *id) { cpld_client = client; return 0; } static int __devexit cpld_reg_remove(struct i2c_client *client) { cpld_client = NULL; return 0; } static const struct i2c_device_id cpld_reg_id[] = { { "cpld_reg", 0 }, { } }; static struct i2c_driver cpld_reg_driver = { .driver = { .name = "cpld_reg", }, .probe = cpld_reg_probe, .remove = cpld_reg_remove, .id_table = cpld_reg_id, }; static void evm_init_cpld(void) { i2c_add_driver(&cpld_reg_driver); } |
1ca8aed50 arm:omap:am33xx: ... |
1466 1467 |
static void __init am335x_evm_i2c_init(void) { |
609691c19 ARM:omap:am33xx: ... |
1468 1469 1470 1471 |
/* Initially assume Low Cost EVM Config */ am335x_evm_id = LOW_COST_EVM; evm_init_cpld(); |
1ca8aed50 arm:omap:am33xx: ... |
1472 1473 1474 |
omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo, ARRAY_SIZE(am335x_i2c_boardinfo)); } |
95d86ef9d ARM:omap3:am335x ... |
1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 |
static struct resource am335x_rtc_resources[] = { { .start = AM33XX_RTC_BASE, .end = AM33XX_RTC_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { /* timer irq */ .start = AM33XX_IRQ_RTC_TIMER, .end = AM33XX_IRQ_RTC_TIMER, .flags = IORESOURCE_IRQ, }, { /* alarm irq */ .start = AM33XX_IRQ_RTC_ALARM, .end = AM33XX_IRQ_RTC_ALARM, .flags = IORESOURCE_IRQ, }, }; static struct platform_device am335x_rtc_device = { .name = "omap_rtc", .id = -1, .num_resources = ARRAY_SIZE(am335x_rtc_resources), .resource = am335x_rtc_resources, }; static int am335x_rtc_init(void) { void __iomem *base; struct clk *clk; clk = clk_get(NULL, "rtc_fck"); if (IS_ERR(clk)) { pr_err("rtc : Failed to get RTC clock "); return -1; } if (clk_enable(clk)) { pr_err("rtc: Clock Enable Failed "); return -1; } base = ioremap(AM33XX_RTC_BASE, SZ_4K); if (WARN_ON(!base)) return -ENOMEM; /* Unlock the rtc's registers */ __raw_writel(0x83e70b13, base + 0x6c); __raw_writel(0x95a4f1e0, base + 0x70); /* * Enable the 32K OSc * TODO: Need a better way to handle this * Since we want the clock to be running before mmc init * we need to do it before the rtc probe happens */ __raw_writel(0x48, base + 0x54); iounmap(base); return platform_device_register(&am335x_rtc_device); } /* Enable clkout2 */ static struct pinmux_config clkout2_pin_mux[] = { {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT}, |
ca0024b85 arm:omap:am33xx: ... |
1543 |
{NULL, 0}, |
95d86ef9d ARM:omap3:am335x ... |
1544 1545 1546 1547 1548 1549 1550 |
}; static void __init clkout2_enable(void) { struct clk *ck_32; ck_32 = clk_get(NULL, "clkout2_ck"); |
ca0024b85 arm:omap:am33xx: ... |
1551 |
if (IS_ERR(ck_32)) { |
95d86ef9d ARM:omap3:am335x ... |
1552 1553 |
pr_err("Cannot clk_get ck_32 "); |
ca0024b85 arm:omap:am33xx: ... |
1554 1555 |
return; } |
95d86ef9d ARM:omap3:am335x ... |
1556 1557 1558 1559 1560 |
clk_enable(ck_32); setup_pin_mux(clkout2_pin_mux); } |
433039582 arm:omap:am33xx: ... |
1561 1562 |
static void __init am335x_evm_init(void) { |
385ed291a arm:omap:am33xx: ... |
1563 |
am33xx_mux_init(board_mux); |
433039582 arm:omap:am33xx: ... |
1564 |
omap_serial_init(); |
95d86ef9d ARM:omap3:am335x ... |
1565 1566 |
am335x_rtc_init(); clkout2_enable(); |
1ca8aed50 arm:omap:am33xx: ... |
1567 |
am335x_evm_i2c_init(); |
433039582 arm:omap:am33xx: ... |
1568 |
omap_sdrc_init(NULL, NULL); |
eb3dad1ce am335x: add musb ... |
1569 |
usb_musb_init(&musb_board_data); |
433039582 arm:omap:am33xx: ... |
1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 |
omap_board_config = am335x_evm_config; omap_board_config_size = ARRAY_SIZE(am335x_evm_config); } static void __init am335x_evm_map_io(void) { omap2_set_globals_am33xx(); omapam33xx_map_common_io(); } MACHINE_START(AM335XEVM, "am335xevm") /* Maintainer: Texas Instruments */ .atag_offset = 0x100, .map_io = am335x_evm_map_io, |
433039582 arm:omap:am33xx: ... |
1584 |
.init_irq = ti816x_init_irq, |
1ca8aed50 arm:omap:am33xx: ... |
1585 |
.init_early = am335x_init_early, |
433039582 arm:omap:am33xx: ... |
1586 1587 1588 |
.timer = &omap3_am33xx_timer, .init_machine = am335x_evm_init, MACHINE_END |
67feecc90 arm:omap:am33xx: ... |
1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 |
MACHINE_START(AM335XIAEVM, "am335xiaevm") /* Maintainer: Texas Instruments */ .atag_offset = 0x100, .map_io = am335x_evm_map_io, .init_irq = ti816x_init_irq, .init_early = am335x_init_early, .timer = &omap3_am33xx_timer, .init_machine = am335x_evm_init, MACHINE_END |