Commit f80ad58752f150aad0d9312bd2353c02b3de592b
Committed by
Afzal Mohammed
1 parent
e6f8996213
Exists in
master
ARM:omaP:am33xx; Move mmc CD & WP handling to GPIO
On AM335X, MMC CD & WP pins are handled directly by HSMMC ip. Currently IP seems to fail to detect changes properly. So move the CD & WP handling to GPIO module Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Showing 2 changed files with 29 additions and 101 deletions Side-by-side Diff
arch/arm/mach-omap2/board-am335xevm.c
... | ... | @@ -105,6 +105,9 @@ |
105 | 105 | #define am335x_tlk110_phy_init() do { } while (0); |
106 | 106 | #endif |
107 | 107 | |
108 | +/* Convert GPIO signal to GPIO pin number */ | |
109 | +#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) | |
110 | + | |
108 | 111 | static const struct display_panel disp_panel = { |
109 | 112 | WVGA, |
110 | 113 | 32, |
... | ... | @@ -189,8 +192,8 @@ |
189 | 192 | { |
190 | 193 | .mmc = 1, |
191 | 194 | .caps = MMC_CAP_4_BIT_DATA, |
192 | - .gpio_cd = -EINVAL,/* Dedicated pins for CD and WP */ | |
193 | - .gpio_wp = -EINVAL, | |
195 | + .gpio_cd = GPIO_TO_PIN(0, 6), | |
196 | + .gpio_wp = GPIO_TO_PIN(3, 18), | |
194 | 197 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */ |
195 | 198 | }, |
196 | 199 | { |
... | ... | @@ -516,8 +519,8 @@ |
516 | 519 | {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
517 | 520 | {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
518 | 521 | {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP}, |
519 | - {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, | |
520 | - {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT_PULLUP}, | |
522 | + {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | |
523 | + {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | |
521 | 524 | {NULL, 0}, |
522 | 525 | }; |
523 | 526 | |
... | ... | @@ -544,8 +547,8 @@ |
544 | 547 | {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, |
545 | 548 | {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, |
546 | 549 | {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP}, |
547 | - {"uart1_rxd.mmc1_sdwp", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP}, | |
548 | - {"mcasp0_fsx.mmc1_sdcd", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN}, | |
550 | + {"uart1_rxd.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | |
551 | + {"mcasp0_fsx.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | |
549 | 552 | {NULL, 0}, |
550 | 553 | }; |
551 | 554 | |
... | ... | @@ -561,8 +564,8 @@ |
561 | 564 | {"gpmc_ad12.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
562 | 565 | {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
563 | 566 | {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP}, |
564 | - {"spi0_cs0.mmc2_sdwp", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN}, | |
565 | - {"mcasp0_axr0.mmc2_sdcd", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP}, | |
567 | + {"spi0_cs0.mmc2_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | |
568 | + {"mcasp0_axr0.mmc2_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP}, | |
566 | 569 | {NULL, 0}, |
567 | 570 | }; |
568 | 571 | |
... | ... | @@ -627,9 +630,6 @@ |
627 | 630 | } |
628 | 631 | } |
629 | 632 | |
630 | -/* Convert GPIO signal to GPIO pin number */ | |
631 | -#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) | |
632 | - | |
633 | 633 | #define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7) |
634 | 634 | |
635 | 635 | /* pinmux for usb0 drvvbus */ |
... | ... | @@ -947,8 +947,8 @@ |
947 | 947 | |
948 | 948 | am335x_mmc[1].mmc = 2; |
949 | 949 | am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; |
950 | - am335x_mmc[1].gpio_cd = -EINVAL; | |
951 | - am335x_mmc[1].gpio_wp = -EINVAL; | |
950 | + am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15); | |
951 | + am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 14); | |
952 | 952 | am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ |
953 | 953 | |
954 | 954 | /* mmc will be initialized when mmc0_init is called */ |
... | ... | @@ -961,8 +961,8 @@ |
961 | 961 | |
962 | 962 | am335x_mmc[1].mmc = 3; |
963 | 963 | am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA; |
964 | - am335x_mmc[1].gpio_cd = -EINVAL; | |
965 | - am335x_mmc[1].gpio_wp = -EINVAL; | |
964 | + am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 16); | |
965 | + am335x_mmc[1].gpio_wp = GPIO_TO_PIN(0, 5); | |
966 | 966 | am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */ |
967 | 967 | |
968 | 968 | /* mmc will be initialized when mmc0_init is called */ |
drivers/mmc/host/omap_hsmmc.c
... | ... | @@ -211,63 +211,25 @@ |
211 | 211 | static int omap_hsmmc_card_detect(struct device *dev, int slot) |
212 | 212 | { |
213 | 213 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
214 | - struct omap_hsmmc_host *host = | |
215 | - platform_get_drvdata(to_platform_device(dev)); | |
216 | 214 | |
217 | - u32 pstate; | |
218 | - u32 enabled; | |
219 | - | |
220 | - if (mmc->version != MMC_CTRL_VERSION_2) | |
221 | - /* NOTE: assumes card detect signal is active-low */ | |
222 | - return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
223 | - else { | |
224 | - pstate = 0; | |
225 | - enabled = 0; | |
226 | - | |
227 | - enabled = host->mmc->enabled; | |
228 | - if (!enabled) | |
229 | - mmc_host_enable(host->mmc); | |
230 | - | |
231 | - pstate = OMAP_HSMMC_READ(host->base, PSTATE); | |
232 | - | |
233 | - if (!enabled) | |
234 | - mmc_host_disable(host->mmc); | |
235 | - pstate = pstate & PSTATE_CINS_MASK; | |
236 | - pstate = pstate >> PSTATE_CINS_SHIFT; | |
237 | - return pstate; | |
238 | - } | |
215 | + /* NOTE: assumes card detect signal is active-low */ | |
216 | + return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
239 | 217 | } |
240 | 218 | |
241 | 219 | static int omap_hsmmc_get_wp(struct device *dev, int slot) |
242 | 220 | { |
243 | 221 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
244 | - struct omap_hsmmc_host *host = | |
245 | - platform_get_drvdata(to_platform_device(dev)); | |
246 | 222 | |
247 | - u32 pstate; | |
248 | - | |
249 | - if (mmc->version != MMC_CTRL_VERSION_2) | |
250 | - /* NOTE: assumes write protect signal is active-high */ | |
251 | - return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
252 | - else { | |
253 | - pstate = 0; | |
254 | - pstate = OMAP_HSMMC_READ(host->base, PSTATE); | |
255 | - pstate &= PSTATE_WP_MASK; | |
256 | - return !(pstate >> PSTATE_WP_SHIFT); | |
257 | - } | |
223 | + /* NOTE: assumes write protect signal is active-high */ | |
224 | + return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
258 | 225 | } |
259 | 226 | |
260 | 227 | static int omap_hsmmc_get_cover_state(struct device *dev, int slot) |
261 | 228 | { |
262 | 229 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
263 | - struct omap_hsmmc_host *host = | |
264 | - platform_get_drvdata(to_platform_device(dev)); | |
265 | 230 | |
266 | - if (mmc->version != MMC_CTRL_VERSION_2) | |
267 | - /* NOTE: assumes card detect signal is active-low */ | |
268 | - return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
269 | - else | |
270 | - return OMAP_HSMMC_READ(host->base, PSTATE) >> PSTATE_CINS_SHIFT; | |
231 | + /* NOTE: assumes card detect signal is active-low */ | |
232 | + return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
271 | 233 | } |
272 | 234 | |
273 | 235 | #ifdef CONFIG_PM |
274 | 236 | |
275 | 237 | |
276 | 238 | |
... | ... | @@ -275,28 +237,18 @@ |
275 | 237 | static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) |
276 | 238 | { |
277 | 239 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
278 | - struct omap_hsmmc_host *host = | |
279 | - platform_get_drvdata(to_platform_device(dev)); | |
280 | 240 | |
281 | - if (mmc->version != MMC_CTRL_VERSION_2) | |
282 | - disable_irq(mmc->slots[0].card_detect_irq); | |
283 | - else | |
284 | - OMAP_HSMMC_WRITE(host->base, IE, | |
285 | - OMAP_HSMMC_READ(host->base, IE) & ~IE_CINS); | |
241 | + disable_irq(mmc->slots[0].card_detect_irq); | |
242 | + | |
286 | 243 | return 0; |
287 | 244 | } |
288 | 245 | |
289 | 246 | static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) |
290 | 247 | { |
291 | 248 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
292 | - struct omap_hsmmc_host *host = | |
293 | - platform_get_drvdata(to_platform_device(dev)); | |
294 | 249 | |
295 | - if (mmc->version != MMC_CTRL_VERSION_2) | |
296 | - enable_irq(mmc->slots[0].card_detect_irq); | |
297 | - else | |
298 | - OMAP_HSMMC_WRITE(host->base, IE, | |
299 | - OMAP_HSMMC_READ(host->base, IE) | IE_CINS); | |
250 | + enable_irq(mmc->slots[0].card_detect_irq); | |
251 | + | |
300 | 252 | return 0; |
301 | 253 | } |
302 | 254 | |
... | ... | @@ -452,7 +404,6 @@ |
452 | 404 | struct regulator *reg; |
453 | 405 | int ret = 0; |
454 | 406 | int ocr_value = 0; |
455 | - struct omap_mmc_platform_data *pdata = host->pdata; | |
456 | 407 | |
457 | 408 | switch (host->id) { |
458 | 409 | case OMAP_MMC1_DEVID: |
... | ... | @@ -501,10 +452,6 @@ |
501 | 452 | } |
502 | 453 | } |
503 | 454 | |
504 | - if (pdata->version == MMC_CTRL_VERSION_2) | |
505 | - mmc_slot(host).ocr_mask = | |
506 | - mmc_regulator_get_ocrmask(reg); | |
507 | - | |
508 | 455 | /* Allow an aux regulator */ |
509 | 456 | reg = regulator_get(host->dev, "vmmc_aux"); |
510 | 457 | host->vcc_aux = IS_ERR(reg) ? NULL : reg; |
... | ... | @@ -603,14 +550,6 @@ |
603 | 550 | } else |
604 | 551 | pdata->slots[0].gpio_wp = -EINVAL; |
605 | 552 | |
606 | - if (pdata->version == MMC_CTRL_VERSION_2) { | |
607 | - pdata->suspend = omap_hsmmc_suspend_cdirq; | |
608 | - pdata->resume = omap_hsmmc_resume_cdirq; | |
609 | - pdata->slots[0].get_cover_state = omap_hsmmc_get_cover_state; | |
610 | - pdata->slots[0].get_ro = omap_hsmmc_get_wp; | |
611 | - pdata->slots[0].card_detect = omap_hsmmc_card_detect; | |
612 | - } | |
613 | - | |
614 | 553 | return 0; |
615 | 554 | |
616 | 555 | err_free_wp: |
617 | 556 | |
... | ... | @@ -671,17 +610,11 @@ |
671 | 610 | |
672 | 611 | static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) |
673 | 612 | { |
674 | - struct omap_mmc_platform_data *pdata = host->pdata; | |
675 | 613 | |
676 | - if (pdata->version == MMC_CTRL_VERSION_2) { | |
677 | - OMAP_HSMMC_WRITE(host->base, ISE, 0xC0); | |
678 | - OMAP_HSMMC_WRITE(host->base, IE, 0xC0); | |
679 | - OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
680 | - } else { | |
681 | - OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
682 | - OMAP_HSMMC_WRITE(host->base, IE, 0); | |
683 | - OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
684 | - } | |
614 | + OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
615 | + OMAP_HSMMC_WRITE(host->base, IE, 0); | |
616 | + OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
617 | + | |
685 | 618 | } |
686 | 619 | |
687 | 620 | /* Calculate divisor for the given clock frequency */ |
... | ... | @@ -1183,11 +1116,6 @@ |
1183 | 1116 | { |
1184 | 1117 | struct mmc_data *data; |
1185 | 1118 | int end_cmd = 0, end_trans = 0; |
1186 | - | |
1187 | - /* Schedule card detect here ONLY if irq for CD isn't registerted*/ | |
1188 | - if ((host->pdata->version == MMC_CTRL_VERSION_2) && | |
1189 | - ((status & CINS) || (status & 0x80))) | |
1190 | - omap_hsmmc_cd_handler(irq, host); | |
1191 | 1119 | |
1192 | 1120 | if (!host->req_in_progress) { |
1193 | 1121 | do { |