Eric Lee / linux-smarc-t335x-v3.2

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Commit 0095d58b4a91b9fb57aeb781909355b232517c64

Authored by Joe Perches
Committed by Paul Mundt
1 parent eb9c7f4198
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

sh: include/asm-sh/: Spelling fixes. 

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 3 changed files with 17 additions and 17 deletions Inline Diff

include/asm-sh/hd64461.h
Diff comments   View file @ 0095d58
1 #ifndef __ASM_SH_HD64461 1 #ifndef __ASM_SH_HD64461
2 #define __ASM_SH_HD64461 2 #define __ASM_SH_HD64461
3 /* 3 /*
4 * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com> 4 * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
5 * Copyright (C) 2004 Paul Mundt 5 * Copyright (C) 2004 Paul Mundt
6 * Copyright (C) 2000 YAEGASHI Takeshi 6 * Copyright (C) 2000 YAEGASHI Takeshi
7 * 7 *
8 * Hitachi HD64461 companion chip support 8 * Hitachi HD64461 companion chip support
9 * (please note manual reference 0x10000000 = 0xb0000000) 9 * (please note manual reference 0x10000000 = 0xb0000000)
10 */ 10 */
11 11
12 /* Constants for PCMCIA mappings */ 12 /* Constants for PCMCIA mappings */
13 #define HD64461_PCC_WINDOW 0x01000000 13 #define HD64461_PCC_WINDOW 0x01000000
14 14
15 /* Area 6 - Slot 0 - memory and/or IO card */ 15 /* Area 6 - Slot 0 - memory and/or IO card */
16 #define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 16 #define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000)
17 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 17 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
18 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 18 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
19 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 19 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
20 20
21 /* Area 5 - Slot 1 - memory card only */ 21 /* Area 5 - Slot 1 - memory card only */
22 #define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 22 #define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000)
23 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 23 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
24 #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 24 #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
25 25
26 /* Standby Control Register for HD64461 */ 26 /* Standby Control Register for HD64461 */
27 #define HD64461_STBCR CONFIG_HD64461_IOBASE 27 #define HD64461_STBCR CONFIG_HD64461_IOBASE
28 #define HD64461_STBCR_CKIO_STBY 0x2000 28 #define HD64461_STBCR_CKIO_STBY 0x2000
29 #define HD64461_STBCR_SAFECKE_IST 0x1000 29 #define HD64461_STBCR_SAFECKE_IST 0x1000
30 #define HD64461_STBCR_SLCKE_IST 0x0800 30 #define HD64461_STBCR_SLCKE_IST 0x0800
31 #define HD64461_STBCR_SAFECKE_OST 0x0400 31 #define HD64461_STBCR_SAFECKE_OST 0x0400
32 #define HD64461_STBCR_SLCKE_OST 0x0200 32 #define HD64461_STBCR_SLCKE_OST 0x0200
33 #define HD64461_STBCR_SMIAST 0x0100 33 #define HD64461_STBCR_SMIAST 0x0100
34 #define HD64461_STBCR_SLCDST 0x0080 34 #define HD64461_STBCR_SLCDST 0x0080
35 #define HD64461_STBCR_SPC0ST 0x0040 35 #define HD64461_STBCR_SPC0ST 0x0040
36 #define HD64461_STBCR_SPC1ST 0x0020 36 #define HD64461_STBCR_SPC1ST 0x0020
37 #define HD64461_STBCR_SAFEST 0x0010 37 #define HD64461_STBCR_SAFEST 0x0010
38 #define HD64461_STBCR_STM0ST 0x0008 38 #define HD64461_STBCR_STM0ST 0x0008
39 #define HD64461_STBCR_STM1ST 0x0004 39 #define HD64461_STBCR_STM1ST 0x0004
40 #define HD64461_STBCR_SIRST 0x0002 40 #define HD64461_STBCR_SIRST 0x0002
41 #define HD64461_STBCR_SURTST 0x0001 41 #define HD64461_STBCR_SURTST 0x0001
42 42
43 /* System Configuration Register */ 43 /* System Configuration Register */
44 #define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 44 #define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02)
45 45
46 /* CPU Data Bus Control Register */ 46 /* CPU Data Bus Control Register */
47 #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 47 #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04)
48 48
49 /* Base Adress Register */ 49 /* Base Address Register */
50 #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 50 #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000)
51 51
52 /* Line increment adress */ 52 /* Line increment address */
53 #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 53 #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002)
54 54
55 /* Controls LCD controller */ 55 /* Controls LCD controller */
56 #define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 56 #define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004)
57 57
58 /* LCCDR control bits */ 58 /* LCCDR control bits */
59 #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 59 #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
60 #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */ 60 #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */
61 #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */ 61 #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */
62 #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */ 62 #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */
63 #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */ 63 #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */
64 #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 64 #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
65 65
66 /* Controls LCD (1) */ 66 /* Controls LCD (1) */
67 #define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 67 #define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010)
68 #define HD64461_LDR1_DON 0x01 /* Display On */ 68 #define HD64461_LDR1_DON 0x01 /* Display On */
69 #define HD64461_LDR1_DINV 0x80 /* Display Invert */ 69 #define HD64461_LDR1_DINV 0x80 /* Display Invert */
70 70
71 /* Controls LCD (2) */ 71 /* Controls LCD (2) */
72 #define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 72 #define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012)
73 #define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ 73 #define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */
74 #define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ 74 #define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */
75 #define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ 75 #define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */
76 #define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ 76 #define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */
77 #define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ 77 #define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */
78 78
79 /* Controls LCD (3) */ 79 /* Controls LCD (3) */
80 #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 80 #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e)
81 81
82 /* Palette Registers */ 82 /* Palette Registers */
83 #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Adress Register */ 83 #define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */
84 #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ 84 #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */
85 #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Adress Register */ 85 #define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */
86 #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ 86 #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */
87 87
88 #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ 88 #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */
89 #define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ 89 #define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */
90 #define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ 90 #define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */
91 91
92 #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 92 #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
93 #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 93 #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
94 #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */ 94 #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
95 #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */ 95 #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
96 #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */ 96 #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
97 #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 97 #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98 98
99 /* Line Drawing Registers */ 99 /* Line Drawing Registers */
100 #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Adress Register (H) */ 100 #define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */
101 #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Adress Register (L) */ 101 #define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */
102 #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ 102 #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */
103 #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ 103 #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */
104 #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ 104 #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */
105 #define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ 105 #define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */
106 #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ 106 #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */
107 107
108 /* BitBLT Registers */ 108 /* BitBLT Registers */
109 #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Adress Register (H) */ 109 #define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */
110 #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Adress Register (L) */ 110 #define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */
111 #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Adress Register (H) */ 111 #define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */
112 #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Adress Register (L) */ 112 #define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */
113 #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ 113 #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */
114 #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ 114 #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */
115 #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Adress Register (H) */ 115 #define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */
116 #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Adress Register (L) */ 116 #define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */
117 #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Adress Register (H) */ 117 #define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */
118 #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Adress Register (L) */ 118 #define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */
119 #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ 119 #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */
120 #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ 120 #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */
121 121
122 /* PC Card Controller Registers */ 122 /* PC Card Controller Registers */
123 /* Maps to Physical Area 6 */ 123 /* Maps to Physical Area 6 */
124 #define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ 124 #define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */
125 #define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ 125 #define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */
126 #define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ 126 #define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */
127 #define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ 127 #define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */
128 #define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ 128 #define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */
129 /* Maps to Physical Area 5 */ 129 /* Maps to Physical Area 5 */
130 #define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ 130 #define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */
131 #define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ 131 #define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */
132 #define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ 132 #define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */
133 #define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ 133 #define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */
134 #define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ 134 #define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */
135 135
136 /* PCC Interface Status Register */ 136 /* PCC Interface Status Register */
137 #define HD64461_PCCISR_READY 0x80 /* card ready */ 137 #define HD64461_PCCISR_READY 0x80 /* card ready */
138 #define HD64461_PCCISR_MWP 0x40 /* card write-protected */ 138 #define HD64461_PCCISR_MWP 0x40 /* card write-protected */
139 #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ 139 #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
140 #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ 140 #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
141 #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ 141 #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
142 #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ 142 #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
143 #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ 143 #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
144 #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ 144 #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
145 145
146 #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ 146 #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
147 #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ 147 #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
148 #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ 148 #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
149 #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ 149 #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
150 #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ 150 #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
151 #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ 151 #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
152 152
153 /* PCC General Control Register */ 153 /* PCC General Control Register */
154 #define HD64461_PCCGCR_DRVE 0x80 /* output drive */ 154 #define HD64461_PCCGCR_DRVE 0x80 /* output drive */
155 #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ 155 #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
156 #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ 156 #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
157 #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ 157 #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
158 #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ 158 #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
159 #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ 159 #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
160 #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ 160 #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
161 #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ 161 #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
162 162
163 /* PCC Card Status Change Register */ 163 /* PCC Card Status Change Register */
164 #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ 164 #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
165 #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ 165 #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
166 #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ 166 #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
167 #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ 167 #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
168 #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ 168 #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
169 #define HD64461_PCCCSCR_RC 0x04 /* READY change */ 169 #define HD64461_PCCCSCR_RC 0x04 /* READY change */
170 #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ 170 #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
171 #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ 171 #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
172 172
173 /* PCC Card Status Change Interrupt Enable Register */ 173 /* PCC Card Status Change Interrupt Enable Register */
174 #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ 174 #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
175 #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ 175 #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
176 #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ 176 #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
177 #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ 177 #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
178 #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ 178 #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
179 #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ 179 #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
180 180
181 #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ 181 #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
182 #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ 182 #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
183 #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ 183 #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
184 #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ 184 #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
185 #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ 185 #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
186 186
187 /* PCC Software Control Register */ 187 /* PCC Software Control Register */
188 #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ 188 #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
189 #define HD64461_PCCSCR_SWP 0x01 /* write protect */ 189 #define HD64461_PCCSCR_SWP 0x01 /* write protect */
190 190
191 /* PCC0 Output Pins Control Register */ 191 /* PCC0 Output Pins Control Register */
192 #define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 192 #define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a)
193 193
194 /* PCC1 Output Pins Control Register */ 194 /* PCC1 Output Pins Control Register */
195 #define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 195 #define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c)
196 196
197 /* PC Card General Control Register */ 197 /* PC Card General Control Register */
198 #define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 198 #define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e)
199 199
200 /* Port Control Registers */ 200 /* Port Control Registers */
201 #define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ 201 #define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */
202 #define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ 202 #define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */
203 #define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ 203 #define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */
204 #define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ 204 #define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */
205 205
206 /* Port Control Data Registers */ 206 /* Port Control Data Registers */
207 #define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ 207 #define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */
208 #define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ 208 #define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */
209 #define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ 209 #define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */
210 #define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ 210 #define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */
211 211
212 /* Interrupt Control Registers */ 212 /* Interrupt Control Registers */
213 #define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ 213 #define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */
214 #define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ 214 #define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */
215 #define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ 215 #define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */
216 #define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ 216 #define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */
217 217
218 /* Interrupt Status Registers */ 218 /* Interrupt Status Registers */
219 #define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ 219 #define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */
220 #define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ 220 #define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */
221 #define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ 221 #define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */
222 #define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ 222 #define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */
223 223
224 /* Interrupt Request Register & Interrupt Mask Register */ 224 /* Interrupt Request Register & Interrupt Mask Register */
225 #define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 225 #define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000)
226 #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 226 #define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002)
227 227
228 #define HD64461_IRQBASE OFFCHIP_IRQ_BASE 228 #define HD64461_IRQBASE OFFCHIP_IRQ_BASE
229 #define OFFCHIP_IRQ_BASE 64 229 #define OFFCHIP_IRQ_BASE 64
230 #define HD64461_IRQ_NUM 16 230 #define HD64461_IRQ_NUM 16
231 231
232 #define HD64461_IRQ_UART (HD64461_IRQBASE+5) 232 #define HD64461_IRQ_UART (HD64461_IRQBASE+5)
233 #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) 233 #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
234 #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) 234 #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
235 #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) 235 #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
236 #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) 236 #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
237 #define HD64461_IRQ_AFE (HD64461_IRQBASE+12) 237 #define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
238 #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) 238 #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
239 #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) 239 #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
240 240
241 #define __IO_PREFIX hd64461 241 #define __IO_PREFIX hd64461
242 #include <asm/io_generic.h> 242 #include <asm/io_generic.h>
243 243
244 /* arch/sh/cchips/hd6446x/hd64461/setup.c */ 244 /* arch/sh/cchips/hd6446x/hd64461/setup.c */
245 int hd64461_irq_demux(int irq); 245 int hd64461_irq_demux(int irq);
246 void hd64461_register_irq_demux(int irq, 246 void hd64461_register_irq_demux(int irq,
247 int (*demux) (int irq, void *dev), void *dev); 247 int (*demux) (int irq, void *dev), void *dev);
248 void hd64461_unregister_irq_demux(int irq); 248 void hd64461_unregister_irq_demux(int irq);
249 249
250 #endif 250 #endif
251 251
include/asm-sh/microdev.h
Diff comments   View file @ 0095d58
1 /* 1 /*
2 * linux/include/asm-sh/microdev.h 2 * linux/include/asm-sh/microdev.h
3 * 3 *
4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) 4 * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
5 * 5 *
6 * Definitions for the SuperH SH4-202 MicroDev board. 6 * Definitions for the SuperH SH4-202 MicroDev board.
7 * 7 *
8 * May be copied or modified under the terms of the GNU General Public 8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information. 9 * License. See linux/COPYING for more information.
10 */ 10 */
11 #ifndef __ASM_SH_MICRODEV_H 11 #ifndef __ASM_SH_MICRODEV_H
12 #define __ASM_SH_MICRODEV_H 12 #define __ASM_SH_MICRODEV_H
13 13
14 extern void init_microdev_irq(void); 14 extern void init_microdev_irq(void);
15 extern void microdev_print_fpga_intc_status(void); 15 extern void microdev_print_fpga_intc_status(void);
16 16
17 /* 17 /*
18 * The following are useful macros for manipulating the interrupt 18 * The following are useful macros for manipulating the interrupt
19 * controller (INTC) on the CPU-board FPGA. should be noted that there 19 * controller (INTC) on the CPU-board FPGA. should be noted that there
20 * is an INTC on the FPGA, and a seperate INTC on the SH4-202 core - 20 * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
21 * these are two different things, both of which need to be prorammed to 21 * these are two different things, both of which need to be prorammed to
22 * correctly route - unfortunately, they have the same name and 22 * correctly route - unfortunately, they have the same name and
23 * abbreviations! 23 * abbreviations!
24 */ 24 */
25 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ 25 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
26 #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ 26 #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
27 #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ 27 #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
28 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interupt mask to enable/disable INTC in CPU-board FPGA */ 28 #define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
29 #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ 29 #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
30 #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ 30 #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
31 #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ 31 #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
32 #define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */ 32 #define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
33 #define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */ 33 #define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
34 34
35 35
36 /* 36 /*
37 * The following are the IRQ numbers for the Linux Kernel for external 37 * The following are the IRQ numbers for the Linux Kernel for external
38 * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'. 38 * interrupts. i.e. the numbers seen by 'cat /proc/interrupt'.
39 */ 39 */
40 #define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ 40 #define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
41 #define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */ 41 #define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */
42 #define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */ 42 #define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */
43 #define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ 43 #define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
44 #define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */ 44 #define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */
45 #define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ 45 #define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
46 #define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */ 46 #define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */
47 #define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */ 47 #define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */
48 48
49 /* 49 /*
50 * The following are the IRQ numbers for the INTC on the FPGA for 50 * The following are the IRQ numbers for the INTC on the FPGA for
51 * external interrupts. i.e. the bits in the INTC registers in the 51 * external interrupts. i.e. the bits in the INTC registers in the
52 * FPGA. 52 * FPGA.
53 */ 53 */
54 #define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ 54 #define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
55 #define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */ 55 #define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */
56 #define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ 56 #define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
57 #define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ 57 #define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
58 #define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */ 58 #define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */
59 #define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */ 59 #define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */
60 #define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */ 60 #define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */
61 #define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */ 61 #define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */
62 62
63 #define MICRODEV_IRQ_PCI_INTA 8 63 #define MICRODEV_IRQ_PCI_INTA 8
64 #define MICRODEV_IRQ_PCI_INTB 9 64 #define MICRODEV_IRQ_PCI_INTB 9
65 #define MICRODEV_IRQ_PCI_INTC 10 65 #define MICRODEV_IRQ_PCI_INTC 10
66 #define MICRODEV_IRQ_PCI_INTD 11 66 #define MICRODEV_IRQ_PCI_INTD 11
67 67
68 #define __IO_PREFIX microdev 68 #define __IO_PREFIX microdev
69 #include <asm/io_generic.h> 69 #include <asm/io_generic.h>
70 70
71 #if defined(CONFIG_PCI) 71 #if defined(CONFIG_PCI)
72 unsigned char microdev_pci_inb(unsigned long port); 72 unsigned char microdev_pci_inb(unsigned long port);
73 unsigned short microdev_pci_inw(unsigned long port); 73 unsigned short microdev_pci_inw(unsigned long port);
74 unsigned long microdev_pci_inl(unsigned long port); 74 unsigned long microdev_pci_inl(unsigned long port);
75 void microdev_pci_outb(unsigned char data, unsigned long port); 75 void microdev_pci_outb(unsigned char data, unsigned long port);
76 void microdev_pci_outw(unsigned short data, unsigned long port); 76 void microdev_pci_outw(unsigned short data, unsigned long port);
77 void microdev_pci_outl(unsigned long data, unsigned long port); 77 void microdev_pci_outl(unsigned long data, unsigned long port);
78 #endif 78 #endif
79 79
80 #endif /* __ASM_SH_MICRODEV_H */ 80 #endif /* __ASM_SH_MICRODEV_H */
81 81
include/asm-sh/voyagergx.h
Diff comments   View file @ 0095d58
1 /* -------------------------------------------------------------------- */ 1 /* -------------------------------------------------------------------- */
2 /* voyagergx.h */ 2 /* voyagergx.h */
3 /* -------------------------------------------------------------------- */ 3 /* -------------------------------------------------------------------- */
4 /* This program is free software; you can redistribute it and/or modify 4 /* This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by 5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or 6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version. 7 (at your option) any later version.
8 8
9 This program is distributed in the hope that it will be useful, 9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of 10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details. 12 GNU General Public License for more details.
13 13
14 You should have received a copy of the GNU General Public License 14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 17
18 Copyright 2003 (c) Lineo uSolutions,Inc. 18 Copyright 2003 (c) Lineo uSolutions,Inc.
19 */ 19 */
20 /* -------------------------------------------------------------------- */ 20 /* -------------------------------------------------------------------- */
21 21
22 #ifndef _VOYAGER_GX_REG_H 22 #ifndef _VOYAGER_GX_REG_H
23 #define _VOYAGER_GX_REG_H 23 #define _VOYAGER_GX_REG_H
24 24
25 #define VOYAGER_BASE 0xb3e00000 25 #define VOYAGER_BASE 0xb3e00000
26 #define VOYAGER_USBH_BASE (0x40000 + VOYAGER_BASE) 26 #define VOYAGER_USBH_BASE (0x40000 + VOYAGER_BASE)
27 #define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE) 27 #define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE)
28 #define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE) 28 #define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE)
29 29
30 #define VOYAGER_IRQ_NUM 26 30 #define VOYAGER_IRQ_NUM 26
31 #define VOYAGER_IRQ_BASE 200 31 #define VOYAGER_IRQ_BASE 200
32 32
33 #define IRQ_SM501_UP (VOYAGER_IRQ_BASE + 0) 33 #define IRQ_SM501_UP (VOYAGER_IRQ_BASE + 0)
34 #define IRQ_SM501_G54 (VOYAGER_IRQ_BASE + 1) 34 #define IRQ_SM501_G54 (VOYAGER_IRQ_BASE + 1)
35 #define IRQ_SM501_G53 (VOYAGER_IRQ_BASE + 2) 35 #define IRQ_SM501_G53 (VOYAGER_IRQ_BASE + 2)
36 #define IRQ_SM501_G52 (VOYAGER_IRQ_BASE + 3) 36 #define IRQ_SM501_G52 (VOYAGER_IRQ_BASE + 3)
37 #define IRQ_SM501_G51 (VOYAGER_IRQ_BASE + 4) 37 #define IRQ_SM501_G51 (VOYAGER_IRQ_BASE + 4)
38 #define IRQ_SM501_G50 (VOYAGER_IRQ_BASE + 5) 38 #define IRQ_SM501_G50 (VOYAGER_IRQ_BASE + 5)
39 #define IRQ_SM501_G49 (VOYAGER_IRQ_BASE + 6) 39 #define IRQ_SM501_G49 (VOYAGER_IRQ_BASE + 6)
40 #define IRQ_SM501_G48 (VOYAGER_IRQ_BASE + 7) 40 #define IRQ_SM501_G48 (VOYAGER_IRQ_BASE + 7)
41 #define IRQ_SM501_I2C (VOYAGER_IRQ_BASE + 8) 41 #define IRQ_SM501_I2C (VOYAGER_IRQ_BASE + 8)
42 #define IRQ_SM501_PW (VOYAGER_IRQ_BASE + 9) 42 #define IRQ_SM501_PW (VOYAGER_IRQ_BASE + 9)
43 #define IRQ_SM501_DMA (VOYAGER_IRQ_BASE + 10) 43 #define IRQ_SM501_DMA (VOYAGER_IRQ_BASE + 10)
44 #define IRQ_SM501_PCI (VOYAGER_IRQ_BASE + 11) 44 #define IRQ_SM501_PCI (VOYAGER_IRQ_BASE + 11)
45 #define IRQ_SM501_I2S (VOYAGER_IRQ_BASE + 12) 45 #define IRQ_SM501_I2S (VOYAGER_IRQ_BASE + 12)
46 #define IRQ_SM501_AC (VOYAGER_IRQ_BASE + 13) 46 #define IRQ_SM501_AC (VOYAGER_IRQ_BASE + 13)
47 #define IRQ_SM501_US (VOYAGER_IRQ_BASE + 14) 47 #define IRQ_SM501_US (VOYAGER_IRQ_BASE + 14)
48 #define IRQ_SM501_U1 (VOYAGER_IRQ_BASE + 15) 48 #define IRQ_SM501_U1 (VOYAGER_IRQ_BASE + 15)
49 #define IRQ_SM501_U0 (VOYAGER_IRQ_BASE + 16) 49 #define IRQ_SM501_U0 (VOYAGER_IRQ_BASE + 16)
50 #define IRQ_SM501_CV (VOYAGER_IRQ_BASE + 17) 50 #define IRQ_SM501_CV (VOYAGER_IRQ_BASE + 17)
51 #define IRQ_SM501_MC (VOYAGER_IRQ_BASE + 18) 51 #define IRQ_SM501_MC (VOYAGER_IRQ_BASE + 18)
52 #define IRQ_SM501_S1 (VOYAGER_IRQ_BASE + 19) 52 #define IRQ_SM501_S1 (VOYAGER_IRQ_BASE + 19)
53 #define IRQ_SM501_S0 (VOYAGER_IRQ_BASE + 20) 53 #define IRQ_SM501_S0 (VOYAGER_IRQ_BASE + 20)
54 #define IRQ_SM501_UH (VOYAGER_IRQ_BASE + 21) 54 #define IRQ_SM501_UH (VOYAGER_IRQ_BASE + 21)
55 #define IRQ_SM501_2D (VOYAGER_IRQ_BASE + 22) 55 #define IRQ_SM501_2D (VOYAGER_IRQ_BASE + 22)
56 #define IRQ_SM501_ZD (VOYAGER_IRQ_BASE + 23) 56 #define IRQ_SM501_ZD (VOYAGER_IRQ_BASE + 23)
57 #define IRQ_SM501_PV (VOYAGER_IRQ_BASE + 24) 57 #define IRQ_SM501_PV (VOYAGER_IRQ_BASE + 24)
58 #define IRQ_SM501_CI (VOYAGER_IRQ_BASE + 25) 58 #define IRQ_SM501_CI (VOYAGER_IRQ_BASE + 25)
59 59
60 /* ----- MISC controle register ------------------------------ */ 60 /* ----- MISC controle register ------------------------------ */
61 #define MISC_CTRL (0x000004 + VOYAGER_BASE) 61 #define MISC_CTRL (0x000004 + VOYAGER_BASE)
62 #define MISC_CTRL_USBCLK_48 (3 << 28) 62 #define MISC_CTRL_USBCLK_48 (3 << 28)
63 #define MISC_CTRL_USBCLK_96 (2 << 28) 63 #define MISC_CTRL_USBCLK_96 (2 << 28)
64 #define MISC_CTRL_USBCLK_CRYSTAL (1 << 28) 64 #define MISC_CTRL_USBCLK_CRYSTAL (1 << 28)
65 65
66 /* ----- GPIO[31:0] register --------------------------------- */ 66 /* ----- GPIO[31:0] register --------------------------------- */
67 #define GPIO_MUX_LOW (0x000008 + VOYAGER_BASE) 67 #define GPIO_MUX_LOW (0x000008 + VOYAGER_BASE)
68 #define GPIO_MUX_LOW_AC97 0x1F000000 68 #define GPIO_MUX_LOW_AC97 0x1F000000
69 #define GPIO_MUX_LOW_8051 0x0000ffff 69 #define GPIO_MUX_LOW_8051 0x0000ffff
70 #define GPIO_MUX_LOW_PWM (1 << 29) 70 #define GPIO_MUX_LOW_PWM (1 << 29)
71 71
72 /* ----- GPIO[63:32] register --------------------------------- */ 72 /* ----- GPIO[63:32] register --------------------------------- */
73 #define GPIO_MUX_HIGH (0x00000C + VOYAGER_BASE) 73 #define GPIO_MUX_HIGH (0x00000C + VOYAGER_BASE)
74 74
75 /* ----- DRAM controle register ------------------------------- */ 75 /* ----- DRAM controle register ------------------------------- */
76 #define DRAM_CTRL (0x000010 + VOYAGER_BASE) 76 #define DRAM_CTRL (0x000010 + VOYAGER_BASE)
77 #define DRAM_CTRL_EMBEDDED (1 << 31) 77 #define DRAM_CTRL_EMBEDDED (1 << 31)
78 #define DRAM_CTRL_CPU_BURST_1 (0 << 28) 78 #define DRAM_CTRL_CPU_BURST_1 (0 << 28)
79 #define DRAM_CTRL_CPU_BURST_2 (1 << 28) 79 #define DRAM_CTRL_CPU_BURST_2 (1 << 28)
80 #define DRAM_CTRL_CPU_BURST_4 (2 << 28) 80 #define DRAM_CTRL_CPU_BURST_4 (2 << 28)
81 #define DRAM_CTRL_CPU_BURST_8 (3 << 28) 81 #define DRAM_CTRL_CPU_BURST_8 (3 << 28)
82 #define DRAM_CTRL_CPU_CAS_LATENCY (1 << 27) 82 #define DRAM_CTRL_CPU_CAS_LATENCY (1 << 27)
83 #define DRAM_CTRL_CPU_SIZE_2 (0 << 24) 83 #define DRAM_CTRL_CPU_SIZE_2 (0 << 24)
84 #define DRAM_CTRL_CPU_SIZE_4 (1 << 24) 84 #define DRAM_CTRL_CPU_SIZE_4 (1 << 24)
85 #define DRAM_CTRL_CPU_SIZE_64 (4 << 24) 85 #define DRAM_CTRL_CPU_SIZE_64 (4 << 24)
86 #define DRAM_CTRL_CPU_SIZE_32 (5 << 24) 86 #define DRAM_CTRL_CPU_SIZE_32 (5 << 24)
87 #define DRAM_CTRL_CPU_SIZE_16 (6 << 24) 87 #define DRAM_CTRL_CPU_SIZE_16 (6 << 24)
88 #define DRAM_CTRL_CPU_SIZE_8 (7 << 24) 88 #define DRAM_CTRL_CPU_SIZE_8 (7 << 24)
89 #define DRAM_CTRL_CPU_COLUMN_SIZE_1024 (0 << 22) 89 #define DRAM_CTRL_CPU_COLUMN_SIZE_1024 (0 << 22)
90 #define DRAM_CTRL_CPU_COLUMN_SIZE_512 (2 << 22) 90 #define DRAM_CTRL_CPU_COLUMN_SIZE_512 (2 << 22)
91 #define DRAM_CTRL_CPU_COLUMN_SIZE_256 (3 << 22) 91 #define DRAM_CTRL_CPU_COLUMN_SIZE_256 (3 << 22)
92 #define DRAM_CTRL_CPU_ACTIVE_PRECHARGE (1 << 21) 92 #define DRAM_CTRL_CPU_ACTIVE_PRECHARGE (1 << 21)
93 #define DRAM_CTRL_CPU_RESET (1 << 20) 93 #define DRAM_CTRL_CPU_RESET (1 << 20)
94 #define DRAM_CTRL_CPU_BANKS (1 << 19) 94 #define DRAM_CTRL_CPU_BANKS (1 << 19)
95 #define DRAM_CTRL_CPU_WRITE_PRECHARGE (1 << 18) 95 #define DRAM_CTRL_CPU_WRITE_PRECHARGE (1 << 18)
96 #define DRAM_CTRL_BLOCK_WRITE (1 << 17) 96 #define DRAM_CTRL_BLOCK_WRITE (1 << 17)
97 #define DRAM_CTRL_REFRESH_COMMAND (1 << 16) 97 #define DRAM_CTRL_REFRESH_COMMAND (1 << 16)
98 #define DRAM_CTRL_SIZE_4 (0 << 13) 98 #define DRAM_CTRL_SIZE_4 (0 << 13)
99 #define DRAM_CTRL_SIZE_8 (1 << 13) 99 #define DRAM_CTRL_SIZE_8 (1 << 13)
100 #define DRAM_CTRL_SIZE_16 (2 << 13) 100 #define DRAM_CTRL_SIZE_16 (2 << 13)
101 #define DRAM_CTRL_SIZE_32 (3 << 13) 101 #define DRAM_CTRL_SIZE_32 (3 << 13)
102 #define DRAM_CTRL_SIZE_64 (4 << 13) 102 #define DRAM_CTRL_SIZE_64 (4 << 13)
103 #define DRAM_CTRL_SIZE_2 (5 << 13) 103 #define DRAM_CTRL_SIZE_2 (5 << 13)
104 #define DRAM_CTRL_COLUMN_SIZE_256 (0 << 11) 104 #define DRAM_CTRL_COLUMN_SIZE_256 (0 << 11)
105 #define DRAM_CTRL_COLUMN_SIZE_512 (2 << 11) 105 #define DRAM_CTRL_COLUMN_SIZE_512 (2 << 11)
106 #define DRAM_CTRL_COLUMN_SIZE_1024 (3 << 11) 106 #define DRAM_CTRL_COLUMN_SIZE_1024 (3 << 11)
107 #define DRAM_CTRL_BLOCK_WRITE_TIME (1 << 10) 107 #define DRAM_CTRL_BLOCK_WRITE_TIME (1 << 10)
108 #define DRAM_CTRL_BLOCK_WRITE_PRECHARGE (1 << 9) 108 #define DRAM_CTRL_BLOCK_WRITE_PRECHARGE (1 << 9)
109 #define DRAM_CTRL_ACTIVE_PRECHARGE (1 << 8) 109 #define DRAM_CTRL_ACTIVE_PRECHARGE (1 << 8)
110 #define DRAM_CTRL_RESET (1 << 7) 110 #define DRAM_CTRL_RESET (1 << 7)
111 #define DRAM_CTRL_REMAIN_ACTIVE (1 << 6) 111 #define DRAM_CTRL_REMAIN_ACTIVE (1 << 6)
112 #define DRAM_CTRL_BANKS (1 << 1) 112 #define DRAM_CTRL_BANKS (1 << 1)
113 #define DRAM_CTRL_WRITE_PRECHARGE (1 << 0) 113 #define DRAM_CTRL_WRITE_PRECHARGE (1 << 0)
114 114
115 /* ----- Arvitration control register -------------------------- */ 115 /* ----- Arvitration control register -------------------------- */
116 #define ARBITRATION_CTRL (0x000014 + VOYAGER_BASE) 116 #define ARBITRATION_CTRL (0x000014 + VOYAGER_BASE)
117 #define ARBITRATION_CTRL_CPUMEM (1 << 29) 117 #define ARBITRATION_CTRL_CPUMEM (1 << 29)
118 #define ARBITRATION_CTRL_INTMEM (1 << 28) 118 #define ARBITRATION_CTRL_INTMEM (1 << 28)
119 #define ARBITRATION_CTRL_USB_OFF (0 << 24) 119 #define ARBITRATION_CTRL_USB_OFF (0 << 24)
120 #define ARBITRATION_CTRL_USB_PRIORITY_1 (1 << 24) 120 #define ARBITRATION_CTRL_USB_PRIORITY_1 (1 << 24)
121 #define ARBITRATION_CTRL_USB_PRIORITY_2 (2 << 24) 121 #define ARBITRATION_CTRL_USB_PRIORITY_2 (2 << 24)
122 #define ARBITRATION_CTRL_USB_PRIORITY_3 (3 << 24) 122 #define ARBITRATION_CTRL_USB_PRIORITY_3 (3 << 24)
123 #define ARBITRATION_CTRL_USB_PRIORITY_4 (4 << 24) 123 #define ARBITRATION_CTRL_USB_PRIORITY_4 (4 << 24)
124 #define ARBITRATION_CTRL_USB_PRIORITY_5 (5 << 24) 124 #define ARBITRATION_CTRL_USB_PRIORITY_5 (5 << 24)
125 #define ARBITRATION_CTRL_USB_PRIORITY_6 (6 << 24) 125 #define ARBITRATION_CTRL_USB_PRIORITY_6 (6 << 24)
126 #define ARBITRATION_CTRL_USB_PRIORITY_7 (7 << 24) 126 #define ARBITRATION_CTRL_USB_PRIORITY_7 (7 << 24)
127 #define ARBITRATION_CTRL_PANEL_OFF (0 << 20) 127 #define ARBITRATION_CTRL_PANEL_OFF (0 << 20)
128 #define ARBITRATION_CTRL_PANEL_PRIORITY_1 (1 << 20) 128 #define ARBITRATION_CTRL_PANEL_PRIORITY_1 (1 << 20)
129 #define ARBITRATION_CTRL_PANEL_PRIORITY_2 (2 << 20) 129 #define ARBITRATION_CTRL_PANEL_PRIORITY_2 (2 << 20)
130 #define ARBITRATION_CTRL_PANEL_PRIORITY_3 (3 << 20) 130 #define ARBITRATION_CTRL_PANEL_PRIORITY_3 (3 << 20)
131 #define ARBITRATION_CTRL_PANEL_PRIORITY_4 (4 << 20) 131 #define ARBITRATION_CTRL_PANEL_PRIORITY_4 (4 << 20)
132 #define ARBITRATION_CTRL_PANEL_PRIORITY_5 (5 << 20) 132 #define ARBITRATION_CTRL_PANEL_PRIORITY_5 (5 << 20)
133 #define ARBITRATION_CTRL_PANEL_PRIORITY_6 (6 << 20) 133 #define ARBITRATION_CTRL_PANEL_PRIORITY_6 (6 << 20)
134 #define ARBITRATION_CTRL_PANEL_PRIORITY_7 (7 << 20) 134 #define ARBITRATION_CTRL_PANEL_PRIORITY_7 (7 << 20)
135 #define ARBITRATION_CTRL_ZVPORT_OFF (0 << 16) 135 #define ARBITRATION_CTRL_ZVPORT_OFF (0 << 16)
136 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_1 (1 << 16) 136 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_1 (1 << 16)
137 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_2 (2 << 16) 137 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_2 (2 << 16)
138 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_3 (3 << 16) 138 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_3 (3 << 16)
139 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_4 (4 << 16) 139 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_4 (4 << 16)
140 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_5 (5 << 16) 140 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_5 (5 << 16)
141 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_6 (6 << 16) 141 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_6 (6 << 16)
142 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_7 (7 << 16) 142 #define ARBITRATION_CTRL_ZVPORTL_PRIORITY_7 (7 << 16)
143 #define ARBITRATION_CTRL_CMD_INTPR_OFF (0 << 12) 143 #define ARBITRATION_CTRL_CMD_INTPR_OFF (0 << 12)
144 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 (1 << 12) 144 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 (1 << 12)
145 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_2 (2 << 12) 145 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_2 (2 << 12)
146 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_3 (3 << 12) 146 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_3 (3 << 12)
147 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_4 (4 << 12) 147 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_4 (4 << 12)
148 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_5 (5 << 12) 148 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_5 (5 << 12)
149 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_6 (6 << 12) 149 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_6 (6 << 12)
150 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_7 (7 << 12) 150 #define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_7 (7 << 12)
151 #define ARBITRATION_CTRL_DMA_OFF (0 << 8) 151 #define ARBITRATION_CTRL_DMA_OFF (0 << 8)
152 #define ARBITRATION_CTRL_DMA_PRIORITY_1 (1 << 8) 152 #define ARBITRATION_CTRL_DMA_PRIORITY_1 (1 << 8)
153 #define ARBITRATION_CTRL_DMA_PRIORITY_2 (2 << 8) 153 #define ARBITRATION_CTRL_DMA_PRIORITY_2 (2 << 8)
154 #define ARBITRATION_CTRL_DMA_PRIORITY_3 (3 << 8) 154 #define ARBITRATION_CTRL_DMA_PRIORITY_3 (3 << 8)
155 #define ARBITRATION_CTRL_DMA_PRIORITY_4 (4 << 8) 155 #define ARBITRATION_CTRL_DMA_PRIORITY_4 (4 << 8)
156 #define ARBITRATION_CTRL_DMA_PRIORITY_5 (5 << 8) 156 #define ARBITRATION_CTRL_DMA_PRIORITY_5 (5 << 8)
157 #define ARBITRATION_CTRL_DMA_PRIORITY_6 (6 << 8) 157 #define ARBITRATION_CTRL_DMA_PRIORITY_6 (6 << 8)
158 #define ARBITRATION_CTRL_DMA_PRIORITY_7 (7 << 8) 158 #define ARBITRATION_CTRL_DMA_PRIORITY_7 (7 << 8)
159 #define ARBITRATION_CTRL_VIDEO_OFF (0 << 4) 159 #define ARBITRATION_CTRL_VIDEO_OFF (0 << 4)
160 #define ARBITRATION_CTRL_VIDEO_PRIORITY_1 (1 << 4) 160 #define ARBITRATION_CTRL_VIDEO_PRIORITY_1 (1 << 4)
161 #define ARBITRATION_CTRL_VIDEO_PRIORITY_2 (2 << 4) 161 #define ARBITRATION_CTRL_VIDEO_PRIORITY_2 (2 << 4)
162 #define ARBITRATION_CTRL_VIDEO_PRIORITY_3 (3 << 4) 162 #define ARBITRATION_CTRL_VIDEO_PRIORITY_3 (3 << 4)
163 #define ARBITRATION_CTRL_VIDEO_PRIORITY_4 (4 << 4) 163 #define ARBITRATION_CTRL_VIDEO_PRIORITY_4 (4 << 4)
164 #define ARBITRATION_CTRL_VIDEO_PRIORITY_5 (5 << 4) 164 #define ARBITRATION_CTRL_VIDEO_PRIORITY_5 (5 << 4)
165 #define ARBITRATION_CTRL_VIDEO_PRIORITY_6 (6 << 4) 165 #define ARBITRATION_CTRL_VIDEO_PRIORITY_6 (6 << 4)
166 #define ARBITRATION_CTRL_VIDEO_PRIORITY_7 (7 << 4) 166 #define ARBITRATION_CTRL_VIDEO_PRIORITY_7 (7 << 4)
167 #define ARBITRATION_CTRL_CRT_OFF (0 << 0) 167 #define ARBITRATION_CTRL_CRT_OFF (0 << 0)
168 #define ARBITRATION_CTRL_CRT_PRIORITY_1 (1 << 0) 168 #define ARBITRATION_CTRL_CRT_PRIORITY_1 (1 << 0)
169 #define ARBITRATION_CTRL_CRT_PRIORITY_2 (2 << 0) 169 #define ARBITRATION_CTRL_CRT_PRIORITY_2 (2 << 0)
170 #define ARBITRATION_CTRL_CRT_PRIORITY_3 (3 << 0) 170 #define ARBITRATION_CTRL_CRT_PRIORITY_3 (3 << 0)
171 #define ARBITRATION_CTRL_CRT_PRIORITY_4 (4 << 0) 171 #define ARBITRATION_CTRL_CRT_PRIORITY_4 (4 << 0)
172 #define ARBITRATION_CTRL_CRT_PRIORITY_5 (5 << 0) 172 #define ARBITRATION_CTRL_CRT_PRIORITY_5 (5 << 0)
173 #define ARBITRATION_CTRL_CRT_PRIORITY_6 (6 << 0) 173 #define ARBITRATION_CTRL_CRT_PRIORITY_6 (6 << 0)
174 #define ARBITRATION_CTRL_CRT_PRIORITY_7 (7 << 0) 174 #define ARBITRATION_CTRL_CRT_PRIORITY_7 (7 << 0)
175 175
176 /* ----- Command list status register -------------------------- */ 176 /* ----- Command list status register -------------------------- */
177 #define CMD_INTPR_STATUS (0x000024 + VOYAGER_BASE) 177 #define CMD_INTPR_STATUS (0x000024 + VOYAGER_BASE)
178 178
179 /* ----- Interrupt status register ----------------------------- */ 179 /* ----- Interrupt status register ----------------------------- */
180 #define INT_STATUS (0x00002c + VOYAGER_BASE) 180 #define INT_STATUS (0x00002c + VOYAGER_BASE)
181 #define INT_STATUS_UH (1 << 6) 181 #define INT_STATUS_UH (1 << 6)
182 #define INT_STATUS_MC (1 << 10) 182 #define INT_STATUS_MC (1 << 10)
183 #define INT_STATUS_U0 (1 << 12) 183 #define INT_STATUS_U0 (1 << 12)
184 #define INT_STATUS_U1 (1 << 13) 184 #define INT_STATUS_U1 (1 << 13)
185 #define INT_STATUS_AC (1 << 17) 185 #define INT_STATUS_AC (1 << 17)
186 186
187 /* ----- Interrupt mask register ------------------------------ */ 187 /* ----- Interrupt mask register ------------------------------ */
188 #define VOYAGER_INT_MASK (0x000030 + VOYAGER_BASE) 188 #define VOYAGER_INT_MASK (0x000030 + VOYAGER_BASE)
189 #define VOYAGER_INT_MASK_AC (1 << 17) 189 #define VOYAGER_INT_MASK_AC (1 << 17)
190 190
191 /* ----- Current Gate register ---------------------------------*/ 191 /* ----- Current Gate register ---------------------------------*/
192 #define CURRENT_GATE (0x000038 + VOYAGER_BASE) 192 #define CURRENT_GATE (0x000038 + VOYAGER_BASE)
193 193
194 /* ----- Power mode 0 gate register --------------------------- */ 194 /* ----- Power mode 0 gate register --------------------------- */
195 #define POWER_MODE0_GATE (0x000040 + VOYAGER_BASE) 195 #define POWER_MODE0_GATE (0x000040 + VOYAGER_BASE)
196 #define POWER_MODE0_GATE_G (1 << 6) 196 #define POWER_MODE0_GATE_G (1 << 6)
197 #define POWER_MODE0_GATE_U0 (1 << 7) 197 #define POWER_MODE0_GATE_U0 (1 << 7)
198 #define POWER_MODE0_GATE_U1 (1 << 8) 198 #define POWER_MODE0_GATE_U1 (1 << 8)
199 #define POWER_MODE0_GATE_UH (1 << 11) 199 #define POWER_MODE0_GATE_UH (1 << 11)
200 #define POWER_MODE0_GATE_AC (1 << 18) 200 #define POWER_MODE0_GATE_AC (1 << 18)
201 201
202 /* ----- Power mode 1 gate register --------------------------- */ 202 /* ----- Power mode 1 gate register --------------------------- */
203 #define POWER_MODE1_GATE (0x000048 + VOYAGER_BASE) 203 #define POWER_MODE1_GATE (0x000048 + VOYAGER_BASE)
204 #define POWER_MODE1_GATE_G (1 << 6) 204 #define POWER_MODE1_GATE_G (1 << 6)
205 #define POWER_MODE1_GATE_U0 (1 << 7) 205 #define POWER_MODE1_GATE_U0 (1 << 7)
206 #define POWER_MODE1_GATE_U1 (1 << 8) 206 #define POWER_MODE1_GATE_U1 (1 << 8)
207 #define POWER_MODE1_GATE_UH (1 << 11) 207 #define POWER_MODE1_GATE_UH (1 << 11)
208 #define POWER_MODE1_GATE_AC (1 << 18) 208 #define POWER_MODE1_GATE_AC (1 << 18)
209 209
210 /* ----- Power mode 0 clock register -------------------------- */ 210 /* ----- Power mode 0 clock register -------------------------- */
211 #define POWER_MODE0_CLOCK (0x000044 + VOYAGER_BASE) 211 #define POWER_MODE0_CLOCK (0x000044 + VOYAGER_BASE)
212 212
213 /* ----- Power mode 1 clock register -------------------------- */ 213 /* ----- Power mode 1 clock register -------------------------- */
214 #define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE) 214 #define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE)
215 215
216 /* ----- Power mode controll register ------------------------- */ 216 /* ----- Power mode control register ------------------------- */
217 #define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE) 217 #define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE)
218 218
219 /* ----- Miscellaneous Timing register ------------------------ */ 219 /* ----- Miscellaneous Timing register ------------------------ */
220 #define SYSTEM_DRAM_CTRL (0x000068 + VOYAGER_BASE) 220 #define SYSTEM_DRAM_CTRL (0x000068 + VOYAGER_BASE)
221 221
222 /* ----- PWM register ------------------------------------------*/ 222 /* ----- PWM register ------------------------------------------*/
223 #define PWM_0 (0x010020 + VOYAGER_BASE) 223 #define PWM_0 (0x010020 + VOYAGER_BASE)
224 #define PWM_0_HC(x) (((x)&0x0fff)<<20) 224 #define PWM_0_HC(x) (((x)&0x0fff)<<20)
225 #define PWM_0_LC(x) (((x)&0x0fff)<<8 ) 225 #define PWM_0_LC(x) (((x)&0x0fff)<<8 )
226 #define PWM_0_CLK_DEV(x) (((x)&0x000f)<<4 ) 226 #define PWM_0_CLK_DEV(x) (((x)&0x000f)<<4 )
227 #define PWM_0_EN (1<<0) 227 #define PWM_0_EN (1<<0)
228 228
229 /* ----- I2C register ----------------------------------------- */ 229 /* ----- I2C register ----------------------------------------- */
230 #define I2C_BYTECOUNT (0x010040 + VOYAGER_BASE) 230 #define I2C_BYTECOUNT (0x010040 + VOYAGER_BASE)
231 #define I2C_CONTROL (0x010041 + VOYAGER_BASE) 231 #define I2C_CONTROL (0x010041 + VOYAGER_BASE)
232 #define I2C_STATUS (0x010042 + VOYAGER_BASE) 232 #define I2C_STATUS (0x010042 + VOYAGER_BASE)
233 #define I2C_RESET (0x010042 + VOYAGER_BASE) 233 #define I2C_RESET (0x010042 + VOYAGER_BASE)
234 #define I2C_SADDRESS (0x010043 + VOYAGER_BASE) 234 #define I2C_SADDRESS (0x010043 + VOYAGER_BASE)
235 #define I2C_DATA (0x010044 + VOYAGER_BASE) 235 #define I2C_DATA (0x010044 + VOYAGER_BASE)
236 236
237 /* ----- Controle register bits ----------------------------------------- */ 237 /* ----- Controle register bits ----------------------------------------- */
238 #define I2C_CONTROL_E (1 << 0) 238 #define I2C_CONTROL_E (1 << 0)
239 #define I2C_CONTROL_MODE (1 << 1) 239 #define I2C_CONTROL_MODE (1 << 1)
240 #define I2C_CONTROL_STATUS (1 << 2) 240 #define I2C_CONTROL_STATUS (1 << 2)
241 #define I2C_CONTROL_INT (1 << 4) 241 #define I2C_CONTROL_INT (1 << 4)
242 #define I2C_CONTROL_INTACK (1 << 5) 242 #define I2C_CONTROL_INTACK (1 << 5)
243 #define I2C_CONTROL_REPEAT (1 << 6) 243 #define I2C_CONTROL_REPEAT (1 << 6)
244 244
245 /* ----- Status register bits ----------------------------------------- */ 245 /* ----- Status register bits ----------------------------------------- */
246 #define I2C_STATUS_BUSY (1 << 0) 246 #define I2C_STATUS_BUSY (1 << 0)
247 #define I2C_STATUS_ACK (1 << 1) 247 #define I2C_STATUS_ACK (1 << 1)
248 #define I2C_STATUS_ERROR (1 << 2) 248 #define I2C_STATUS_ERROR (1 << 2)
249 #define I2C_STATUS_COMPLETE (1 << 3) 249 #define I2C_STATUS_COMPLETE (1 << 3)
250 250
251 /* ----- Reset register ---------------------------------------------- */ 251 /* ----- Reset register ---------------------------------------------- */
252 #define I2C_RESET_ERROR (1 << 2) 252 #define I2C_RESET_ERROR (1 << 2)
253 253
254 /* ----- transmission frequencies ------------------------------------- */ 254 /* ----- transmission frequencies ------------------------------------- */
255 #define I2C_SADDRESS_SELECT (1 << 0) 255 #define I2C_SADDRESS_SELECT (1 << 0)
256 256
257 /* ----- Display Controll register ----------------------------------------- */ 257 /* ----- Display Controll register ----------------------------------------- */
258 #define PANEL_DISPLAY_CTRL (0x080000 + VOYAGER_BASE) 258 #define PANEL_DISPLAY_CTRL (0x080000 + VOYAGER_BASE)
259 #define PANEL_DISPLAY_CTRL_BIAS (1<<26) 259 #define PANEL_DISPLAY_CTRL_BIAS (1<<26)
260 #define PANEL_PAN_CTRL (0x080004 + VOYAGER_BASE) 260 #define PANEL_PAN_CTRL (0x080004 + VOYAGER_BASE)
261 #define PANEL_COLOR_KEY (0x080008 + VOYAGER_BASE) 261 #define PANEL_COLOR_KEY (0x080008 + VOYAGER_BASE)
262 #define PANEL_FB_ADDRESS (0x08000C + VOYAGER_BASE) 262 #define PANEL_FB_ADDRESS (0x08000C + VOYAGER_BASE)
263 #define PANEL_FB_WIDTH (0x080010 + VOYAGER_BASE) 263 #define PANEL_FB_WIDTH (0x080010 + VOYAGER_BASE)
264 #define PANEL_WINDOW_WIDTH (0x080014 + VOYAGER_BASE) 264 #define PANEL_WINDOW_WIDTH (0x080014 + VOYAGER_BASE)
265 #define PANEL_WINDOW_HEIGHT (0x080018 + VOYAGER_BASE) 265 #define PANEL_WINDOW_HEIGHT (0x080018 + VOYAGER_BASE)
266 #define PANEL_PLANE_TL (0x08001C + VOYAGER_BASE) 266 #define PANEL_PLANE_TL (0x08001C + VOYAGER_BASE)
267 #define PANEL_PLANE_BR (0x080020 + VOYAGER_BASE) 267 #define PANEL_PLANE_BR (0x080020 + VOYAGER_BASE)
268 #define PANEL_HORIZONTAL_TOTAL (0x080024 + VOYAGER_BASE) 268 #define PANEL_HORIZONTAL_TOTAL (0x080024 + VOYAGER_BASE)
269 #define PANEL_HORIZONTAL_SYNC (0x080028 + VOYAGER_BASE) 269 #define PANEL_HORIZONTAL_SYNC (0x080028 + VOYAGER_BASE)
270 #define PANEL_VERTICAL_TOTAL (0x08002C + VOYAGER_BASE) 270 #define PANEL_VERTICAL_TOTAL (0x08002C + VOYAGER_BASE)
271 #define PANEL_VERTICAL_SYNC (0x080030 + VOYAGER_BASE) 271 #define PANEL_VERTICAL_SYNC (0x080030 + VOYAGER_BASE)
272 #define PANEL_CURRENT_LINE (0x080034 + VOYAGER_BASE) 272 #define PANEL_CURRENT_LINE (0x080034 + VOYAGER_BASE)
273 #define VIDEO_DISPLAY_CTRL (0x080040 + VOYAGER_BASE) 273 #define VIDEO_DISPLAY_CTRL (0x080040 + VOYAGER_BASE)
274 #define VIDEO_FB_0_ADDRESS (0x080044 + VOYAGER_BASE) 274 #define VIDEO_FB_0_ADDRESS (0x080044 + VOYAGER_BASE)
275 #define VIDEO_FB_WIDTH (0x080048 + VOYAGER_BASE) 275 #define VIDEO_FB_WIDTH (0x080048 + VOYAGER_BASE)
276 #define VIDEO_FB_0_LAST_ADDRESS (0x08004C + VOYAGER_BASE) 276 #define VIDEO_FB_0_LAST_ADDRESS (0x08004C + VOYAGER_BASE)
277 #define VIDEO_PLANE_TL (0x080050 + VOYAGER_BASE) 277 #define VIDEO_PLANE_TL (0x080050 + VOYAGER_BASE)
278 #define VIDEO_PLANE_BR (0x080054 + VOYAGER_BASE) 278 #define VIDEO_PLANE_BR (0x080054 + VOYAGER_BASE)
279 #define VIDEO_SCALE (0x080058 + VOYAGER_BASE) 279 #define VIDEO_SCALE (0x080058 + VOYAGER_BASE)
280 #define VIDEO_INITIAL_SCALE (0x08005C + VOYAGER_BASE) 280 #define VIDEO_INITIAL_SCALE (0x08005C + VOYAGER_BASE)
281 #define VIDEO_YUV_CONSTANTS (0x080060 + VOYAGER_BASE) 281 #define VIDEO_YUV_CONSTANTS (0x080060 + VOYAGER_BASE)
282 #define VIDEO_FB_1_ADDRESS (0x080064 + VOYAGER_BASE) 282 #define VIDEO_FB_1_ADDRESS (0x080064 + VOYAGER_BASE)
283 #define VIDEO_FB_1_LAST_ADDRESS (0x080068 + VOYAGER_BASE) 283 #define VIDEO_FB_1_LAST_ADDRESS (0x080068 + VOYAGER_BASE)
284 #define VIDEO_ALPHA_DISPLAY_CTRL (0x080080 + VOYAGER_BASE) 284 #define VIDEO_ALPHA_DISPLAY_CTRL (0x080080 + VOYAGER_BASE)
285 #define VIDEO_ALPHA_FB_ADDRESS (0x080084 + VOYAGER_BASE) 285 #define VIDEO_ALPHA_FB_ADDRESS (0x080084 + VOYAGER_BASE)
286 #define VIDEO_ALPHA_FB_WIDTH (0x080088 + VOYAGER_BASE) 286 #define VIDEO_ALPHA_FB_WIDTH (0x080088 + VOYAGER_BASE)
287 #define VIDEO_ALPHA_FB_LAST_ADDRESS (0x08008C + VOYAGER_BASE) 287 #define VIDEO_ALPHA_FB_LAST_ADDRESS (0x08008C + VOYAGER_BASE)
288 #define VIDEO_ALPHA_PLANE_TL (0x080090 + VOYAGER_BASE) 288 #define VIDEO_ALPHA_PLANE_TL (0x080090 + VOYAGER_BASE)
289 #define VIDEO_ALPHA_PLANE_BR (0x080094 + VOYAGER_BASE) 289 #define VIDEO_ALPHA_PLANE_BR (0x080094 + VOYAGER_BASE)
290 #define VIDEO_ALPHA_SCALE (0x080098 + VOYAGER_BASE) 290 #define VIDEO_ALPHA_SCALE (0x080098 + VOYAGER_BASE)
291 #define VIDEO_ALPHA_INITIAL_SCALE (0x08009C + VOYAGER_BASE) 291 #define VIDEO_ALPHA_INITIAL_SCALE (0x08009C + VOYAGER_BASE)
292 #define VIDEO_ALPHA_CHROMA_KEY (0x0800A0 + VOYAGER_BASE) 292 #define VIDEO_ALPHA_CHROMA_KEY (0x0800A0 + VOYAGER_BASE)
293 #define PANEL_HWC_ADDRESS (0x0800F0 + VOYAGER_BASE) 293 #define PANEL_HWC_ADDRESS (0x0800F0 + VOYAGER_BASE)
294 #define PANEL_HWC_LOCATION (0x0800F4 + VOYAGER_BASE) 294 #define PANEL_HWC_LOCATION (0x0800F4 + VOYAGER_BASE)
295 #define PANEL_HWC_COLOR_12 (0x0800F8 + VOYAGER_BASE) 295 #define PANEL_HWC_COLOR_12 (0x0800F8 + VOYAGER_BASE)
296 #define PANEL_HWC_COLOR_3 (0x0800FC + VOYAGER_BASE) 296 #define PANEL_HWC_COLOR_3 (0x0800FC + VOYAGER_BASE)
297 #define ALPHA_DISPLAY_CTRL (0x080100 + VOYAGER_BASE) 297 #define ALPHA_DISPLAY_CTRL (0x080100 + VOYAGER_BASE)
298 #define ALPHA_FB_ADDRESS (0x080104 + VOYAGER_BASE) 298 #define ALPHA_FB_ADDRESS (0x080104 + VOYAGER_BASE)
299 #define ALPHA_FB_WIDTH (0x080108 + VOYAGER_BASE) 299 #define ALPHA_FB_WIDTH (0x080108 + VOYAGER_BASE)
300 #define ALPHA_PLANE_TL (0x08010C + VOYAGER_BASE) 300 #define ALPHA_PLANE_TL (0x08010C + VOYAGER_BASE)
301 #define ALPHA_PLANE_BR (0x080110 + VOYAGER_BASE) 301 #define ALPHA_PLANE_BR (0x080110 + VOYAGER_BASE)
302 #define ALPHA_CHROMA_KEY (0x080114 + VOYAGER_BASE) 302 #define ALPHA_CHROMA_KEY (0x080114 + VOYAGER_BASE)
303 #define CRT_DISPLAY_CTRL (0x080200 + VOYAGER_BASE) 303 #define CRT_DISPLAY_CTRL (0x080200 + VOYAGER_BASE)
304 #define CRT_FB_ADDRESS (0x080204 + VOYAGER_BASE) 304 #define CRT_FB_ADDRESS (0x080204 + VOYAGER_BASE)
305 #define CRT_FB_WIDTH (0x080208 + VOYAGER_BASE) 305 #define CRT_FB_WIDTH (0x080208 + VOYAGER_BASE)
306 #define CRT_HORIZONTAL_TOTAL (0x08020C + VOYAGER_BASE) 306 #define CRT_HORIZONTAL_TOTAL (0x08020C + VOYAGER_BASE)
307 #define CRT_HORIZONTAL_SYNC (0x080210 + VOYAGER_BASE) 307 #define CRT_HORIZONTAL_SYNC (0x080210 + VOYAGER_BASE)
308 #define CRT_VERTICAL_TOTAL (0x080214 + VOYAGER_BASE) 308 #define CRT_VERTICAL_TOTAL (0x080214 + VOYAGER_BASE)
309 #define CRT_VERTICAL_SYNC (0x080218 + VOYAGER_BASE) 309 #define CRT_VERTICAL_SYNC (0x080218 + VOYAGER_BASE)
310 #define CRT_SIGNATURE_ANALYZER (0x08021C + VOYAGER_BASE) 310 #define CRT_SIGNATURE_ANALYZER (0x08021C + VOYAGER_BASE)
311 #define CRT_CURRENT_LINE (0x080220 + VOYAGER_BASE) 311 #define CRT_CURRENT_LINE (0x080220 + VOYAGER_BASE)
312 #define CRT_MONITOR_DETECT (0x080224 + VOYAGER_BASE) 312 #define CRT_MONITOR_DETECT (0x080224 + VOYAGER_BASE)
313 #define CRT_HWC_ADDRESS (0x080230 + VOYAGER_BASE) 313 #define CRT_HWC_ADDRESS (0x080230 + VOYAGER_BASE)
314 #define CRT_HWC_LOCATION (0x080234 + VOYAGER_BASE) 314 #define CRT_HWC_LOCATION (0x080234 + VOYAGER_BASE)
315 #define CRT_HWC_COLOR_12 (0x080238 + VOYAGER_BASE) 315 #define CRT_HWC_COLOR_12 (0x080238 + VOYAGER_BASE)
316 #define CRT_HWC_COLOR_3 (0x08023C + VOYAGER_BASE) 316 #define CRT_HWC_COLOR_3 (0x08023C + VOYAGER_BASE)
317 #define CRT_PALETTE_RAM (0x080400 + VOYAGER_BASE) 317 #define CRT_PALETTE_RAM (0x080400 + VOYAGER_BASE)
318 #define PANEL_PALETTE_RAM (0x080800 + VOYAGER_BASE) 318 #define PANEL_PALETTE_RAM (0x080800 + VOYAGER_BASE)
319 #define VIDEO_PALETTE_RAM (0x080C00 + VOYAGER_BASE) 319 #define VIDEO_PALETTE_RAM (0x080C00 + VOYAGER_BASE)
320 320
321 /* ----- 8051 Controle register ----------------------------------------- */ 321 /* ----- 8051 Controle register ----------------------------------------- */
322 #define VOYAGER_8051_BASE (0x000c0000 + VOYAGER_BASE) 322 #define VOYAGER_8051_BASE (0x000c0000 + VOYAGER_BASE)
323 #define VOYAGER_8051_RESET (0x000b0000 + VOYAGER_BASE) 323 #define VOYAGER_8051_RESET (0x000b0000 + VOYAGER_BASE)
324 #define VOYAGER_8051_SELECT (0x000b0004 + VOYAGER_BASE) 324 #define VOYAGER_8051_SELECT (0x000b0004 + VOYAGER_BASE)
325 #define VOYAGER_8051_CPU_INT (0x000b000c + VOYAGER_BASE) 325 #define VOYAGER_8051_CPU_INT (0x000b000c + VOYAGER_BASE)
326 326
327 /* ----- AC97 Controle register ----------------------------------------- */ 327 /* ----- AC97 Controle register ----------------------------------------- */
328 #define AC97_TX_SLOT0 (0x00000000 + VOYAGER_AC97_BASE) 328 #define AC97_TX_SLOT0 (0x00000000 + VOYAGER_AC97_BASE)
329 #define AC97_CONTROL_STATUS (0x00000080 + VOYAGER_AC97_BASE) 329 #define AC97_CONTROL_STATUS (0x00000080 + VOYAGER_AC97_BASE)
330 #define AC97C_READ (1 << 19) 330 #define AC97C_READ (1 << 19)
331 #define AC97C_WD_BIT (1 << 2) 331 #define AC97C_WD_BIT (1 << 2)
332 #define AC97C_INDEX_MASK 0x7f 332 #define AC97C_INDEX_MASK 0x7f
333 333
334 /* arch/sh/cchips/voyagergx/consistent.c */ 334 /* arch/sh/cchips/voyagergx/consistent.c */
335 void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t); 335 void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t);
336 int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t); 336 int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t);
337 337
338 /* arch/sh/cchips/voyagergx/irq.c */ 338 /* arch/sh/cchips/voyagergx/irq.c */
339 void setup_voyagergx_irq(void); 339 void setup_voyagergx_irq(void);
340 340
341 #endif /* _VOYAGER_GX_REG_H */ 341 #endif /* _VOYAGER_GX_REG_H */
342 342