Eric Lee / linux-smarc-t335x-v3.2

Download as
Browse Code ยป

Commit 0095d58b4a91b9fb57aeb781909355b232517c64

Authored by Joe Perches
Committed by Paul Mundt
1 parent eb9c7f4198
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

sh: include/asm-sh/: Spelling fixes. 

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 3 changed files with 17 additions and 17 deletions Side-by-side Diff

include/asm-sh/hd64461.h
Diff comments   View file @ 0095d58
... ... @@ -46,10 +46,10 @@
46 46 /* CPU Data Bus Control Register */
47 47 #define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04)
48 48  
49   -/* Base Adress Register */
  49 +/* Base Address Register */
50 50 #define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000)
51 51  
52   -/* Line increment adress */
  52 +/* Line increment address */
53 53 #define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002)
54 54  
55 55 /* Controls LCD controller */
56 56  
... ... @@ -80,9 +80,9 @@
80 80 #define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e)
81 81  
82 82 /* Palette Registers */
83   -#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Adress Register */
  83 +#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */
84 84 #define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */
85   -#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Adress Register */
  85 +#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */
86 86 #define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */
87 87  
88 88 #define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */
... ... @@ -97,8 +97,8 @@
97 97 #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98 98  
99 99 /* Line Drawing Registers */
100   -#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Adress Register (H) */
101   -#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Adress Register (L) */
  100 +#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */
  101 +#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */
102 102 #define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */
103 103 #define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */
104 104 #define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */
105 105  
... ... @@ -106,16 +106,16 @@
106 106 #define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */
107 107  
108 108 /* BitBLT Registers */
109   -#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Adress Register (H) */
110   -#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Adress Register (L) */
111   -#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Adress Register (H) */
112   -#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Adress Register (L) */
  109 +#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */
  110 +#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */
  111 +#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */
  112 +#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */
113 113 #define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */
114 114 #define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */
115   -#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Adress Register (H) */
116   -#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Adress Register (L) */
117   -#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Adress Register (H) */
118   -#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Adress Register (L) */
  115 +#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */
  116 +#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */
  117 +#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */
  118 +#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */
119 119 #define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */
120 120 #define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */
121 121  
include/asm-sh/microdev.h
Diff comments   View file @ 0095d58
... ... @@ -17,7 +17,7 @@
17 17 /*
18 18 * The following are useful macros for manipulating the interrupt
19 19 * controller (INTC) on the CPU-board FPGA. should be noted that there
20   - * is an INTC on the FPGA, and a seperate INTC on the SH4-202 core -
  20 + * is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
21 21 * these are two different things, both of which need to be prorammed to
22 22 * correctly route - unfortunately, they have the same name and
23 23 * abbreviations!
... ... @@ -25,7 +25,7 @@
25 25 #define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
26 26 #define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
27 27 #define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
28   -#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interupt mask to enable/disable INTC in CPU-board FPGA */
  28 +#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
29 29 #define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
30 30 #define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
31 31 #define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
include/asm-sh/voyagergx.h
Diff comments   View file @ 0095d58
... ... @@ -213,7 +213,7 @@
213 213 /* ----- Power mode 1 clock register -------------------------- */
214 214 #define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE)
215 215  
216   -/* ----- Power mode controll register ------------------------- */
  216 +/* ----- Power mode control register ------------------------- */
217 217 #define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE)
218 218  
219 219 /* ----- Miscellaneous Timing register ------------------------ */