gpio: Add STMPE GPIO driver

Add support for the GPIOs on STMPE I/O Expanders. [l.fu@pengutronix.de: fix set direction input] [l.fu@pengutronix.de: set GPIO alternate function while requesting] Acked-by: Luotao Fu <l.fu@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

gpio: Add STMPE GPIO driver
Add support for the GPIOs on STMPE I/O Expanders. [l.fu@pengutronix.de: fix set direction input] [l.fu@pengutronix.de: set GPIO alternate function while requesting] Acked-by: Luotao Fu <l.fu@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Rabin Vincent · Samuel Ortiz
1 parent 27e34995e1
Showing 3 changed files with 407 additions and 0 deletions Side-by-side Diff
drivers/gpio/Kconfig
drivers/gpio/Makefile
drivers/gpio/stmpe-gpio.c
@@ -206,6 +206,13 @@
 	  8 bits:  sx1508q
 	  16 bits: sx1509q
  
+config GPIO_STMPE
+	bool "STMPE GPIOs"
+	depends on MFD_STMPE
+	help
+	  This enables support for the GPIOs found on the STMPE I/O
+	  Expanders.
+
 config GPIO_TC35892
 	bool "TC35892 GPIOs"
 	depends on MFD_TC35892
@@ -20,6 +20,7 @@
 obj-$(CONFIG_GPIO_PCA953X)	+= pca953x.o
 obj-$(CONFIG_GPIO_PCF857X)	+= pcf857x.o
 obj-$(CONFIG_GPIO_PL061)	+= pl061.o
+obj-$(CONFIG_GPIO_STMPE)	+= stmpe-gpio.o
 obj-$(CONFIG_GPIO_TC35892)	+= tc35892-gpio.o
 obj-$(CONFIG_GPIO_TIMBERDALE)	+= timbgpio.o
 obj-$(CONFIG_GPIO_TWL4030)	+= twl4030-gpio.o
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License, version 2
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/stmpe.h>
+
+/*
+ * These registers are modified under the irq bus lock and cached to avoid
+ * unnecessary writes in bus_sync_unlock.
+ */
+enum { REG_RE, REG_FE, REG_IE };
+
+#define CACHE_NR_REGS	3
+#define CACHE_NR_BANKS	(STMPE_NR_GPIOS / 8)
+
+struct stmpe_gpio {
+	struct gpio_chip chip;
+	struct stmpe *stmpe;
+	struct device *dev;
+	struct mutex irq_lock;
+
+	int irq_base;
+
+	/* Caches of interrupt control registers for bus_lock */
+	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
+	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
+};
+
+static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
+{
+	return container_of(chip, struct stmpe_gpio, chip);
+}
+
+static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
+	u8 mask = 1 << (offset % 8);
+	int ret;
+
+	ret = stmpe_reg_read(stmpe, reg);
+	if (ret < 0)
+		return ret;
+
+	return ret & mask;
+}
+
+static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
+	u8 reg = stmpe->regs[which] - (offset / 8);
+	u8 mask = 1 << (offset % 8);
+
+	stmpe_reg_write(stmpe, reg, mask);
+}
+
+static int stmpe_gpio_direction_output(struct gpio_chip *chip,
+					 unsigned offset, int val)
+{
+	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
+	u8 mask = 1 << (offset % 8);
+
+	stmpe_gpio_set(chip, offset, val);
+
+	return stmpe_set_bits(stmpe, reg, mask, mask);
+}
+
+static int stmpe_gpio_direction_input(struct gpio_chip *chip,
+					unsigned offset)
+{
+	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
+	u8 mask = 1 << (offset % 8);
+
+	return stmpe_set_bits(stmpe, reg, mask, 0);
+}
+
+static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
+
+	return stmpe_gpio->irq_base + offset;
+}
+
+static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+
+	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
+}
+
+static struct gpio_chip template_chip = {
+	.label			= "stmpe",
+	.owner			= THIS_MODULE,
+	.direction_input	= stmpe_gpio_direction_input,
+	.get			= stmpe_gpio_get,
+	.direction_output	= stmpe_gpio_direction_output,
+	.set			= stmpe_gpio_set,
+	.to_irq			= stmpe_gpio_to_irq,
+	.request		= stmpe_gpio_request,
+	.can_sleep		= 1,
+};
+
+static int stmpe_gpio_irq_set_type(unsigned int irq, unsigned int type)
+{
+	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
+	int offset = irq - stmpe_gpio->irq_base;
+	int regoffset = offset / 8;
+	int mask = 1 << (offset % 8);
+
+	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
+		return -EINVAL;
+
+	if (type == IRQ_TYPE_EDGE_RISING)
+		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
+	else
+		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
+
+	if (type == IRQ_TYPE_EDGE_FALLING)
+		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
+	else
+		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
+
+	return 0;
+}
+
+static void stmpe_gpio_irq_lock(unsigned int irq)
+{
+	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
+
+	mutex_lock(&stmpe_gpio->irq_lock);
+}
+
+static void stmpe_gpio_irq_sync_unlock(unsigned int irq)
+{
+	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
+	static const u8 regmap[] = {
+		[REG_RE]	= STMPE_IDX_GPRER_LSB,
+		[REG_FE]	= STMPE_IDX_GPFER_LSB,
+		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
+	};
+	int i, j;
+
+	for (i = 0; i < CACHE_NR_REGS; i++) {
+		for (j = 0; j < num_banks; j++) {
+			u8 old = stmpe_gpio->oldregs[i][j];
+			u8 new = stmpe_gpio->regs[i][j];
+
+			if (new == old)
+				continue;
+
+			stmpe_gpio->oldregs[i][j] = new;
+			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
+		}
+	}
+
+	mutex_unlock(&stmpe_gpio->irq_lock);
+}
+
+static void stmpe_gpio_irq_mask(unsigned int irq)
+{
+	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
+	int offset = irq - stmpe_gpio->irq_base;
+	int regoffset = offset / 8;
+	int mask = 1 << (offset % 8);
+
+	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
+}
+
+static void stmpe_gpio_irq_unmask(unsigned int irq)
+{
+	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
+	int offset = irq - stmpe_gpio->irq_base;
+	int regoffset = offset / 8;
+	int mask = 1 << (offset % 8);
+
+	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
+}
+
+static struct irq_chip stmpe_gpio_irq_chip = {
+	.name			= "stmpe-gpio",
+	.bus_lock		= stmpe_gpio_irq_lock,
+	.bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
+	.mask			= stmpe_gpio_irq_mask,
+	.unmask			= stmpe_gpio_irq_unmask,
+	.set_type		= stmpe_gpio_irq_set_type,
+};
+
+static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
+{
+	struct stmpe_gpio *stmpe_gpio = dev;
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
+	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
+	u8 status[num_banks];
+	int ret;
+	int i;
+
+	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
+	if (ret < 0)
+		return IRQ_NONE;
+
+	for (i = 0; i < num_banks; i++) {
+		int bank = num_banks - i - 1;
+		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
+		unsigned int stat = status[i];
+
+		stat &= enabled;
+		if (!stat)
+			continue;
+
+		while (stat) {
+			int bit = __ffs(stat);
+			int line = bank * 8 + bit;
+
+			handle_nested_irq(stmpe_gpio->irq_base + line);
+			stat &= ~(1 << bit);
+		}
+
+		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
+		stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
+				status[i]);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
+{
+	int base = stmpe_gpio->irq_base;
+	int irq;
+
+	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
+		set_irq_chip_data(irq, stmpe_gpio);
+		set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip,
+					 handle_simple_irq);
+		set_irq_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+		set_irq_flags(irq, IRQF_VALID);
+#else
+		set_irq_noprobe(irq);
+#endif
+	}
+
+	return 0;
+}
+
+static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
+{
+	int base = stmpe_gpio->irq_base;
+	int irq;
+
+	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
+#ifdef CONFIG_ARM
+		set_irq_flags(irq, 0);
+#endif
+		set_irq_chip_and_handler(irq, NULL, NULL);
+		set_irq_chip_data(irq, NULL);
+	}
+}
+
+static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
+{
+	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
+	struct stmpe_gpio_platform_data *pdata;
+	struct stmpe_gpio *stmpe_gpio;
+	int ret;
+	int irq;
+
+	pdata = stmpe->pdata->gpio;
+	if (!pdata)
+		return -ENODEV;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
+	if (!stmpe_gpio)
+		return -ENOMEM;
+
+	mutex_init(&stmpe_gpio->irq_lock);
+
+	stmpe_gpio->dev = &pdev->dev;
+	stmpe_gpio->stmpe = stmpe;
+
+	stmpe_gpio->chip = template_chip;
+	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
+	stmpe_gpio->chip.dev = &pdev->dev;
+	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
+
+	stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
+
+	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
+	if (ret)
+		return ret;
+
+	ret = stmpe_gpio_irq_init(stmpe_gpio);
+	if (ret)
+		goto out_free;
+
+	ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
+				   "stmpe-gpio", stmpe_gpio);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
+		goto out_removeirq;
+	}
+
+	ret = gpiochip_add(&stmpe_gpio->chip);
+	if (ret) {
+		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
+		goto out_freeirq;
+	}
+
+	if (pdata && pdata->setup)
+		pdata->setup(stmpe, stmpe_gpio->chip.base);
+
+	platform_set_drvdata(pdev, stmpe_gpio);
+
+	return 0;
+
+out_freeirq:
+	free_irq(irq, stmpe_gpio);
+out_removeirq:
+	stmpe_gpio_irq_remove(stmpe_gpio);
+out_free:
+	kfree(stmpe_gpio);
+	return ret;
+}
+
+static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
+{
+	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
+	struct stmpe *stmpe = stmpe_gpio->stmpe;
+	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
+	int irq = platform_get_irq(pdev, 0);
+	int ret;
+
+	if (pdata && pdata->remove)
+		pdata->remove(stmpe, stmpe_gpio->chip.base);
+
+	ret = gpiochip_remove(&stmpe_gpio->chip);
+	if (ret < 0) {
+		dev_err(stmpe_gpio->dev,
+			"unable to remove gpiochip: %d\n", ret);
+		return ret;
+	}
+
+	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
+
+	free_irq(irq, stmpe_gpio);
+	stmpe_gpio_irq_remove(stmpe_gpio);
+	platform_set_drvdata(pdev, NULL);
+	kfree(stmpe_gpio);
+
+	return 0;
+}
+
+static struct platform_driver stmpe_gpio_driver = {
+	.driver.name	= "stmpe-gpio",
+	.driver.owner	= THIS_MODULE,
+	.probe		= stmpe_gpio_probe,
+	.remove		= __devexit_p(stmpe_gpio_remove),
+};
+
+static int __init stmpe_gpio_init(void)
+{
+	return platform_driver_register(&stmpe_gpio_driver);
+}
+subsys_initcall(stmpe_gpio_init);
+
+static void __exit stmpe_gpio_exit(void)
+{
+	platform_driver_unregister(&stmpe_gpio_driver);
+}
+module_exit(stmpe_gpio_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("STMPExxxx GPIO driver");
+MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
...	...	@@ -206,6 +206,13 @@
206	206	8 bits: sx1508q
207	207	16 bits: sx1509q
208	208
	209	+config GPIO_STMPE
	210	+ bool "STMPE GPIOs"
	211	+ depends on MFD_STMPE
	212	+ help
	213	+ This enables support for the GPIOs found on the STMPE I/O
	214	+ Expanders.
	215	+
209	216	config GPIO_TC35892
210	217	bool "TC35892 GPIOs"
211	218	depends on MFD_TC35892
...	...	@@ -20,6 +20,7 @@
20	20	obj-$(CONFIG_GPIO_PCA953X) += pca953x.o
21	21	obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o
22	22	obj-$(CONFIG_GPIO_PL061) += pl061.o
	23	+obj-$(CONFIG_GPIO_STMPE) += stmpe-gpio.o
23	24	obj-$(CONFIG_GPIO_TC35892) += tc35892-gpio.o
24	25	obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o
25	26	obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o
	1	+/*
	2	+ * Copyright (C) ST-Ericsson SA 2010
	3	+ *
	4	+ * License Terms: GNU General Public License, version 2
	5	+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	+ */
	7	+
	8	+#include <linux/module.h>
	9	+#include <linux/init.h>
	10	+#include <linux/platform_device.h>
	11	+#include <linux/slab.h>
	12	+#include <linux/gpio.h>
	13	+#include <linux/irq.h>
	14	+#include <linux/interrupt.h>
	15	+#include <linux/mfd/stmpe.h>
	16	+
	17	+/*
	18	+ * These registers are modified under the irq bus lock and cached to avoid
	19	+ * unnecessary writes in bus_sync_unlock.
	20	+ */
	21	+enum { REG_RE, REG_FE, REG_IE };
	22	+
	23	+#define CACHE_NR_REGS 3
	24	+#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
	25	+
	26	+struct stmpe_gpio {
	27	+ struct gpio_chip chip;
	28	+ struct stmpe *stmpe;
	29	+ struct device *dev;
	30	+ struct mutex irq_lock;
	31	+
	32	+ int irq_base;
	33	+
	34	+ /* Caches of interrupt control registers for bus_lock */
	35	+ u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	36	+ u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	37	+};
	38	+
	39	+static inline struct stmpe_gpio to_stmpe_gpio(struct gpio_chip chip)
	40	+{
	41	+ return container_of(chip, struct stmpe_gpio, chip);
	42	+}
	43	+
	44	+static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
	45	+{
	46	+ struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	47	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	48	+ u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	49	+ u8 mask = 1 << (offset % 8);
	50	+ int ret;
	51	+
	52	+ ret = stmpe_reg_read(stmpe, reg);
	53	+ if (ret < 0)
	54	+ return ret;
	55	+
	56	+ return ret & mask;
	57	+}
	58	+
	59	+static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	60	+{
	61	+ struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	62	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	63	+ int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	64	+ u8 reg = stmpe->regs[which] - (offset / 8);
	65	+ u8 mask = 1 << (offset % 8);
	66	+
	67	+ stmpe_reg_write(stmpe, reg, mask);
	68	+}
	69	+
	70	+static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	71	+ unsigned offset, int val)
	72	+{
	73	+ struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	74	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	75	+ u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	76	+ u8 mask = 1 << (offset % 8);
	77	+
	78	+ stmpe_gpio_set(chip, offset, val);
	79	+
	80	+ return stmpe_set_bits(stmpe, reg, mask, mask);
	81	+}
	82	+
	83	+static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	84	+ unsigned offset)
	85	+{
	86	+ struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	87	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	88	+ u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	89	+ u8 mask = 1 << (offset % 8);
	90	+
	91	+ return stmpe_set_bits(stmpe, reg, mask, 0);
	92	+}
	93	+
	94	+static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	95	+{
	96	+ struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	97	+
	98	+ return stmpe_gpio->irq_base + offset;
	99	+}
	100	+
	101	+static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
	102	+{
	103	+ struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	104	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	105	+
	106	+ return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
	107	+}
	108	+
	109	+static struct gpio_chip template_chip = {
	110	+ .label = "stmpe",
	111	+ .owner = THIS_MODULE,
	112	+ .direction_input = stmpe_gpio_direction_input,
	113	+ .get = stmpe_gpio_get,
	114	+ .direction_output = stmpe_gpio_direction_output,
	115	+ .set = stmpe_gpio_set,
	116	+ .to_irq = stmpe_gpio_to_irq,
	117	+ .request = stmpe_gpio_request,
	118	+ .can_sleep = 1,
	119	+};
	120	+
	121	+static int stmpe_gpio_irq_set_type(unsigned int irq, unsigned int type)
	122	+{
	123	+ struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	124	+ int offset = irq - stmpe_gpio->irq_base;
	125	+ int regoffset = offset / 8;
	126	+ int mask = 1 << (offset % 8);
	127	+
	128	+ if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
	129	+ return -EINVAL;
	130	+
	131	+ if (type == IRQ_TYPE_EDGE_RISING)
	132	+ stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	133	+ else
	134	+ stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	135	+
	136	+ if (type == IRQ_TYPE_EDGE_FALLING)
	137	+ stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	138	+ else
	139	+ stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	140	+
	141	+ return 0;
	142	+}
	143	+
	144	+static void stmpe_gpio_irq_lock(unsigned int irq)
	145	+{
	146	+ struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	147	+
	148	+ mutex_lock(&stmpe_gpio->irq_lock);
	149	+}
	150	+
	151	+static void stmpe_gpio_irq_sync_unlock(unsigned int irq)
	152	+{
	153	+ struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	154	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	155	+ int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	156	+ static const u8 regmap[] = {
	157	+ [REG_RE] = STMPE_IDX_GPRER_LSB,
	158	+ [REG_FE] = STMPE_IDX_GPFER_LSB,
	159	+ [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
	160	+ };
	161	+ int i, j;
	162	+
	163	+ for (i = 0; i < CACHE_NR_REGS; i++) {
	164	+ for (j = 0; j < num_banks; j++) {
	165	+ u8 old = stmpe_gpio->oldregs[i][j];
	166	+ u8 new = stmpe_gpio->regs[i][j];
	167	+
	168	+ if (new == old)
	169	+ continue;
	170	+
	171	+ stmpe_gpio->oldregs[i][j] = new;
	172	+ stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
	173	+ }
	174	+ }
	175	+
	176	+ mutex_unlock(&stmpe_gpio->irq_lock);
	177	+}
	178	+
	179	+static void stmpe_gpio_irq_mask(unsigned int irq)
	180	+{
	181	+ struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	182	+ int offset = irq - stmpe_gpio->irq_base;
	183	+ int regoffset = offset / 8;
	184	+ int mask = 1 << (offset % 8);
	185	+
	186	+ stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	187	+}
	188	+
	189	+static void stmpe_gpio_irq_unmask(unsigned int irq)
	190	+{
	191	+ struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	192	+ int offset = irq - stmpe_gpio->irq_base;
	193	+ int regoffset = offset / 8;
	194	+ int mask = 1 << (offset % 8);
	195	+
	196	+ stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	197	+}
	198	+
	199	+static struct irq_chip stmpe_gpio_irq_chip = {
	200	+ .name = "stmpe-gpio",
	201	+ .bus_lock = stmpe_gpio_irq_lock,
	202	+ .bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	203	+ .mask = stmpe_gpio_irq_mask,
	204	+ .unmask = stmpe_gpio_irq_unmask,
	205	+ .set_type = stmpe_gpio_irq_set_type,
	206	+};
	207	+
	208	+static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	209	+{
	210	+ struct stmpe_gpio *stmpe_gpio = dev;
	211	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	212	+ u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	213	+ int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	214	+ u8 status[num_banks];
	215	+ int ret;
	216	+ int i;
	217	+
	218	+ ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	219	+ if (ret < 0)
	220	+ return IRQ_NONE;
	221	+
	222	+ for (i = 0; i < num_banks; i++) {
	223	+ int bank = num_banks - i - 1;
	224	+ unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	225	+ unsigned int stat = status[i];
	226	+
	227	+ stat &= enabled;
	228	+ if (!stat)
	229	+ continue;
	230	+
	231	+ while (stat) {
	232	+ int bit = __ffs(stat);
	233	+ int line = bank * 8 + bit;
	234	+
	235	+ handle_nested_irq(stmpe_gpio->irq_base + line);
	236	+ stat &= ~(1 << bit);
	237	+ }
	238	+
	239	+ stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
	240	+ stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
	241	+ status[i]);
	242	+ }
	243	+
	244	+ return IRQ_HANDLED;
	245	+}
	246	+
	247	+static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
	248	+{
	249	+ int base = stmpe_gpio->irq_base;
	250	+ int irq;
	251	+
	252	+ for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
	253	+ set_irq_chip_data(irq, stmpe_gpio);
	254	+ set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip,
	255	+ handle_simple_irq);
	256	+ set_irq_nested_thread(irq, 1);
	257	+#ifdef CONFIG_ARM
	258	+ set_irq_flags(irq, IRQF_VALID);
	259	+#else
	260	+ set_irq_noprobe(irq);
	261	+#endif
	262	+ }
	263	+
	264	+ return 0;
	265	+}
	266	+
	267	+static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
	268	+{
	269	+ int base = stmpe_gpio->irq_base;
	270	+ int irq;
	271	+
	272	+ for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
	273	+#ifdef CONFIG_ARM
	274	+ set_irq_flags(irq, 0);
	275	+#endif
	276	+ set_irq_chip_and_handler(irq, NULL, NULL);
	277	+ set_irq_chip_data(irq, NULL);
	278	+ }
	279	+}
	280	+
	281	+static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
	282	+{
	283	+ struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	284	+ struct stmpe_gpio_platform_data *pdata;
	285	+ struct stmpe_gpio *stmpe_gpio;
	286	+ int ret;
	287	+ int irq;
	288	+
	289	+ pdata = stmpe->pdata->gpio;
	290	+ if (!pdata)
	291	+ return -ENODEV;
	292	+
	293	+ irq = platform_get_irq(pdev, 0);
	294	+ if (irq < 0)
	295	+ return irq;
	296	+
	297	+ stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	298	+ if (!stmpe_gpio)
	299	+ return -ENOMEM;
	300	+
	301	+ mutex_init(&stmpe_gpio->irq_lock);
	302	+
	303	+ stmpe_gpio->dev = &pdev->dev;
	304	+ stmpe_gpio->stmpe = stmpe;
	305	+
	306	+ stmpe_gpio->chip = template_chip;
	307	+ stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	308	+ stmpe_gpio->chip.dev = &pdev->dev;
	309	+ stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
	310	+
	311	+ stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
	312	+
	313	+ ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	314	+ if (ret)
	315	+ return ret;
	316	+
	317	+ ret = stmpe_gpio_irq_init(stmpe_gpio);
	318	+ if (ret)
	319	+ goto out_free;
	320	+
	321	+ ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
	322	+ "stmpe-gpio", stmpe_gpio);
	323	+ if (ret) {
	324	+ dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
	325	+ goto out_removeirq;
	326	+ }
	327	+
	328	+ ret = gpiochip_add(&stmpe_gpio->chip);
	329	+ if (ret) {
	330	+ dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	331	+ goto out_freeirq;
	332	+ }
	333	+
	334	+ if (pdata && pdata->setup)
	335	+ pdata->setup(stmpe, stmpe_gpio->chip.base);
	336	+
	337	+ platform_set_drvdata(pdev, stmpe_gpio);
	338	+
	339	+ return 0;
	340	+
	341	+out_freeirq:
	342	+ free_irq(irq, stmpe_gpio);
	343	+out_removeirq:
	344	+ stmpe_gpio_irq_remove(stmpe_gpio);
	345	+out_free:
	346	+ kfree(stmpe_gpio);
	347	+ return ret;
	348	+}
	349	+
	350	+static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
	351	+{
	352	+ struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	353	+ struct stmpe *stmpe = stmpe_gpio->stmpe;
	354	+ struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	355	+ int irq = platform_get_irq(pdev, 0);
	356	+ int ret;
	357	+
	358	+ if (pdata && pdata->remove)
	359	+ pdata->remove(stmpe, stmpe_gpio->chip.base);
	360	+
	361	+ ret = gpiochip_remove(&stmpe_gpio->chip);
	362	+ if (ret < 0) {
	363	+ dev_err(stmpe_gpio->dev,
	364	+ "unable to remove gpiochip: %d\n", ret);
	365	+ return ret;
	366	+ }
	367	+
	368	+ stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	369	+
	370	+ free_irq(irq, stmpe_gpio);
	371	+ stmpe_gpio_irq_remove(stmpe_gpio);
	372	+ platform_set_drvdata(pdev, NULL);
	373	+ kfree(stmpe_gpio);
	374	+
	375	+ return 0;
	376	+}
	377	+
	378	+static struct platform_driver stmpe_gpio_driver = {
	379	+ .driver.name = "stmpe-gpio",
	380	+ .driver.owner = THIS_MODULE,
	381	+ .probe = stmpe_gpio_probe,
	382	+ .remove = __devexit_p(stmpe_gpio_remove),
	383	+};
	384	+
	385	+static int __init stmpe_gpio_init(void)
	386	+{
	387	+ return platform_driver_register(&stmpe_gpio_driver);
	388	+}
	389	+subsys_initcall(stmpe_gpio_init);
	390	+
	391	+static void __exit stmpe_gpio_exit(void)
	392	+{
	393	+ platform_driver_unregister(&stmpe_gpio_driver);
	394	+}
	395	+module_exit(stmpe_gpio_exit);
	396	+
	397	+MODULE_LICENSE("GPL v2");
	398	+MODULE_DESCRIPTION("STMPExxxx GPIO driver");
	399	+MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");