Commit 0f2a3e7288e91d42f9a527f193b1df61d5afff5c
1 parent
a62dbd7027
Exists in
v3.2_SMARCT335xPSP_04.06.00.11
and in
3 other branches
input: ti_tsc: Configure TSC to use FIFO 0 only
The MFD device has 2 fifo's FIFO0 and FIFO1. Previously these FIFO's were shared between touchscreen and ADC. This led to a situation were in while using TSC, ADC interrupts were also getting generated. Ideally this should not be the condition. Hence TSC now has been updated to use FIFO 0 only to store touchscreen samples. By this we can even make sure that data between the clients is not lost and corrupted. Signed-off-by: Patil, Rachna <rachna@ti.com>
Showing 1 changed file with 26 additions and 18 deletions Side-by-side Diff
drivers/input/touchscreen/ti_tsc.c
... | ... | @@ -92,7 +92,7 @@ |
92 | 92 | |
93 | 93 | stepconfigy = TSCADC_STEPCONFIG_MODE_HWSYNC | |
94 | 94 | TSCADC_STEPCONFIG_AVG_16 | TSCADC_STEPCONFIG_YNN | |
95 | - TSCADC_STEPCONFIG_INM_ADCREFM | TSCADC_STEPCONFIG_FIFO1; | |
95 | + TSCADC_STEPCONFIG_INM_ADCREFM; | |
96 | 96 | switch (ts_dev->wires) { |
97 | 97 | case 4: |
98 | 98 | stepconfigy |= TSCADC_STEPCONFIG_YPP; |
... | ... | @@ -123,8 +123,7 @@ |
123 | 123 | stepconfigz1 = TSCADC_STEPCONFIG_MODE_HWSYNC | |
124 | 124 | TSCADC_STEPCONFIG_AVG_16 | TSCADC_STEPCONFIG_XNP | |
125 | 125 | TSCADC_STEPCONFIG_YPN | TSCADC_STEPCONFIG_INM_ADCREFM; |
126 | - stepconfigz2 = stepconfigz1 | TSCADC_STEPCONFIG_INP_AN3 | | |
127 | - TSCADC_STEPCONFIG_FIFO1; | |
126 | + stepconfigz2 = stepconfigz1 | TSCADC_STEPCONFIG_INP_AN3; | |
128 | 127 | tscadc_writel(ts_dev, TSCADC_REG_STEPCONFIG(total_steps + 1), |
129 | 128 | stepconfigz1); |
130 | 129 | tscadc_writel(ts_dev, TSCADC_REG_STEPDELAY(total_steps + 1), delay); |
... | ... | @@ -132,7 +131,17 @@ |
132 | 131 | stepconfigz2); |
133 | 132 | tscadc_writel(ts_dev, TSCADC_REG_STEPDELAY(total_steps + 2), delay); |
134 | 133 | |
135 | - tscadc_writel(ts_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TC); | |
134 | + /* | |
135 | + * ts_dev->steps_to_config holds the number of steps to used to | |
136 | + * read X/Y samples. Hence Multiply by 2, to account for both | |
137 | + * X and Y samples. | |
138 | + * Add 3 to account for pressure values being read. | |
139 | + * Subtract 1 because in the Step enable register the last bit is | |
140 | + * used to set the charge bit. | |
141 | + */ | |
142 | + tscadc_writel(ts_dev, TSCADC_REG_SE, tscadc_readl | |
143 | + (ts_dev, TSCADC_REG_SE) | | |
144 | + ((1 << ((ts_dev->steps_to_config * 2) + 3)) - 1)); | |
136 | 145 | } |
137 | 146 | |
138 | 147 | static irqreturn_t tscadc_interrupt(int irq, void *dev) |
... | ... | @@ -141,7 +150,7 @@ |
141 | 150 | struct input_dev *input_dev = ts_dev->input; |
142 | 151 | unsigned int status, irqclr = 0; |
143 | 152 | int i; |
144 | - int fsm = 0, fifo0count = 0, fifo1count = 0; | |
153 | + int fsm = 0, fifo0count = 0; | |
145 | 154 | unsigned int readx1 = 0, ready1 = 0; |
146 | 155 | unsigned int prev_val_x = ~0, prev_val_y = ~0; |
147 | 156 | unsigned int prev_diff_x = ~0, prev_diff_y = ~0; |
... | ... | @@ -164,9 +173,7 @@ |
164 | 173 | (status & TSCADC_IRQENB_FIFO1UNDRFLW)) |
165 | 174 | return IRQ_NONE; |
166 | 175 | else if (status & TSCADC_IRQENB_FIFO0THRES) { |
167 | - fifo0count = tscadc_readl(ts_dev, TSCADC_REG_FIFO0CNT); | |
168 | - fifo1count = tscadc_readl(ts_dev, TSCADC_REG_FIFO1CNT); | |
169 | - for (i = 0; i < (fifo0count-1); i++) { | |
176 | + for (i = 0; i < ts_dev->steps_to_config; i++) { | |
170 | 177 | readx1 = tscadc_readl(ts_dev, TSCADC_REG_FIFO0); |
171 | 178 | channel = readx1 & 0xf0000; |
172 | 179 | channel = channel >> 0x10; |
... | ... | @@ -184,8 +191,9 @@ |
184 | 191 | } |
185 | 192 | prev_val_x = readx1; |
186 | 193 | } |
187 | - | |
188 | - ready1 = tscadc_readl(ts_dev, TSCADC_REG_FIFO1); | |
194 | + } | |
195 | + for (i = 0; i < ts_dev->steps_to_config; i++) { | |
196 | + ready1 = tscadc_readl(ts_dev, TSCADC_REG_FIFO0); | |
189 | 197 | channel = ready1 & 0xf0000; |
190 | 198 | channel = channel >> 0x10; |
191 | 199 | if ((channel >= ts_dev->steps_to_config) && |
192 | 200 | |
... | ... | @@ -215,12 +223,8 @@ |
215 | 223 | bckup_y = val_y; |
216 | 224 | |
217 | 225 | z1 = ((tscadc_readl(ts_dev, TSCADC_REG_FIFO0)) & 0xfff); |
218 | - z2 = ((tscadc_readl(ts_dev, TSCADC_REG_FIFO1)) & 0xfff); | |
226 | + z2 = ((tscadc_readl(ts_dev, TSCADC_REG_FIFO0)) & 0xfff); | |
219 | 227 | |
220 | - fifo1count = tscadc_readl(ts_dev, TSCADC_REG_FIFO1CNT); | |
221 | - for (i = 0; i < fifo1count; i++) | |
222 | - tscadc_readl(ts_dev, TSCADC_REG_FIFO1); | |
223 | - | |
224 | 228 | fifo0count = tscadc_readl(ts_dev, TSCADC_REG_FIFO0CNT); |
225 | 229 | for (i = 0; i < fifo0count; i++) |
226 | 230 | tscadc_readl(ts_dev, TSCADC_REG_FIFO0); |
... | ... | @@ -282,7 +286,9 @@ |
282 | 286 | |
283 | 287 | tscadc_writel(ts_dev, TSCADC_REG_IRQSTATUS, (status | irqclr)); |
284 | 288 | |
285 | - tscadc_writel(ts_dev, TSCADC_REG_SE, TSCADC_STPENB_STEPENB_TC); | |
289 | + tscadc_writel(ts_dev, TSCADC_REG_SE, | |
290 | + tscadc_readl(ts_dev, TSCADC_REG_SE) | | |
291 | + ((1 << ((ts_dev->steps_to_config * 2) + 3)) - 1)); | |
286 | 292 | return IRQ_HANDLED; |
287 | 293 | } |
288 | 294 | |
... | ... | @@ -341,7 +347,8 @@ |
341 | 347 | |
342 | 348 | tsc_step_config(ts_dev); |
343 | 349 | |
344 | - tscadc_writel(ts_dev, TSCADC_REG_FIFO0THR, ts_dev->steps_to_config); | |
350 | + tscadc_writel(ts_dev, TSCADC_REG_FIFO0THR, | |
351 | + ts_dev->steps_to_config * 2 + 1); | |
345 | 352 | |
346 | 353 | input_dev->name = "ti-tsc"; |
347 | 354 | input_dev->dev.parent = &pdev->dev; |
348 | 355 | |
... | ... | @@ -413,8 +420,9 @@ |
413 | 420 | TSCADC_IRQENB_HW_PEN); |
414 | 421 | } |
415 | 422 | tsc_step_config(ts_dev); |
423 | + /* Configure to value minus 1 */ | |
416 | 424 | tscadc_writel(ts_dev, TSCADC_REG_FIFO0THR, |
417 | - ts_dev->steps_to_config); | |
425 | + ts_dev->steps_to_config * 2 + 1); | |
418 | 426 | return 0; |
419 | 427 | } |
420 | 428 |