Commit 0fea95207dc62c0ff3a347e383fc8b0cf1fa84dc

Authored by Afzal Mohammed
1 parent 255f801cdc
Exists in master

arm:omap:am33xx: Update common OMAP machine specific sources

This patch updates the common machine specific source files for
support for AM33XX/AM335x with cpu type, macros for identification of
AM33XX/AM335X device.

Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>

Showing 11 changed files with 110 additions and 6 deletions Side-by-side Diff

arch/arm/mach-omap2/clock3xxx_data.c
... ... @@ -3517,6 +3517,9 @@
3517 3517 } else if (cpu_is_ti816x()) {
3518 3518 cpu_mask = RATE_IN_TI816X;
3519 3519 cpu_clkflg = CK_TI816X;
  3520 + } else if (cpu_is_am33xx()) {
  3521 + cpu_mask = RATE_IN_AM33XX;
  3522 + cpu_clkflg = CK_AM33XX;
3520 3523 } else if (cpu_is_omap34xx()) {
3521 3524 if (omap_rev() == OMAP3430_REV_ES1_0) {
3522 3525 cpu_mask = RATE_IN_3430ES1;
... ... @@ -3600,7 +3603,8 @@
3600 3603 * Lock DPLL5 -- here only until other device init code can
3601 3604 * handle this
3602 3605 */
3603   - if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
  3606 + if (!cpu_is_ti816x() && !cpu_is_am33xx() &&
  3607 + (omap_rev() >= OMAP3430_REV_ES2_0))
3604 3608 omap3_clk_lock_dpll5();
3605 3609  
3606 3610 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
arch/arm/mach-omap2/common.c
... ... @@ -128,6 +128,22 @@
128 128 {
129 129 __omap2_set_globals(&ti816x_globals);
130 130 }
  131 +
  132 +#define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + \
  133 + TI816X_CONTROL_DEVICE_ID - 0x204)
  134 +
  135 +static struct omap_globals am33xx_globals = {
  136 + .class = AM335X_CLASS,
  137 + .tap = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
  138 + .ctrl = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
  139 + .prm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
  140 + .cm = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
  141 +};
  142 +
  143 +void __init omap2_set_globals_am33xx(void)
  144 +{
  145 + __omap2_set_globals(&am33xx_globals);
  146 +}
131 147 #endif
132 148  
133 149 #if defined(CONFIG_ARCH_OMAP4)
arch/arm/mach-omap2/id.c
... ... @@ -337,6 +337,10 @@
337 337 break;
338 338 }
339 339 break;
  340 + case 0xb944:
  341 + omap_revision = AM335X_REV_ES1_0;
  342 + *cpu_rev = "1.0";
  343 + break;
340 344 default:
341 345 /* Unknown default to latest silicon rev as default */
342 346 omap_revision = OMAP3630_REV_ES1_2;
... ... @@ -429,6 +433,8 @@
429 433 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
430 434 } else if (cpu_is_ti816x()) {
431 435 cpu_name = "TI816X";
  436 + } else if (cpu_is_am335x()) {
  437 + cpu_name = "AM335X";
432 438 } else if (omap3_has_iva() && omap3_has_sgx()) {
433 439 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
434 440 cpu_name = "OMAP3430/3530";
... ... @@ -469,8 +475,8 @@
469 475 } else if (cpu_is_omap34xx()) {
470 476 omap3_check_revision(&cpu_rev);
471 477  
472   - /* TI816X doesn't have feature register */
473   - if (!cpu_is_ti816x())
  478 + /* TI816X/AM335X doesn't have feature register */
  479 + if (!cpu_is_ti816x() && !cpu_is_am33xx())
474 480 omap3_check_features();
475 481 else
476 482 ti816x_check_features();
arch/arm/mach-omap2/io.c
... ... @@ -184,7 +184,24 @@
184 184 .pfn = __phys_to_pfn(L4_34XX_PHYS),
185 185 .length = L4_34XX_SIZE,
186 186 .type = MT_DEVICE
  187 + }
  188 +};
  189 +#endif
  190 +
  191 +#ifdef CONFIG_SOC_OMAPAM33XX
  192 +static struct map_desc omapam33xx_io_desc[] __initdata = {
  193 + {
  194 + .virtual = L4_34XX_VIRT,
  195 + .pfn = __phys_to_pfn(L4_34XX_PHYS),
  196 + .length = L4_34XX_SIZE,
  197 + .type = MT_DEVICE
187 198 },
  199 + {
  200 + .virtual = L4_WK_AM33XX_VIRT,
  201 + .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
  202 + .length = L4_WK_AM33XX_SIZE,
  203 + .type = MT_DEVICE
  204 + }
188 205 };
189 206 #endif
190 207  
... ... @@ -268,6 +285,13 @@
268 285 void __init omapti816x_map_common_io(void)
269 286 {
270 287 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
  288 +}
  289 +#endif
  290 +
  291 +#ifdef CONFIG_SOC_OMAPAM33XX
  292 +void __init omapam33xx_map_common_io(void)
  293 +{
  294 + iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
271 295 }
272 296 #endif
273 297  
arch/arm/mach-omap2/serial.c
... ... @@ -464,7 +464,7 @@
464 464 mod_timer(&uart->timer, jiffies + uart->timeout);
465 465 omap_uart_smart_idle_enable(uart, 0);
466 466  
467   - if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
  467 + if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx())) {
468 468 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
469 469 u32 wk_mask = 0;
470 470 u32 padconf = 0;
... ... @@ -746,7 +746,7 @@
746 746 */
747 747 uart->regshift = p->regshift;
748 748 uart->membase = p->membase;
749   - if (cpu_is_omap44xx() || cpu_is_ti816x())
  749 + if (cpu_is_omap44xx() || cpu_is_ti816x() || cpu_is_am33xx())
750 750 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
751 751 else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
752 752 >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
... ... @@ -828,7 +828,7 @@
828 828 }
829 829  
830 830 /* Enable the MDR1 errata for OMAP3 */
831   - if (cpu_is_omap34xx() && !cpu_is_ti816x())
  831 + if (cpu_is_omap34xx() && !(cpu_is_ti816x() || cpu_is_am33xx()))
832 832 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
833 833 }
834 834  
arch/arm/plat-omap/include/plat/am33xx.h
  1 +/*
  2 + * This file contains the address info for various AM33XX modules.
  3 + *
  4 + * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation version 2.
  9 + *
  10 + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11 + * kind, whether express or implied; without even the implied warranty
  12 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + */
  15 +
  16 +#ifndef __ASM_ARCH_AM33XX_H
  17 +#define __ASM_ARCH_AM33XX_H
  18 +
  19 +#define L4_SLOW_AM33XX_BASE 0x48000000
  20 +
  21 +#define AM33XX_SCM_BASE 0x44E10000
  22 +#define AM33XX_CTRL_BASE AM33XX_SCM_BASE
  23 +#define AM33XX_PRCM_BASE 0x44E00000
  24 +
  25 +#endif /* __ASM_ARCH_AM33XX_H */
arch/arm/plat-omap/include/plat/common.h
... ... @@ -79,6 +79,7 @@
79 79 void omap2_set_globals_3xxx(void);
80 80 void omap2_set_globals_443x(void);
81 81 void omap2_set_globals_ti816x(void);
  82 +void omap2_set_globals_am33xx(void);
82 83  
83 84 /* These get called from omap2_set_globals_xxxx(), do not call these */
84 85 void omap2_set_globals_tap(struct omap_globals *);
arch/arm/plat-omap/include/plat/hardware.h
... ... @@ -287,6 +287,7 @@
287 287 #include <plat/omap34xx.h>
288 288 #include <plat/omap44xx.h>
289 289 #include <plat/ti816x.h>
  290 +#include <plat/am33xx.h>
290 291  
291 292 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */
arch/arm/plat-omap/include/plat/io.h
... ... @@ -73,6 +73,9 @@
73 73 #define OMAP4_L3_IO_OFFSET 0xb4000000
74 74 #define OMAP4_L3_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
75 75  
  76 +#define AM33XX_L4_WK_IO_OFFSET 0xb5000000
  77 +#define AM33XX_L4_WK_IO_ADDRESS(pa) IOMEM((pa) + AM33XX_L4_WK_IO_OFFSET)
  78 +
76 79 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
77 80 #define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
78 81  
... ... @@ -154,6 +157,15 @@
154 157 #define L4_34XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
155 158  
156 159 /*
  160 + * ----------------------------------------------------------------------------
  161 + * AM33XX specific IO mapping
  162 + * ----------------------------------------------------------------------------
  163 + */
  164 +#define L4_WK_AM33XX_PHYS L4_WK_AM33XX_BASE
  165 +#define L4_WK_AM33XX_VIRT (L4_WK_AM33XX_PHYS + AM33XX_L4_WK_IO_OFFSET)
  166 +#define L4_WK_AM33XX_SIZE SZ_4M /* 1MB of 128MB used, want 1MB sect */
  167 +
  168 +/*
157 169 * Need to look at the Size 4M for L4.
158 170 * VPOM3430 was not working for Int controller
159 171 */
... ... @@ -312,6 +324,14 @@
312 324 extern void omapti816x_map_common_io(void);
313 325 #else
314 326 static inline void omapti816x_map_common_io(void)
  327 +{
  328 +}
  329 +#endif
  330 +
  331 +#ifdef CONFIG_SOC_OMAPAM33XX
  332 +extern void omapam33xx_map_common_io(void);
  333 +#else
  334 +static inline void omapam33xx_map_common_io(void)
315 335 {
316 336 }
317 337 #endif
arch/arm/plat-omap/include/plat/omap34xx.h
... ... @@ -35,6 +35,8 @@
35 35 #define L4_EMU_34XX_BASE 0x54000000
36 36 #define L3_34XX_BASE 0x68000000
37 37  
  38 +#define L4_WK_AM33XX_BASE 0x44C00000
  39 +
38 40 #define OMAP3430_32KSYNCT_BASE 0x48320000
39 41 #define OMAP3430_CM_BASE 0x48004800
40 42 #define OMAP3430_PRM_BASE 0x48306800
arch/arm/plat-omap/io.c
... ... @@ -93,6 +93,11 @@
93 93 if (cpu_is_ti816x()) {
94 94 if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
95 95 return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
  96 + } else if (cpu_is_am33xx()) {
  97 + if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
  98 + return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
  99 + if (BETWEEN(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_SIZE))
  100 + return XLATE(p, L4_WK_AM33XX_PHYS, L4_WK_AM33XX_VIRT);
96 101 } else if (cpu_is_omap34xx()) {
97 102 if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
98 103 return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);