Eric Lee / linux-smarc-t335x-v3.2

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Commit 178dd0cd28168287a0be6444a7eef8918b6c544e

Authored by Paul Mundt
1 parent 47aa8f493f
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

sh: Add support for SH7723 CPU subtype. 

This adds basic support for the SH7723 MobileR2 CPU.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 10 changed files with 389 additions and 32 deletions Side-by-side Diff

... ... @@ -276,6 +276,15 @@
276 276  
277 277 # SH-4A Processor Support
278 278  
  279 +config CPU_SUBTYPE_SH7723
  280 + bool "Support SH7723 processor"
  281 + select CPU_SH4A
  282 + select CPU_SHX2
  283 + select ARCH_SPARSEMEM_ENABLE
  284 + select SYS_SUPPORTS_NUMA
  285 + help
  286 + Select SH7723 if you have an SH-MobileR2 CPU.
  287 +
279 288 config CPU_SUBTYPE_SH7763
280 289 bool "Support SH7763 processor"
281 290 select CPU_SH4A
... ... @@ -600,7 +609,7 @@
600 609 default "27000000" if CPU_SUBTYPE_SH7343
601 610 default "31250000" if CPU_SUBTYPE_SH7619
602 611 default "32000000" if CPU_SUBTYPE_SH7722
603   - default "33333333" if CPU_SUBTYPE_SH7770 || \
  612 + default "33333333" if CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7723 || \
604 613 CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
605 614 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
606 615 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG
arch/sh/kernel/cpu/sh4/probe.c
Diff comments   View file @ 178dd0c
... ... @@ -126,17 +126,22 @@
126 126 CPU_HAS_LLSC;
127 127 break;
128 128 case 0x3008:
129   - if (prr == 0xa0 || prr == 0xa1) {
130   - boot_cpu_data.type = CPU_SH7722;
131   - boot_cpu_data.icache.ways = 4;
132   - boot_cpu_data.dcache.ways = 4;
133   - boot_cpu_data.flags |= CPU_HAS_LLSC;
134   - }
135   - else if (prr == 0x70) {
  129 + boot_cpu_data.icache.ways = 4;
  130 + boot_cpu_data.dcache.ways = 4;
  131 + boot_cpu_data.flags |= CPU_HAS_LLSC;
  132 +
  133 + switch (prr) {
  134 + case 0x50:
  135 + boot_cpu_data.type = CPU_SH7723;
  136 + boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
  137 + break;
  138 + case 0x70:
136 139 boot_cpu_data.type = CPU_SH7366;
137   - boot_cpu_data.icache.ways = 4;
138   - boot_cpu_data.dcache.ways = 4;
139   - boot_cpu_data.flags |= CPU_HAS_LLSC;
  140 + break;
  141 + case 0xa0:
  142 + case 0xa1:
  143 + boot_cpu_data.type = CPU_SH7722;
  144 + break;
140 145 }
141 146 break;
142 147 case 0x4000: /* 1st cut */
arch/sh/kernel/cpu/sh4a/Makefile
Diff comments   View file @ 178dd0c
... ... @@ -9,6 +9,7 @@
9 9 obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
10 10 obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
11 11 obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
  12 +obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
12 13 obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
13 14 obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
14 15  
... ... @@ -22,6 +23,7 @@
22 23 clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
23 24 clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
24 25 clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
  26 +clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
25 27 clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
26 28 clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
27 29  
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
Diff comments   View file @ 178dd0c
  1 +/*
  2 + * SH7723 Setup
  3 + *
  4 + * Copyright (C) 2008 Paul Mundt
  5 + *
  6 + * This file is subject to the terms and conditions of the GNU General Public
  7 + * License. See the file "COPYING" in the main directory of this archive
  8 + * for more details.
  9 + */
  10 +#include <linux/platform_device.h>
  11 +#include <linux/init.h>
  12 +#include <linux/serial.h>
  13 +#include <linux/mm.h>
  14 +#include <linux/serial_sci.h>
  15 +#include <asm/mmzone.h>
  16 +
  17 +static struct plat_sci_port sci_platform_data[] = {
  18 + {
  19 + .mapbase = 0xa4e30000,
  20 + .flags = UPF_BOOT_AUTOCONF,
  21 + .type = PORT_SCI,
  22 + .irqs = { 56, 56, 56, 56 },
  23 + },{
  24 + .mapbase = 0xa4e40000,
  25 + .flags = UPF_BOOT_AUTOCONF,
  26 + .type = PORT_SCI,
  27 + .irqs = { 88, 88, 88, 88 },
  28 + },{
  29 + .mapbase = 0xa4e50000,
  30 + .flags = UPF_BOOT_AUTOCONF,
  31 + .type = PORT_SCI,
  32 + .irqs = { 109, 109, 109, 109 },
  33 + }, {
  34 + .flags = 0,
  35 + }
  36 +};
  37 +
  38 +static struct platform_device sci_device = {
  39 + .name = "sh-sci",
  40 + .id = -1,
  41 + .dev = {
  42 + .platform_data = sci_platform_data,
  43 + },
  44 +};
  45 +
  46 +static struct resource rtc_resources[] = {
  47 + [0] = {
  48 + .start = 0xa465fec0,
  49 + .end = 0xa465fec0 + 0x58 - 1,
  50 + .flags = IORESOURCE_IO,
  51 + },
  52 + [1] = {
  53 + /* Period IRQ */
  54 + .start = 69,
  55 + .flags = IORESOURCE_IRQ,
  56 + },
  57 + [2] = {
  58 + /* Carry IRQ */
  59 + .start = 70,
  60 + .flags = IORESOURCE_IRQ,
  61 + },
  62 + [3] = {
  63 + /* Alarm IRQ */
  64 + .start = 68,
  65 + .flags = IORESOURCE_IRQ,
  66 + },
  67 +};
  68 +
  69 +static struct platform_device rtc_device = {
  70 + .name = "sh-rtc",
  71 + .id = -1,
  72 + .num_resources = ARRAY_SIZE(rtc_resources),
  73 + .resource = rtc_resources,
  74 +};
  75 +
  76 +static struct platform_device *sh7723_devices[] __initdata = {
  77 + &sci_device,
  78 + &rtc_device,
  79 +};
  80 +
  81 +static int __init sh7723_devices_setup(void)
  82 +{
  83 + return platform_add_devices(sh7723_devices,
  84 + ARRAY_SIZE(sh7723_devices));
  85 +}
  86 +__initcall(sh7723_devices_setup);
  87 +
  88 +enum {
  89 + UNUSED=0,
  90 +
  91 + /* interrupt sources */
  92 + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  93 + HUDI,
  94 + DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
  95 + _2DG_TRI,_2DG_INI,_2DG_CEI,
  96 + DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
  97 + VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
  98 + SCIFA_SCIFA0,
  99 + VPU_VPUI,
  100 + TPU_TPUI,
  101 + ADC_ADI,
  102 + USB_USI0,
  103 + RTC_ATI,RTC_PRI,RTC_CUI,
  104 + DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
  105 + DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
  106 + KEYSC_KEYI,
  107 + SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
  108 + MSIOF_MSIOFI0,MSIOF_MSIOFI1,
  109 + SCIFA_SCIFA1,
  110 + FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
  111 + I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
  112 + SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
  113 + CMT_CMTI,
  114 + TSIF_TSIFI,
  115 + SIU_SIUI,
  116 + SCIFA_SCIFA2,
  117 + TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
  118 + IRDA_IRDAI,
  119 + ATAPI_ATAPII,
  120 + SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
  121 + VEU2H1_VEU2HI,
  122 + LCDC_LCDCI,
  123 + TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
  124 +
  125 + /* interrupt groups */
  126 + DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
  127 + SDHI1, RTC, DMAC1B, SDHI0,
  128 +};
  129 +
  130 +static struct intc_vect vectors[] __initdata = {
  131 + INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
  132 + INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
  133 + INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
  134 + INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
  135 +
  136 + INTC_VECT(DMAC1A_DEI0,0x700),
  137 + INTC_VECT(DMAC1A_DEI1,0x720),
  138 + INTC_VECT(DMAC1A_DEI2,0x740),
  139 + INTC_VECT(DMAC1A_DEI3,0x760),
  140 +
  141 + INTC_VECT(_2DG_TRI, 0x780),
  142 + INTC_VECT(_2DG_INI, 0x7A0),
  143 + INTC_VECT(_2DG_CEI, 0x7C0),
  144 +
  145 + INTC_VECT(DMAC0A_DEI0,0x800),
  146 + INTC_VECT(DMAC0A_DEI1,0x820),
  147 + INTC_VECT(DMAC0A_DEI2,0x840),
  148 + INTC_VECT(DMAC0A_DEI3,0x860),
  149 +
  150 + INTC_VECT(VIO_CEUI,0x880),
  151 + INTC_VECT(VIO_BEUI,0x8A0),
  152 + INTC_VECT(VIO_VEU2HI,0x8C0),
  153 + INTC_VECT(VIO_VOUI,0x8E0),
  154 +
  155 + INTC_VECT(SCIFA_SCIFA0,0x900),
  156 + INTC_VECT(VPU_VPUI,0x920),
  157 + INTC_VECT(TPU_TPUI,0x9A0),
  158 + INTC_VECT(ADC_ADI,0x9E0),
  159 + INTC_VECT(USB_USI0,0xA20),
  160 +
  161 + INTC_VECT(RTC_ATI,0xA80),
  162 + INTC_VECT(RTC_PRI,0xAA0),
  163 + INTC_VECT(RTC_CUI,0xAC0),
  164 +
  165 + INTC_VECT(DMAC1B_DEI4,0xB00),
  166 + INTC_VECT(DMAC1B_DEI5,0xB20),
  167 + INTC_VECT(DMAC1B_DADERR,0xB40),
  168 +
  169 + INTC_VECT(DMAC0B_DEI4,0xB80),
  170 + INTC_VECT(DMAC0B_DEI5,0xBA0),
  171 + INTC_VECT(DMAC0B_DADERR,0xBC0),
  172 +
  173 + INTC_VECT(KEYSC_KEYI,0xBE0),
  174 + INTC_VECT(SCIF_SCIF0,0xC00),
  175 + INTC_VECT(SCIF_SCIF1,0xC20),
  176 + INTC_VECT(SCIF_SCIF2,0xC40),
  177 + INTC_VECT(MSIOF_MSIOFI0,0xC80),
  178 + INTC_VECT(MSIOF_MSIOFI1,0xCA0),
  179 + INTC_VECT(SCIFA_SCIFA1,0xD00),
  180 +
  181 + INTC_VECT(FLCTL_FLSTEI,0xD80),
  182 + INTC_VECT(FLCTL_FLTENDI,0xDA0),
  183 + INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
  184 + INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
  185 +
  186 + INTC_VECT(I2C_ALI,0xE00),
  187 + INTC_VECT(I2C_TACKI,0xE20),
  188 + INTC_VECT(I2C_WAITI,0xE40),
  189 + INTC_VECT(I2C_DTEI,0xE60),
  190 +
  191 + INTC_VECT(SDHI0_SDHII0,0xE80),
  192 + INTC_VECT(SDHI0_SDHII1,0xEA0),
  193 + INTC_VECT(SDHI0_SDHII2,0xEC0),
  194 +
  195 + INTC_VECT(CMT_CMTI,0xF00),
  196 + INTC_VECT(TSIF_TSIFI,0xF20),
  197 + INTC_VECT(SIU_SIUI,0xF80),
  198 + INTC_VECT(SCIFA_SCIFA2,0xFA0),
  199 +
  200 + INTC_VECT(TMU0_TUNI0,0x400),
  201 + INTC_VECT(TMU0_TUNI1,0x420),
  202 + INTC_VECT(TMU0_TUNI2,0x440),
  203 +
  204 + INTC_VECT(IRDA_IRDAI,0x480),
  205 + INTC_VECT(ATAPI_ATAPII,0x4A0),
  206 +
  207 + INTC_VECT(SDHI1_SDHII0,0x4E0),
  208 + INTC_VECT(SDHI1_SDHII1,0x500),
  209 + INTC_VECT(SDHI1_SDHII2,0x520),
  210 +
  211 + INTC_VECT(VEU2H1_VEU2HI,0x560),
  212 + INTC_VECT(LCDC_LCDCI,0x580),
  213 +
  214 + INTC_VECT(TMU1_TUNI0,0x920),
  215 + INTC_VECT(TMU1_TUNI1,0x940),
  216 + INTC_VECT(TMU1_TUNI2,0x960),
  217 +
  218 +};
  219 +
  220 +static struct intc_group groups[] __initdata = {
  221 + INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
  222 + INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
  223 + INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
  224 + INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
  225 + INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
  226 + INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
  227 + INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
  228 + INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
  229 + INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
  230 + INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
  231 + INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
  232 +};
  233 +
  234 +static struct intc_mask_reg mask_registers[] __initdata = {
  235 + { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
  236 + { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
  237 + { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
  238 + { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
  239 + { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
  240 + { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
  241 + { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
  242 + { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
  243 + { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
  244 + { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
  245 + { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
  246 + { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
  247 + { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
  248 + { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
  249 + { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
  250 + { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
  251 + FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
  252 + { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
  253 + { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
  254 + { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
  255 + { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
  256 + { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
  257 + { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
  258 + { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
  259 + { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
  260 + { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
  261 + { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
  262 + { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
  263 + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  264 +};
  265 +
  266 +static struct intc_prio_reg prio_registers[] __initdata = {
  267 + { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
  268 + { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
  269 + { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
  270 + { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
  271 + { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
  272 + { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
  273 + { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
  274 + { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
  275 + { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
  276 + { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
  277 + { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
  278 + { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
  279 + { 0xa4140010, 0, 32, 4, /* INTPRI00 */
  280 + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  281 +};
  282 +
  283 +static struct intc_sense_reg sense_registers[] __initdata = {
  284 + { 0xa414001c, 16, 2, /* ICR1 */
  285 + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
  286 +};
  287 +
  288 +static DECLARE_INTC_DESC(intc_desc, "sh7723", vectors, groups,
  289 + mask_registers, prio_registers, sense_registers);
  290 +
  291 +void __init plat_irq_setup(void)
  292 +{
  293 + register_intc_controller(&intc_desc);
  294 +}
  295 +
  296 +void __init plat_mem_setup(void)
  297 +{
  298 + /* Register the URAM space as Node 1 */
  299 + setup_bootmem_node(1, 0x055f0000, 0x05610000);
  300 +}
arch/sh/kernel/setup.c
Diff comments   View file @ 178dd0c
... ... @@ -335,7 +335,7 @@
335 335 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
336 336 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
337 337 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
338   - [CPU_MXG] = "MX-G",
  338 + [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
339 339 [CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown"
340 340 };
341 341  
drivers/serial/sh-sci.c
Diff comments   View file @ 178dd0c
... ... @@ -333,7 +333,6 @@
333 333 }
334 334 sci_out(port, SCFCR, fcr_val);
335 335 }
336   -
337 336 #elif defined(CONFIG_CPU_SH3)
338 337 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
339 338 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
... ... @@ -383,6 +382,12 @@
383 382 }
384 383  
385 384 sci_out(port, SCFCR, fcr_val);
  385 +}
  386 +#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  387 +static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
  388 +{
  389 + /* Nothing to do here.. */
  390 + sci_out(port, SCFCR, 0);
386 391 }
387 392 #else
388 393 /* For SH7750 */
drivers/serial/sh-sci.h
Diff comments   View file @ 178dd0c
1   -/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2   - *
3   - * linux/drivers/serial/sh-sci.h
4   - *
5   - * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6   - * Copyright (C) 1999, 2000 Niibe Yutaka
7   - * Copyright (C) 2000 Greg Banks
8   - * Copyright (C) 2002, 2003 Paul Mundt
9   - * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10   - * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11   - * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12   - * Removed SH7300 support (Jul 2007).
13   - * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
14   - */
15 1 #include <linux/serial_core.h>
16 2 #include <asm/io.h>
17   -
18 3 #include <asm/gpio.h>
19 4  
20 5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
... ... @@ -102,6 +87,15 @@
102 87 # define SCSPTR0 SCPDR0
103 88 # define SCIF_ORER 0x0001 /* overrun error bit */
104 89 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  90 +#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  91 +# define SCSPTR0 0xa4050160
  92 +# define SCSPTR1 0xa405013e
  93 +# define SCSPTR2 0xa4050160
  94 +# define SCSPTR3 0xa405013e
  95 +# define SCSPTR4 0xa4050128
  96 +# define SCSPTR5 0xa4050128
  97 +# define SCIF_ORER 0x0001 /* overrun error bit */
  98 +# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
105 99 # define SCIF_ONLY
106 100 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
107 101 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
... ... @@ -395,6 +389,11 @@
395 389 h8_sci_offset, h8_sci_size) \
396 390 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
397 391 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
  392 +#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  393 + #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
  394 + CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
  395 + #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
  396 + CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
398 397 #else
399 398 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
400 399 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
... ... @@ -419,6 +418,18 @@
419 418 SCIF_FNS(SCxTDR, 0x20, 8)
420 419 SCIF_FNS(SCxRDR, 0x24, 8)
421 420 SCIF_FNS(SCLSR, 0x24, 16)
  421 +#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  422 +SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
  423 +SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
  424 +SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
  425 +SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
  426 +SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
  427 +SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
  428 +SCIF_FNS(SCTDSR, 0x0c, 8)
  429 +SCIF_FNS(SCFER, 0x10, 16)
  430 +SCIF_FNS(SCFCR, 0x18, 16)
  431 +SCIF_FNS(SCFDR, 0x1c, 16)
  432 +SCIF_FNS(SCLSR, 0x24, 16)
422 433 #else
423 434 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
424 435 /* name off sz off sz off sz off sz off sz*/
... ... @@ -589,6 +600,23 @@
589 600 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
590 601 return 1;
591 602 }
  603 +#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  604 +static inline int sci_rxd_in(struct uart_port *port)
  605 +{
  606 + if (port->mapbase == 0xffe00000)
  607 + return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
  608 + if (port->mapbase == 0xffe10000)
  609 + return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
  610 + if (port->mapbase == 0xffe20000)
  611 + return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
  612 + if (port->mapbase == 0xa4e30000)
  613 + return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
  614 + if (port->mapbase == 0xa4e40000)
  615 + return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
  616 + if (port->mapbase == 0xa4e50000)
  617 + return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
  618 + return 1;
  619 +}
592 620 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
593 621 static inline int sci_rxd_in(struct uart_port *port)
594 622 {
... ... @@ -727,6 +755,8 @@
727 755 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
728 756 defined(CONFIG_CPU_SUBTYPE_SH7721)
729 757 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
  758 +#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  759 +#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
730 760 #elif defined(__H8300H__) || defined(__H8300S__)
731 761 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
732 762 #elif defined(CONFIG_SUPERH64)
include/asm-sh/cpu-sh4/freq.h
Diff comments   View file @ 178dd0c
... ... @@ -10,14 +10,14 @@
10 10 #ifndef __ASM_CPU_SH4_FREQ_H
11 11 #define __ASM_CPU_SH4_FREQ_H
12 12  
13   -#if defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366)
  13 +#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
  14 + defined(CONFIG_CPU_SUBTYPE_SH7723) || \
  15 + defined(CONFIG_CPU_SUBTYPE_SH7366)
14 16 #define FRQCR 0xa4150000
15 17 #define VCLKCR 0xa4150004
16 18 #define SCLKACR 0xa4150008
17 19 #define SCLKBCR 0xa415000c
18   -#if defined(CONFIG_CPU_SUBTYPE_SH7722)
19 20 #define IrDACLKCR 0xa4150010
20   -#endif
21 21 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
22 22 defined(CONFIG_CPU_SUBTYPE_SH7780)
23 23 #define FRQCR 0xffc80000
include/asm-sh/cpu-sh4/rtc.h
Diff comments   View file @ 178dd0c
1 1 #ifndef __ASM_SH_CPU_SH4_RTC_H
2 2 #define __ASM_SH_CPU_SH4_RTC_H
3 3  
  4 +#ifdef CONFIG_CPU_SUBTYPE_SH7723
  5 +#define rtc_reg_size sizeof(u16)
  6 +#else
4 7 #define rtc_reg_size sizeof(u32)
  8 +#endif
  9 +
5 10 #define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
6 11 #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
7 12  
include/asm-sh/processor.h
Diff comments   View file @ 178dd0c
... ... @@ -29,7 +29,8 @@
29 29 CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
30 30  
31 31 /* SH-4A types */
32   - CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
  32 + CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
  33 + CPU_SH7723, CPU_SHX3,
33 34  
34 35 /* SH4AL-DSP types */
35 36 CPU_SH7343, CPU_SH7722, CPU_SH7366,