Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel…

…/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: hwspinlock: depend on OMAP4 ARM: OMAP2+: Fix warnings for GPMC interrupt OMAP4: PandaBoard: remove unused power regulators arm: mach-omap2: omap_l3_smx: fix irq handler setup arm: mach-omap2: devices: fix omap3_l3_init() return value

Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel…
…/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: hwspinlock: depend on OMAP4 ARM: OMAP2+: Fix warnings for GPMC interrupt OMAP4: PandaBoard: remove unused power regulators arm: mach-omap2: omap_l3_smx: fix irq handler setup arm: mach-omap2: devices: fix omap3_l3_init() return value
Linus Torvalds
2 parents 34c27a497a 4fa8eebb04
Showing 6 changed files Side-by-side Diff
arch/arm/mach-omap2/board-omap4panda.c
arch/arm/mach-omap2/devices.c
arch/arm/mach-omap2/gpmc.c
arch/arm/mach-omap2/omap_l3_smx.c
arch/arm/plat-omap/include/plat/irqs.h
drivers/hwspinlock/Kconfig
@@ -285,19 +285,6 @@
 	return 0;
 }
  
-static struct regulator_init_data omap4_panda_vaux1 = {
-	.constraints = {
-		.min_uV			= 1000000,
-		.max_uV			= 3000000,
-		.apply_uV		= true,
-		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-					| REGULATOR_MODE_STANDBY,
-		.valid_ops_mask	 = REGULATOR_CHANGE_VOLTAGE
-					| REGULATOR_CHANGE_MODE
-					| REGULATOR_CHANGE_STATUS,
-	},
-};
-
 static struct regulator_init_data omap4_panda_vaux2 = {
 	.constraints = {
 		.min_uV			= 1200000,
@@ -353,19 +340,6 @@
 	},
 };
  
-static struct regulator_init_data omap4_panda_vusim = {
-	.constraints = {
-		.min_uV			= 1200000,
-		.max_uV			= 2900000,
-		.apply_uV		= true,
-		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-					| REGULATOR_MODE_STANDBY,
-		.valid_ops_mask	 = REGULATOR_CHANGE_VOLTAGE
-					| REGULATOR_CHANGE_MODE
-					| REGULATOR_CHANGE_STATUS,
-	},
-};
-
 static struct regulator_init_data omap4_panda_vana = {
 	.constraints = {
 		.min_uV			= 2100000,
  
@@ -424,12 +398,10 @@
 	/* Regulators */
 	.vmmc		= &omap4_panda_vmmc,
 	.vpp		= &omap4_panda_vpp,
-	.vusim		= &omap4_panda_vusim,
 	.vana		= &omap4_panda_vana,
 	.vcxio		= &omap4_panda_vcxio,
 	.vdac		= &omap4_panda_vdac,
 	.vusb		= &omap4_panda_vusb,
-	.vaux1		= &omap4_panda_vaux1,
 	.vaux2		= &omap4_panda_vaux2,
 	.vaux3		= &omap4_panda_vaux3,
 	.clk32kg	= &omap4_panda_clk32kg,
@@ -66,7 +66,7 @@
  
 	WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
  
-	return PTR_ERR(od);
+	return IS_ERR(od) ? PTR_ERR(od) : 0;
 }
 postcore_initcall(omap3_l3_init);
  
@@ -693,6 +693,7 @@
 {
 	u32 l, irq;
 	int cs, ret = -EINVAL;
+	int gpmc_irq;
 	char *ck = NULL;
  
 	if (cpu_is_omap24xx()) {
  
  
@@ -701,12 +702,15 @@
 			l = OMAP2420_GPMC_BASE;
 		else
 			l = OMAP34XX_GPMC_BASE;
+		gpmc_irq = INT_34XX_GPMC_IRQ;
 	} else if (cpu_is_omap34xx()) {
 		ck = "gpmc_fck";
 		l = OMAP34XX_GPMC_BASE;
+		gpmc_irq = INT_34XX_GPMC_IRQ;
 	} else if (cpu_is_omap44xx()) {
 		ck = "gpmc_ck";
 		l = OMAP44XX_GPMC_BASE;
+		gpmc_irq = OMAP44XX_IRQ_GPMC;
 	}
  
 	if (WARN_ON(!ck))
  
  
@@ -739,16 +743,17 @@
 	/* initalize the irq_chained */
 	irq = OMAP_GPMC_IRQ_BASE;
 	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-		set_irq_handler(irq, handle_simple_irq);
+		set_irq_chip_and_handler(irq, &dummy_irq_chip,
+						handle_simple_irq);
 		set_irq_flags(irq, IRQF_VALID);
 		irq++;
 	}
  
-	ret = request_irq(INT_34XX_GPMC_IRQ,
+	ret = request_irq(gpmc_irq,
 			gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
 	if (ret)
 		pr_err("gpmc: irq-%d could not claim: err %d\n",
-						INT_34XX_GPMC_IRQ, ret);
+						gpmc_irq, ret);
 	return ret;
 }
 postcore_initcall(gpmc_init);
@@ -757,8 +762,6 @@
 {
 	u8 cs;
  
-	if (irq != INT_34XX_GPMC_IRQ)
-		return IRQ_HANDLED;
 	/* check cs to invoke the irq */
 	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
 	if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
@@ -226,7 +226,6 @@
 	struct omap3_l3         *l3;
 	struct resource         *res;
 	int                     ret;
-	int                     irq;
  
 	l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
 	if (!l3) {
  
  
@@ -249,18 +248,17 @@
 		goto err2;
 	}
  
-	irq = platform_get_irq(pdev, 0);
-	ret = request_irq(irq, omap3_l3_app_irq,
+	l3->debug_irq = platform_get_irq(pdev, 0);
+	ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
 		IRQF_DISABLED | IRQF_TRIGGER_RISING,
 		"l3-debug-irq", l3);
 	if (ret) {
 		dev_err(&pdev->dev, "couldn't request debug irq\n");
 		goto err3;
 	}
-	l3->debug_irq = irq;
  
-	irq = platform_get_irq(pdev, 1);
-	ret = request_irq(irq, omap3_l3_app_irq,
+	l3->app_irq = platform_get_irq(pdev, 1);
+	ret = request_irq(l3->app_irq, omap3_l3_app_irq,
 		IRQF_DISABLED | IRQF_TRIGGER_RISING,
 		"l3-app-irq", l3);
  
@@ -269,7 +267,6 @@
 		goto err4;
 	}
  
-	l3->app_irq = irq;
 	goto err0;
  
 err4:
@@ -416,7 +416,7 @@
  
 /* GPMC related */
 #define OMAP_GPMC_IRQ_BASE	(TWL_IRQ_END)
-#define OMAP_GPMC_NR_IRQS	7
+#define OMAP_GPMC_NR_IRQS	8
 #define OMAP_GPMC_IRQ_END	(OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
  
  
@@ -4,6 +4,7 @@
  
 config HWSPINLOCK
 	tristate "Generic Hardware Spinlock framework"
+	depends on ARCH_OMAP4
 	help
 	  Say y here to support the generic hardware spinlock framework.
 	  You only need to enable this if you have hardware spinlock module
...	...	@@ -285,19 +285,6 @@
285	285	return 0;
286	286	}
287	287
288		-static struct regulator_init_data omap4_panda_vaux1 = {
289		- .constraints = {
290		- .min_uV = 1000000,
291		- .max_uV = 3000000,
292		- .apply_uV = true,
293		- .valid_modes_mask = REGULATOR_MODE_NORMAL
294		- \| REGULATOR_MODE_STANDBY,
295		- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
296		- \| REGULATOR_CHANGE_MODE
297		- \| REGULATOR_CHANGE_STATUS,
298		- },
299		-};
300		-
301	288	static struct regulator_init_data omap4_panda_vaux2 = {
302	289	.constraints = {
303	290	.min_uV = 1200000,
...	...	@@ -353,19 +340,6 @@
353	340	},
354	341	};
355	342
356		-static struct regulator_init_data omap4_panda_vusim = {
357		- .constraints = {
358		- .min_uV = 1200000,
359		- .max_uV = 2900000,
360		- .apply_uV = true,
361		- .valid_modes_mask = REGULATOR_MODE_NORMAL
362		- \| REGULATOR_MODE_STANDBY,
363		- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
364		- \| REGULATOR_CHANGE_MODE
365		- \| REGULATOR_CHANGE_STATUS,
366		- },
367		-};
368		-
369	343	static struct regulator_init_data omap4_panda_vana = {
370	344	.constraints = {
371	345	.min_uV = 2100000,
372	346
...	...	@@ -424,12 +398,10 @@
424	398	/* Regulators */
425	399	.vmmc = &omap4_panda_vmmc,
426	400	.vpp = &omap4_panda_vpp,
427		- .vusim = &omap4_panda_vusim,
428	401	.vana = &omap4_panda_vana,
429	402	.vcxio = &omap4_panda_vcxio,
430	403	.vdac = &omap4_panda_vdac,
431	404	.vusb = &omap4_panda_vusb,
432		- .vaux1 = &omap4_panda_vaux1,
433	405	.vaux2 = &omap4_panda_vaux2,
434	406	.vaux3 = &omap4_panda_vaux3,
435	407	.clk32kg = &omap4_panda_clk32kg,
...	...	@@ -66,7 +66,7 @@
66	66
67	67	WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
68	68
69		- return PTR_ERR(od);
	69	+ return IS_ERR(od) ? PTR_ERR(od) : 0;
70	70	}
71	71	postcore_initcall(omap3_l3_init);
72	72
...	...	@@ -693,6 +693,7 @@
693	693	{
694	694	u32 l, irq;
695	695	int cs, ret = -EINVAL;
	696	+ int gpmc_irq;
696	697	char *ck = NULL;
697	698
698	699	if (cpu_is_omap24xx()) {
699	700
700	701
...	...	@@ -701,12 +702,15 @@
701	702	l = OMAP2420_GPMC_BASE;
702	703	else
703	704	l = OMAP34XX_GPMC_BASE;
	705	+ gpmc_irq = INT_34XX_GPMC_IRQ;
704	706	} else if (cpu_is_omap34xx()) {
705	707	ck = "gpmc_fck";
706	708	l = OMAP34XX_GPMC_BASE;
	709	+ gpmc_irq = INT_34XX_GPMC_IRQ;
707	710	} else if (cpu_is_omap44xx()) {
708	711	ck = "gpmc_ck";
709	712	l = OMAP44XX_GPMC_BASE;
	713	+ gpmc_irq = OMAP44XX_IRQ_GPMC;
710	714	}
711	715
712	716	if (WARN_ON(!ck))
713	717
714	718
...	...	@@ -739,16 +743,17 @@
739	743	/* initalize the irq_chained */
740	744	irq = OMAP_GPMC_IRQ_BASE;
741	745	for (cs = 0; cs < GPMC_CS_NUM; cs++) {
742		- set_irq_handler(irq, handle_simple_irq);
	746	+ set_irq_chip_and_handler(irq, &dummy_irq_chip,
	747	+ handle_simple_irq);
743	748	set_irq_flags(irq, IRQF_VALID);
744	749	irq++;
745	750	}
746	751
747		- ret = request_irq(INT_34XX_GPMC_IRQ,
	752	+ ret = request_irq(gpmc_irq,
748	753	gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
749	754	if (ret)
750	755	pr_err("gpmc: irq-%d could not claim: err %d\n",
751		- INT_34XX_GPMC_IRQ, ret);
	756	+ gpmc_irq, ret);
752	757	return ret;
753	758	}
754	759	postcore_initcall(gpmc_init);
...	...	@@ -757,8 +762,6 @@
757	762	{
758	763	u8 cs;
759	764
760		- if (irq != INT_34XX_GPMC_IRQ)
761		- return IRQ_HANDLED;
762	765	/* check cs to invoke the irq */
763	766	cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
764	767	if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
...	...	@@ -226,7 +226,6 @@
226	226	struct omap3_l3 *l3;
227	227	struct resource *res;
228	228	int ret;
229		- int irq;
230	229
231	230	l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
232	231	if (!l3) {
233	232
234	233
...	...	@@ -249,18 +248,17 @@
249	248	goto err2;
250	249	}
251	250
252		- irq = platform_get_irq(pdev, 0);
253		- ret = request_irq(irq, omap3_l3_app_irq,
	251	+ l3->debug_irq = platform_get_irq(pdev, 0);
	252	+ ret = request_irq(l3->debug_irq, omap3_l3_app_irq,
254	253	IRQF_DISABLED \| IRQF_TRIGGER_RISING,
255	254	"l3-debug-irq", l3);
256	255	if (ret) {
257	256	dev_err(&pdev->dev, "couldn't request debug irq\n");
258	257	goto err3;
259	258	}
260		- l3->debug_irq = irq;
261	259
262		- irq = platform_get_irq(pdev, 1);
263		- ret = request_irq(irq, omap3_l3_app_irq,
	260	+ l3->app_irq = platform_get_irq(pdev, 1);
	261	+ ret = request_irq(l3->app_irq, omap3_l3_app_irq,
264	262	IRQF_DISABLED \| IRQF_TRIGGER_RISING,
265	263	"l3-app-irq", l3);
266	264
...	...	@@ -269,7 +267,6 @@
269	267	goto err4;
270	268	}
271	269
272		- l3->app_irq = irq;
273	270	goto err0;
274	271
275	272	err4:
...	...	@@ -416,7 +416,7 @@
416	416
417	417	/* GPMC related */
418	418	#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END)
419		-#define OMAP_GPMC_NR_IRQS 7
	419	+#define OMAP_GPMC_NR_IRQS 8
420	420	#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
421	421
422	422
...	...	@@ -4,6 +4,7 @@
4	4
5	5	config HWSPINLOCK
6	6	tristate "Generic Hardware Spinlock framework"
	7	+ depends on ARCH_OMAP4
7	8	help
8	9	Say y here to support the generic hardware spinlock framework.
9	10	You only need to enable this if you have hardware spinlock module