Eric Lee / linux-smarc-t335x-v3.2

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Commit 1b9169d8a0fe2b41fbbb8d152c8108190865f3cf

Authored by Marek Vasut
Committed by Eric Miao
1 parent e60f137b71
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

ARM: pxa: Update Balloon3 for new FPGA firmware 

The new FPGA firmware in Balloon3 uses different methods to control it's bus
control lines. In the new version, there are separate registers to set/clear
bus control lines. This patch updates affected places.

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>

Showing 3 changed files with 36 additions and 28 deletions Side-by-side Diff

arch/arm/mach-pxa/balloon3.c
Diff comments   View file @ 1b9169d
... ... @@ -567,27 +567,29 @@
567 567 * NAND
568 568 ******************************************************************************/
569 569 #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
570   -static uint16_t balloon3_ctl =
571   - BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
572   - BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
573   - BALLOON3_NAND_CONTROL_FLWP;
574   -
575 570 static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
576 571 {
577 572 struct nand_chip *this = mtd->priv;
  573 + uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0;
578 574  
579 575 if (ctrl & NAND_CTRL_CHANGE) {
580 576 if (ctrl & NAND_CLE)
581   - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE;
  577 + balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE;
582 578 else
583   - balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE;
  579 + balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE;
584 580  
585 581 if (ctrl & NAND_ALE)
586   - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE;
  582 + balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE;
587 583 else
588   - balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE;
  584 + balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE;
589 585  
590   - __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
  586 + if (balloon3_ctl_clr)
  587 + __raw_writel(balloon3_ctl_clr,
  588 + BALLOON3_NAND_CONTROL_REG);
  589 + if (balloon3_ctl_set)
  590 + __raw_writel(balloon3_ctl_set,
  591 + BALLOON3_NAND_CONTROL_REG |
  592 + BALLOON3_FPGA_SETnCLR);
591 593 }
592 594  
593 595 if (cmd != NAND_CMD_NONE)
594 596  
... ... @@ -599,15 +601,15 @@
599 601 if (chip < 0 || chip > 3)
600 602 return;
601 603  
602   - balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 |
603   - BALLOON3_NAND_CONTROL_FLCE1 |
604   - BALLOON3_NAND_CONTROL_FLCE2 |
605   - BALLOON3_NAND_CONTROL_FLCE3;
  604 + /* Assert all nCE lines */
  605 + __raw_writew(
  606 + BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
  607 + BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
  608 + BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
606 609  
607 610 /* Deassert correct nCE line */
608   - balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip);
609   -
610   - __raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
  611 + __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
  612 + BALLOON3_NAND_CONTROL_REG);
611 613 }
612 614  
613 615 static int balloon3_nand_probe(struct platform_device *pdev)
614 616  
... ... @@ -616,11 +618,12 @@
616 618 uint16_t ver;
617 619 int ret;
618 620  
619   - __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG);
  621 + __raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
  622 + BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR);
620 623  
621 624 ver = __raw_readw(BALLOON3_FPGA_VER);
622   - if (ver > 0x0201)
623   - pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. "
  625 + if (ver < 0x4f08)
  626 + pr_warn("The FPGA code, version 0x%04x, is too old. "
624 627 "NAND support might be broken in this version!", ver);
625 628  
626 629 /* Power up the NAND chips */
... ... @@ -635,7 +638,11 @@
635 638 gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1);
636 639  
637 640 /* Deassert all nCE lines and write protect line */
638   - __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
  641 + __raw_writel(
  642 + BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
  643 + BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
  644 + BALLOON3_NAND_CONTROL_FLWP,
  645 + BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
639 646 return 0;
640 647  
641 648 err2:
arch/arm/mach-pxa/include/mach/balloon3.h
Diff comments   View file @ 1b9169d
... ... @@ -26,6 +26,8 @@
26 26 #define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */
27 27 #define BALLOON3_FPGA_LENGTH 0x01000000
28 28  
  29 +#define BALLOON3_FPGA_SETnCLR (0x1000)
  30 +
29 31 /* FPGA / CPLD registers for CF socket */
30 32 #define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
31 33 #define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
drivers/pcmcia/pxa2xx_balloon3.c
Diff comments   View file @ 1b9169d
... ... @@ -39,12 +39,10 @@
39 39 static int balloon3_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
40 40 {
41 41 uint16_t ver;
42   - int ret;
43   - static void __iomem *fpga_ver;
44 42  
45 43 ver = __raw_readw(BALLOON3_FPGA_VER);
46   - if (ver > 0x0201)
47   - pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. "
  44 + if (ver < 0x4f08)
  45 + pr_warn("The FPGA code, version 0x%04x, is too old. "
48 46 "PCMCIA/CF support might be broken in this version!",
49 47 ver);
50 48  
... ... @@ -97,8 +95,9 @@
97 95 static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
98 96 const socket_state_t *state)
99 97 {
100   - __raw_writew((state->flags & SS_RESET) ? BALLOON3_CF_RESET : 0,
101   - BALLOON3_CF_CONTROL_REG);
  98 + __raw_writew(BALLOON3_CF_RESET, BALLOON3_CF_CONTROL_REG |
  99 + ((state->flags & SS_RESET) ?
  100 + BALLOON3_FPGA_SETnCLR : 0));
102 101 return 0;
103 102 }
104 103