OMAP3+: VC: abstract out channel configuration

VC channel configuration is programmed based on settings coming from the PMIC configuration. Currently, the VC channel to PMIC mapping is a simple one-to-one mapping. Whenever a VC channel parameter is configured (i2c slave addres, PMIC register address, on/ret/off command), the corresponding bits are enabled in the VC channel configuration register. If necessary, the programmability of channel configuration settings could be extended to board/PMIC files, however, because this patch changes the channel configuration to be programmed based on existing values from the PMIC settings, it may not be required. Also note that starting with OMAP4, where there are more than 2 channels, one channel is identified as the "default" channel. When any of the bits in the channel config for the other channels are zero, it means to use the default channel. The OMAP4 TRM (at least through NDA version Q) is wrong in describing which is the default channel. The default channel on OMAP4 is MPU, not CORE as decribed in the TRM. Signed-off-by: Kevin Hilman <khilman@ti.com>

OMAP3+: VC: abstract out channel configuration
VC channel configuration is programmed based on settings coming from the PMIC configuration. Currently, the VC channel to PMIC mapping is a simple one-to-one mapping. Whenever a VC channel parameter is configured (i2c slave addres, PMIC register address, on/ret/off command), the corresponding bits are enabled in the VC channel configuration register. If necessary, the programmability of channel configuration settings could be extended to board/PMIC files, however, because this patch changes the channel configuration to be programmed based on existing values from the PMIC settings, it may not be required. Also note that starting with OMAP4, where there are more than 2 channels, one channel is identified as the "default" channel. When any of the bits in the channel config for the other channels are zero, it means to use the default channel. The OMAP4 TRM (at least through NDA version Q) is wrong in describing which is the default channel. The default channel on OMAP4 is MPU, not CORE as decribed in the TRM. Signed-off-by: Kevin Hilman <khilman@ti.com>
Kevin Hilman
1 parent 08d1c9a3e2
Showing 4 changed files with 74 additions and 12 deletions Side-by-side Diff
arch/arm/mach-omap2/vc.c
arch/arm/mach-omap2/vc.h
arch/arm/mach-omap2/vc3xxx_data.c
arch/arm/mach-omap2/vc44xx_data.c
@@ -19,6 +19,52 @@
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
  
+/*
+ * Channel configuration bits, common for OMAP3 & 4
+ * OMAP3 register: PRM_VC_CH_CONF
+ * OMAP4 register: PRM_VC_CFG_CHANNEL
+ */
+#define CFG_CHANNEL_SA    BIT(0)
+#define CFG_CHANNEL_RAV   BIT(1)
+#define CFG_CHANNEL_RAC   BIT(2)
+#define CFG_CHANNEL_RACEN BIT(3)
+#define CFG_CHANNEL_CMD   BIT(4)
+#define CFG_CHANNEL_MASK 0x3f
+
+/**
+ * omap_vc_config_channel - configure VC channel to PMIC mappings
+ * @voltdm: pointer to voltagdomain defining the desired VC channel
+ *
+ * Configures the VC channel to PMIC mappings for the following
+ * PMIC settings
+ * - i2c slave address (SA)
+ * - voltage configuration address (RAV)
+ * - command configuration address (RAC) and enable bit (RACEN)
+ * - command values for ON, ONLP, RET and OFF (CMD)
+ *
+ * This function currently only allows flexible configuration of the
+ * non-default channel.  Starting with OMAP4, there are more than 2
+ * channels, with one defined as the default (on OMAP4, it's MPU.)
+ * Only the non-default channel can be configured.
+ */
+static int omap_vc_config_channel(struct voltagedomain *voltdm)
+{
+	struct omap_vc_channel *vc = voltdm->vc;
+
+	/*
+	 * For default channel, the only configurable bit is RACEN.
+	 * All others must stay at zero (see function comment above.)
+	 */
+	if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
+		vc->cfg_channel &= CFG_CHANNEL_RACEN;
+
+	voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
+		    vc->cfg_channel << vc->cfg_channel_sa_shift,
+		    vc->common->cfg_channel_reg);
+
+	return 0;
+}
+
 /* Voltage scale and accessory APIs */
 int omap_vc_pre_scale(struct voltagedomain *voltdm,
 		      unsigned long target_volt,
@@ -166,8 +212,6 @@
 	 * Generic VC parameters init
 	 * XXX This data should be abstracted out
 	 */
-	voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK,
-		       OMAP3_PRM_VC_CH_CONF_OFFSET);
 	voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
 		       OMAP3_PRM_VC_I2C_CFG_OFFSET);
  
@@ -186,15 +230,6 @@
 	if (is_initialized)
 		return;
  
-	/*
-	 * Generic VC parameters init
-	 * XXX This data should be abstracted out
-	 */
-	vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
-		  OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
-		  OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
-	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
-
 	/* XXX These are magic numbers and do not belong! */
 	vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
 	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
@@ -222,6 +257,8 @@
 		return;
 	}
  
+	vc->cfg_channel = 0;
+
 	/* get PMIC/board specific settings */
 	vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
 	vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
@@ -232,6 +269,7 @@
 	voltdm->rmw(vc->smps_sa_mask,
 		    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
 		    vc->common->smps_sa_reg);
+	vc->cfg_channel |= CFG_CHANNEL_SA;
  
 	/*
 	 * Configure the PMIC register addresses.
  
@@ -239,10 +277,14 @@
 	voltdm->rmw(vc->smps_volra_mask,
 		    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
 		    vc->common->smps_volra_reg);
-	if (vc->cmd_reg_addr)
+	vc->cfg_channel |= CFG_CHANNEL_RAV;
+
+	if (vc->cmd_reg_addr) {
 		voltdm->rmw(vc->smps_cmdra_mask,
 			    vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
 			    vc->common->smps_cmdra_reg);
+		vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
+	}
  
 	/* Set up the on, inactive, retention and off voltage */
 	on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
@@ -254,6 +296,10 @@
 	       (ret_vsel << vc->common->cmd_ret_shift) |
 	       (off_vsel << vc->common->cmd_off_shift));
 	voltdm->write(val, vc->cmdval_reg);
+	vc->cfg_channel |= CFG_CHANNEL_CMD;
+
+	/* Channel configuration */
+	omap_vc_config_channel(voltdm);
  
 	/* Configure the setup times */
 	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
@@ -54,8 +54,12 @@
 	u8 cmd_onlp_shift;
 	u8 cmd_ret_shift;
 	u8 cmd_off_shift;
+	u8 cfg_channel_reg;
 };
  
+/* omap_vc_channel.flags values */
+#define OMAP_VC_CHANNEL_DEFAULT BIT(0)
+
 /**
  * struct omap_vc_channel - VC per-instance data
  * @i2c_slave_addr: I2C slave address of PMIC for this VC channel
@@ -67,6 +71,7 @@
  * @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
  * @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
  * @cmdval_reg: register for on/ret/off voltage level values for this channel
+ * @flags: VC channel-specific flags (optional)
  */
 struct omap_vc_channel {
 	/* channel state */
@@ -74,6 +79,7 @@
 	u16 volt_reg_addr;
 	u16 cmd_reg_addr;
 	u16 setup_time;
+	u8 cfg_channel;
  
 	/* register access data */
 	const struct omap_vc_common *common;
@@ -81,6 +87,8 @@
 	u32 smps_volra_mask;
 	u32 smps_cmdra_mask;
 	u8 cmdval_reg;
+	u8 cfg_channel_sa_shift;
+	u8 flags;
 };
  
 extern struct omap_vc_channel omap3_vc_mpu;
@@ -43,6 +43,7 @@
 	.cmd_onlp_shift	 = OMAP3430_VC_CMD_ONLP_SHIFT,
 	.cmd_ret_shift	 = OMAP3430_VC_CMD_RET_SHIFT,
 	.cmd_off_shift	 = OMAP3430_VC_CMD_OFF_SHIFT,
+	.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
 };
  
 struct omap_vc_channel omap3_vc_mpu = {
@@ -51,6 +52,7 @@
 	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
 	.smps_volra_mask = OMAP3430_VOLRA0_MASK,
 	.smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
+	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
 };
  
 struct omap_vc_channel omap3_vc_core = {
@@ -59,5 +61,6 @@
 	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
 	.smps_volra_mask = OMAP3430_VOLRA1_MASK,
 	.smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
+	.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
 };
@@ -44,15 +44,18 @@
 	.cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
 	.cmd_ret_shift = OMAP4430_RET_SHIFT,
 	.cmd_off_shift = OMAP4430_OFF_SHIFT,
+	.cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
 };
  
 /* VC instance data for each controllable voltage line */
 struct omap_vc_channel omap4_vc_mpu = {
+	.flags = OMAP_VC_CHANNEL_DEFAULT,
 	.common = &omap4_vc_common,
 	.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
 	.smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
 	.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
 	.smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
+	.cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT,
 };
  
 struct omap_vc_channel omap4_vc_iva = {
@@ -61,6 +64,7 @@
 	.smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
 	.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
 	.smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
+	.cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT,
 };
  
 struct omap_vc_channel omap4_vc_core = {
@@ -69,5 +73,6 @@
 	.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
 	.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
 	.smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
+	.cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
 };
...	...	@@ -19,6 +19,52 @@
19	19	#include "prm-regbits-44xx.h"
20	20	#include "prm44xx.h"
21	21
	22	+/*
	23	+ * Channel configuration bits, common for OMAP3 & 4
	24	+ * OMAP3 register: PRM_VC_CH_CONF
	25	+ * OMAP4 register: PRM_VC_CFG_CHANNEL
	26	+ */
	27	+#define CFG_CHANNEL_SA BIT(0)
	28	+#define CFG_CHANNEL_RAV BIT(1)
	29	+#define CFG_CHANNEL_RAC BIT(2)
	30	+#define CFG_CHANNEL_RACEN BIT(3)
	31	+#define CFG_CHANNEL_CMD BIT(4)
	32	+#define CFG_CHANNEL_MASK 0x3f
	33	+
	34	+/**
	35	+ * omap_vc_config_channel - configure VC channel to PMIC mappings
	36	+ * @voltdm: pointer to voltagdomain defining the desired VC channel
	37	+ *
	38	+ * Configures the VC channel to PMIC mappings for the following
	39	+ * PMIC settings
	40	+ * - i2c slave address (SA)
	41	+ * - voltage configuration address (RAV)
	42	+ * - command configuration address (RAC) and enable bit (RACEN)
	43	+ * - command values for ON, ONLP, RET and OFF (CMD)
	44	+ *
	45	+ * This function currently only allows flexible configuration of the
	46	+ * non-default channel. Starting with OMAP4, there are more than 2
	47	+ * channels, with one defined as the default (on OMAP4, it's MPU.)
	48	+ * Only the non-default channel can be configured.
	49	+ */
	50	+static int omap_vc_config_channel(struct voltagedomain *voltdm)
	51	+{
	52	+ struct omap_vc_channel *vc = voltdm->vc;
	53	+
	54	+ /*
	55	+ * For default channel, the only configurable bit is RACEN.
	56	+ * All others must stay at zero (see function comment above.)
	57	+ */
	58	+ if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
	59	+ vc->cfg_channel &= CFG_CHANNEL_RACEN;
	60	+
	61	+ voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
	62	+ vc->cfg_channel << vc->cfg_channel_sa_shift,
	63	+ vc->common->cfg_channel_reg);
	64	+
	65	+ return 0;
	66	+}
	67	+
22	68	/* Voltage scale and accessory APIs */
23	69	int omap_vc_pre_scale(struct voltagedomain *voltdm,
24	70	unsigned long target_volt,
...	...	@@ -166,8 +212,6 @@
166	212	* Generic VC parameters init
167	213	* XXX This data should be abstracted out
168	214	*/
169		- voltdm->write(OMAP3430_CMD1_MASK \| OMAP3430_RAV1_MASK,
170		- OMAP3_PRM_VC_CH_CONF_OFFSET);
171	215	voltdm->write(OMAP3430_MCODE_SHIFT \| OMAP3430_HSEN_MASK,
172	216	OMAP3_PRM_VC_I2C_CFG_OFFSET);
173	217
...	...	@@ -186,15 +230,6 @@
186	230	if (is_initialized)
187	231	return;
188	232
189		- /*
190		- * Generic VC parameters init
191		- * XXX This data should be abstracted out
192		- */
193		- vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK \| OMAP4430_CMD_VDD_MPU_L_MASK \|
194		- OMAP4430_RAV_VDD_IVA_L_MASK \| OMAP4430_CMD_VDD_IVA_L_MASK \|
195		- OMAP4430_RAV_VDD_CORE_L_MASK \| OMAP4430_CMD_VDD_CORE_L_MASK);
196		- voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
197		-
198	233	/* XXX These are magic numbers and do not belong! */
199	234	vc_val = (0x60 << OMAP4430_SCLL_SHIFT \| 0x26 << OMAP4430_SCLH_SHIFT);
200	235	voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
...	...	@@ -222,6 +257,8 @@
222	257	return;
223	258	}
224	259
	260	+ vc->cfg_channel = 0;
	261	+
225	262	/* get PMIC/board specific settings */
226	263	vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
227	264	vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
...	...	@@ -232,6 +269,7 @@
232	269	voltdm->rmw(vc->smps_sa_mask,
233	270	vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
234	271	vc->common->smps_sa_reg);
	272	+ vc->cfg_channel \|= CFG_CHANNEL_SA;
235	273
236	274	/*
237	275	* Configure the PMIC register addresses.
238	276
...	...	@@ -239,10 +277,14 @@
239	277	voltdm->rmw(vc->smps_volra_mask,
240	278	vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
241	279	vc->common->smps_volra_reg);
242		- if (vc->cmd_reg_addr)
	280	+ vc->cfg_channel \|= CFG_CHANNEL_RAV;
	281	+
	282	+ if (vc->cmd_reg_addr) {
243	283	voltdm->rmw(vc->smps_cmdra_mask,
244	284	vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
245	285	vc->common->smps_cmdra_reg);
	286	+ vc->cfg_channel \|= CFG_CHANNEL_RAC \| CFG_CHANNEL_RACEN;
	287	+ }
246	288
247	289	/* Set up the on, inactive, retention and off voltage */
248	290	on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
...	...	@@ -254,6 +296,10 @@
254	296	(ret_vsel << vc->common->cmd_ret_shift) \|
255	297	(off_vsel << vc->common->cmd_off_shift));
256	298	voltdm->write(val, vc->cmdval_reg);
	299	+ vc->cfg_channel \|= CFG_CHANNEL_CMD;
	300	+
	301	+ /* Channel configuration */
	302	+ omap_vc_config_channel(voltdm);
257	303
258	304	/* Configure the setup times */
259	305	voltdm->rmw(voltdm->vfsm->voltsetup_mask,
...	...	@@ -54,8 +54,12 @@
54	54	u8 cmd_onlp_shift;
55	55	u8 cmd_ret_shift;
56	56	u8 cmd_off_shift;
	57	+ u8 cfg_channel_reg;
57	58	};
58	59
	60	+/* omap_vc_channel.flags values */
	61	+#define OMAP_VC_CHANNEL_DEFAULT BIT(0)
	62	+
59	63	/**
60	64	* struct omap_vc_channel - VC per-instance data
61	65	* @i2c_slave_addr: I2C slave address of PMIC for this VC channel
...	...	@@ -67,6 +71,7 @@
67	71	* @smps_volra_mask: VOLRA* bitmask in the PRM_VC_VOL_RA register
68	72	* @smps_cmdra_mask: CMDRA* bitmask in the PRM_VC_CMD_RA register
69	73	* @cmdval_reg: register for on/ret/off voltage level values for this channel
	74	+ * @flags: VC channel-specific flags (optional)
70	75	*/
71	76	struct omap_vc_channel {
72	77	/* channel state */
...	...	@@ -74,6 +79,7 @@
74	79	u16 volt_reg_addr;
75	80	u16 cmd_reg_addr;
76	81	u16 setup_time;
	82	+ u8 cfg_channel;
77	83
78	84	/* register access data */
79	85	const struct omap_vc_common *common;
...	...	@@ -81,6 +87,8 @@
81	87	u32 smps_volra_mask;
82	88	u32 smps_cmdra_mask;
83	89	u8 cmdval_reg;
	90	+ u8 cfg_channel_sa_shift;
	91	+ u8 flags;
84	92	};
85	93
86	94	extern struct omap_vc_channel omap3_vc_mpu;
...	...	@@ -43,6 +43,7 @@
43	43	.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
44	44	.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
45	45	.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
	46	+ .cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
46	47	};
47	48
48	49	struct omap_vc_channel omap3_vc_mpu = {
...	...	@@ -51,6 +52,7 @@
51	52	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
52	53	.smps_volra_mask = OMAP3430_VOLRA0_MASK,
53	54	.smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
	55	+ .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
54	56	};
55	57
56	58	struct omap_vc_channel omap3_vc_core = {
...	...	@@ -59,5 +61,6 @@
59	61	.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
60	62	.smps_volra_mask = OMAP3430_VOLRA1_MASK,
61	63	.smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
	64	+ .cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
62	65	};
...	...	@@ -44,15 +44,18 @@
44	44	.cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
45	45	.cmd_ret_shift = OMAP4430_RET_SHIFT,
46	46	.cmd_off_shift = OMAP4430_OFF_SHIFT,
	47	+ .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
47	48	};
48	49
49	50	/* VC instance data for each controllable voltage line */
50	51	struct omap_vc_channel omap4_vc_mpu = {
	52	+ .flags = OMAP_VC_CHANNEL_DEFAULT,
51	53	.common = &omap4_vc_common,
52	54	.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
53	55	.smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
54	56	.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
55	57	.smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
	58	+ .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT,
56	59	};
57	60
58	61	struct omap_vc_channel omap4_vc_iva = {
...	...	@@ -61,6 +64,7 @@
61	64	.smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
62	65	.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
63	66	.smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
	67	+ .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT,
64	68	};
65	69
66	70	struct omap_vc_channel omap4_vc_core = {
...	...	@@ -69,5 +73,6 @@
69	73	.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
70	74	.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
71	75	.smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
	76	+ .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
72	77	};