Commit 27e5c5a9a240d2a7790bfe31045020a043c5d74a
1 parent
9f7b218713
Exists in
master
and in
4 other branches
m32r: Convert genirq namespace
Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Showing 8 changed files with 75 additions and 75 deletions Side-by-side Diff
arch/m32r/platforms/m32104ut/setup.c
... | ... | @@ -76,7 +76,7 @@ |
76 | 76 | |
77 | 77 | #if defined(CONFIG_SMC91X) |
78 | 78 | /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ |
79 | - set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, | |
79 | + irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, | |
80 | 80 | handle_level_irq); |
81 | 81 | /* "H" level sense */ |
82 | 82 | cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; |
83 | 83 | |
84 | 84 | |
... | ... | @@ -84,20 +84,20 @@ |
84 | 84 | #endif /* CONFIG_SMC91X */ |
85 | 85 | |
86 | 86 | /* MFT2 : system timer */ |
87 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, | |
87 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, | |
88 | 88 | handle_level_irq); |
89 | 89 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
90 | 90 | disable_m32104ut_irq(M32R_IRQ_MFT2); |
91 | 91 | |
92 | 92 | #ifdef CONFIG_SERIAL_M32R_SIO |
93 | 93 | /* SIO0_R : uart receive data */ |
94 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, | |
94 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, | |
95 | 95 | handle_level_irq); |
96 | 96 | icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; |
97 | 97 | disable_m32104ut_irq(M32R_IRQ_SIO0_R); |
98 | 98 | |
99 | 99 | /* SIO0_S : uart send data */ |
100 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, | |
100 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, | |
101 | 101 | handle_level_irq); |
102 | 102 | icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; |
103 | 103 | disable_m32104ut_irq(M32R_IRQ_SIO0_S); |
arch/m32r/platforms/m32700ut/setup.c
... | ... | @@ -259,76 +259,76 @@ |
259 | 259 | { |
260 | 260 | #if defined(CONFIG_SMC91X) |
261 | 261 | /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ |
262 | - set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN, | |
262 | + irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN, | |
263 | 263 | &m32700ut_lanpld_irq_type, handle_level_irq); |
264 | 264 | lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
265 | 265 | disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); |
266 | 266 | #endif /* CONFIG_SMC91X */ |
267 | 267 | |
268 | 268 | /* MFT2 : system timer */ |
269 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, | |
269 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, | |
270 | 270 | handle_level_irq); |
271 | 271 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
272 | 272 | disable_m32700ut_irq(M32R_IRQ_MFT2); |
273 | 273 | |
274 | 274 | /* SIO0 : receive */ |
275 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, | |
275 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, | |
276 | 276 | handle_level_irq); |
277 | 277 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
278 | 278 | disable_m32700ut_irq(M32R_IRQ_SIO0_R); |
279 | 279 | |
280 | 280 | /* SIO0 : send */ |
281 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, | |
281 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, | |
282 | 282 | handle_level_irq); |
283 | 283 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
284 | 284 | disable_m32700ut_irq(M32R_IRQ_SIO0_S); |
285 | 285 | |
286 | 286 | /* SIO1 : receive */ |
287 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, | |
287 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, | |
288 | 288 | handle_level_irq); |
289 | 289 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
290 | 290 | disable_m32700ut_irq(M32R_IRQ_SIO1_R); |
291 | 291 | |
292 | 292 | /* SIO1 : send */ |
293 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, | |
293 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, | |
294 | 294 | handle_level_irq); |
295 | 295 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
296 | 296 | disable_m32700ut_irq(M32R_IRQ_SIO1_S); |
297 | 297 | |
298 | 298 | /* DMA1 : */ |
299 | - set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, | |
299 | + irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, | |
300 | 300 | handle_level_irq); |
301 | 301 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
302 | 302 | disable_m32700ut_irq(M32R_IRQ_DMA1); |
303 | 303 | |
304 | 304 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
305 | 305 | /* INT#1: SIO0 Receive on PLD */ |
306 | - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, | |
306 | + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, | |
307 | 307 | handle_level_irq); |
308 | 308 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
309 | 309 | disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); |
310 | 310 | |
311 | 311 | /* INT#1: SIO0 Send on PLD */ |
312 | - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, | |
312 | + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, | |
313 | 313 | handle_level_irq); |
314 | 314 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
315 | 315 | disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); |
316 | 316 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ |
317 | 317 | |
318 | 318 | /* INT#1: CFC IREQ on PLD */ |
319 | - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, | |
319 | + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, | |
320 | 320 | handle_level_irq); |
321 | 321 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
322 | 322 | disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); |
323 | 323 | |
324 | 324 | /* INT#1: CFC Insert on PLD */ |
325 | - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, | |
325 | + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, | |
326 | 326 | handle_level_irq); |
327 | 327 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
328 | 328 | disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); |
329 | 329 | |
330 | 330 | /* INT#1: CFC Eject on PLD */ |
331 | - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, | |
331 | + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, | |
332 | 332 | handle_level_irq); |
333 | 333 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
334 | 334 | disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); |
... | ... | @@ -349,7 +349,7 @@ |
349 | 349 | |
350 | 350 | #if defined(CONFIG_USB) |
351 | 351 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
352 | - set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, | |
352 | + irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, | |
353 | 353 | &m32700ut_lcdpld_irq_type, handle_level_irq); |
354 | 354 | |
355 | 355 | lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
... | ... | @@ -366,7 +366,7 @@ |
366 | 366 | /* |
367 | 367 | * INT3# is used for AR |
368 | 368 | */ |
369 | - set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, | |
369 | + irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, | |
370 | 370 | handle_level_irq); |
371 | 371 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
372 | 372 | disable_m32700ut_irq(M32R_IRQ_INT3); |
arch/m32r/platforms/mappi/setup.c
... | ... | @@ -75,39 +75,39 @@ |
75 | 75 | |
76 | 76 | #ifdef CONFIG_NE2000 |
77 | 77 | /* INT0 : LAN controller (RTL8019AS) */ |
78 | - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, | |
78 | + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, | |
79 | 79 | handle_level_irq); |
80 | 80 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; |
81 | 81 | disable_mappi_irq(M32R_IRQ_INT0); |
82 | 82 | #endif /* CONFIG_M32R_NE2000 */ |
83 | 83 | |
84 | 84 | /* MFT2 : system timer */ |
85 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, | |
85 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, | |
86 | 86 | handle_level_irq); |
87 | 87 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
88 | 88 | disable_mappi_irq(M32R_IRQ_MFT2); |
89 | 89 | |
90 | 90 | #ifdef CONFIG_SERIAL_M32R_SIO |
91 | 91 | /* SIO0_R : uart receive data */ |
92 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, | |
92 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, | |
93 | 93 | handle_level_irq); |
94 | 94 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
95 | 95 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
96 | 96 | |
97 | 97 | /* SIO0_S : uart send data */ |
98 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, | |
98 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, | |
99 | 99 | handle_level_irq); |
100 | 100 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
101 | 101 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
102 | 102 | |
103 | 103 | /* SIO1_R : uart receive data */ |
104 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, | |
104 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, | |
105 | 105 | handle_level_irq); |
106 | 106 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
107 | 107 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
108 | 108 | |
109 | 109 | /* SIO1_S : uart send data */ |
110 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, | |
110 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, | |
111 | 111 | handle_level_irq); |
112 | 112 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
113 | 113 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
114 | 114 | |
... | ... | @@ -115,13 +115,13 @@ |
115 | 115 | |
116 | 116 | #if defined(CONFIG_M32R_PCC) |
117 | 117 | /* INT1 : pccard0 interrupt */ |
118 | - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, | |
118 | + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, | |
119 | 119 | handle_level_irq); |
120 | 120 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
121 | 121 | disable_mappi_irq(M32R_IRQ_INT1); |
122 | 122 | |
123 | 123 | /* INT2 : pccard1 interrupt */ |
124 | - set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, | |
124 | + irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, | |
125 | 125 | handle_level_irq); |
126 | 126 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
127 | 127 | disable_mappi_irq(M32R_IRQ_INT2); |
arch/m32r/platforms/mappi2/setup.c
... | ... | @@ -76,38 +76,38 @@ |
76 | 76 | { |
77 | 77 | #if defined(CONFIG_SMC91X) |
78 | 78 | /* INT0 : LAN controller (SMC91111) */ |
79 | - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, | |
79 | + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, | |
80 | 80 | handle_level_irq); |
81 | 81 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
82 | 82 | disable_mappi2_irq(M32R_IRQ_INT0); |
83 | 83 | #endif /* CONFIG_SMC91X */ |
84 | 84 | |
85 | 85 | /* MFT2 : system timer */ |
86 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, | |
86 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, | |
87 | 87 | handle_level_irq); |
88 | 88 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
89 | 89 | disable_mappi2_irq(M32R_IRQ_MFT2); |
90 | 90 | |
91 | 91 | #ifdef CONFIG_SERIAL_M32R_SIO |
92 | 92 | /* SIO0_R : uart receive data */ |
93 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, | |
93 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, | |
94 | 94 | handle_level_irq); |
95 | 95 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
96 | 96 | disable_mappi2_irq(M32R_IRQ_SIO0_R); |
97 | 97 | |
98 | 98 | /* SIO0_S : uart send data */ |
99 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, | |
99 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, | |
100 | 100 | handle_level_irq); |
101 | 101 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
102 | 102 | disable_mappi2_irq(M32R_IRQ_SIO0_S); |
103 | 103 | /* SIO1_R : uart receive data */ |
104 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, | |
104 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, | |
105 | 105 | handle_level_irq); |
106 | 106 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
107 | 107 | disable_mappi2_irq(M32R_IRQ_SIO1_R); |
108 | 108 | |
109 | 109 | /* SIO1_S : uart send data */ |
110 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, | |
110 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, | |
111 | 111 | handle_level_irq); |
112 | 112 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
113 | 113 | disable_mappi2_irq(M32R_IRQ_SIO1_S); |
114 | 114 | |
115 | 115 | |
116 | 116 | |
... | ... | @@ -115,27 +115,27 @@ |
115 | 115 | |
116 | 116 | #if defined(CONFIG_USB) |
117 | 117 | /* INT1 : USB Host controller interrupt */ |
118 | - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, | |
118 | + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, | |
119 | 119 | handle_level_irq); |
120 | 120 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
121 | 121 | disable_mappi2_irq(M32R_IRQ_INT1); |
122 | 122 | #endif /* CONFIG_USB */ |
123 | 123 | |
124 | 124 | /* ICUCR40: CFC IREQ */ |
125 | - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, | |
125 | + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, | |
126 | 126 | handle_level_irq); |
127 | 127 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
128 | 128 | disable_mappi2_irq(PLD_IRQ_CFIREQ); |
129 | 129 | |
130 | 130 | #if defined(CONFIG_M32R_CFC) |
131 | 131 | /* ICUCR41: CFC Insert */ |
132 | - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, | |
132 | + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, | |
133 | 133 | handle_level_irq); |
134 | 134 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
135 | 135 | disable_mappi2_irq(PLD_IRQ_CFC_INSERT); |
136 | 136 | |
137 | 137 | /* ICUCR42: CFC Eject */ |
138 | - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, | |
138 | + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, | |
139 | 139 | handle_level_irq); |
140 | 140 | icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
141 | 141 | disable_mappi2_irq(PLD_IRQ_CFC_EJECT); |
arch/m32r/platforms/mappi3/setup.c
... | ... | @@ -75,38 +75,38 @@ |
75 | 75 | { |
76 | 76 | #if defined(CONFIG_SMC91X) |
77 | 77 | /* INT0 : LAN controller (SMC91111) */ |
78 | - set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, | |
78 | + irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, | |
79 | 79 | handle_level_irq); |
80 | 80 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
81 | 81 | disable_mappi3_irq(M32R_IRQ_INT0); |
82 | 82 | #endif /* CONFIG_SMC91X */ |
83 | 83 | |
84 | 84 | /* MFT2 : system timer */ |
85 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, | |
85 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, | |
86 | 86 | handle_level_irq); |
87 | 87 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
88 | 88 | disable_mappi3_irq(M32R_IRQ_MFT2); |
89 | 89 | |
90 | 90 | #ifdef CONFIG_SERIAL_M32R_SIO |
91 | 91 | /* SIO0_R : uart receive data */ |
92 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, | |
92 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, | |
93 | 93 | handle_level_irq); |
94 | 94 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
95 | 95 | disable_mappi3_irq(M32R_IRQ_SIO0_R); |
96 | 96 | |
97 | 97 | /* SIO0_S : uart send data */ |
98 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, | |
98 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, | |
99 | 99 | handle_level_irq); |
100 | 100 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
101 | 101 | disable_mappi3_irq(M32R_IRQ_SIO0_S); |
102 | 102 | /* SIO1_R : uart receive data */ |
103 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, | |
103 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, | |
104 | 104 | handle_level_irq); |
105 | 105 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
106 | 106 | disable_mappi3_irq(M32R_IRQ_SIO1_R); |
107 | 107 | |
108 | 108 | /* SIO1_S : uart send data */ |
109 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, | |
109 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, | |
110 | 110 | handle_level_irq); |
111 | 111 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
112 | 112 | disable_mappi3_irq(M32R_IRQ_SIO1_S); |
113 | 113 | |
114 | 114 | |
... | ... | @@ -114,21 +114,21 @@ |
114 | 114 | |
115 | 115 | #if defined(CONFIG_USB) |
116 | 116 | /* INT1 : USB Host controller interrupt */ |
117 | - set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, | |
117 | + irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, | |
118 | 118 | handle_level_irq); |
119 | 119 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
120 | 120 | disable_mappi3_irq(M32R_IRQ_INT1); |
121 | 121 | #endif /* CONFIG_USB */ |
122 | 122 | |
123 | 123 | /* CFC IREQ */ |
124 | - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, | |
124 | + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, | |
125 | 125 | handle_level_irq); |
126 | 126 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
127 | 127 | disable_mappi3_irq(PLD_IRQ_CFIREQ); |
128 | 128 | |
129 | 129 | #if defined(CONFIG_M32R_CFC) |
130 | 130 | /* ICUCR41: CFC Insert & eject */ |
131 | - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, | |
131 | + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, | |
132 | 132 | handle_level_irq); |
133 | 133 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
134 | 134 | disable_mappi3_irq(PLD_IRQ_CFC_INSERT); |
... | ... | @@ -136,7 +136,7 @@ |
136 | 136 | #endif /* CONFIG_M32R_CFC */ |
137 | 137 | |
138 | 138 | /* IDE IREQ */ |
139 | - set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, | |
139 | + irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, | |
140 | 140 | handle_level_irq); |
141 | 141 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
142 | 142 | disable_mappi3_irq(PLD_IRQ_IDEIREQ); |
arch/m32r/platforms/oaks32r/setup.c
... | ... | @@ -74,39 +74,39 @@ |
74 | 74 | |
75 | 75 | #ifdef CONFIG_NE2000 |
76 | 76 | /* INT3 : LAN controller (RTL8019AS) */ |
77 | - set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, | |
77 | + irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, | |
78 | 78 | handle_level_irq); |
79 | 79 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
80 | 80 | disable_oaks32r_irq(M32R_IRQ_INT3); |
81 | 81 | #endif /* CONFIG_M32R_NE2000 */ |
82 | 82 | |
83 | 83 | /* MFT2 : system timer */ |
84 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, | |
84 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, | |
85 | 85 | handle_level_irq); |
86 | 86 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
87 | 87 | disable_oaks32r_irq(M32R_IRQ_MFT2); |
88 | 88 | |
89 | 89 | #ifdef CONFIG_SERIAL_M32R_SIO |
90 | 90 | /* SIO0_R : uart receive data */ |
91 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, | |
91 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, | |
92 | 92 | handle_level_irq); |
93 | 93 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
94 | 94 | disable_oaks32r_irq(M32R_IRQ_SIO0_R); |
95 | 95 | |
96 | 96 | /* SIO0_S : uart send data */ |
97 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, | |
97 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, | |
98 | 98 | handle_level_irq); |
99 | 99 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
100 | 100 | disable_oaks32r_irq(M32R_IRQ_SIO0_S); |
101 | 101 | |
102 | 102 | /* SIO1_R : uart receive data */ |
103 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, | |
103 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, | |
104 | 104 | handle_level_irq); |
105 | 105 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
106 | 106 | disable_oaks32r_irq(M32R_IRQ_SIO1_R); |
107 | 107 | |
108 | 108 | /* SIO1_S : uart send data */ |
109 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, | |
109 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, | |
110 | 110 | handle_level_irq); |
111 | 111 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
112 | 112 | disable_oaks32r_irq(M32R_IRQ_SIO1_S); |
arch/m32r/platforms/opsput/setup.c
... | ... | @@ -259,76 +259,76 @@ |
259 | 259 | { |
260 | 260 | #if defined(CONFIG_SMC91X) |
261 | 261 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ |
262 | - set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, | |
262 | + irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, | |
263 | 263 | handle_level_irq); |
264 | 264 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
265 | 265 | disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); |
266 | 266 | #endif /* CONFIG_SMC91X */ |
267 | 267 | |
268 | 268 | /* MFT2 : system timer */ |
269 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, | |
269 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, | |
270 | 270 | handle_level_irq); |
271 | 271 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
272 | 272 | disable_opsput_irq(M32R_IRQ_MFT2); |
273 | 273 | |
274 | 274 | /* SIO0 : receive */ |
275 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, | |
275 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, | |
276 | 276 | handle_level_irq); |
277 | 277 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
278 | 278 | disable_opsput_irq(M32R_IRQ_SIO0_R); |
279 | 279 | |
280 | 280 | /* SIO0 : send */ |
281 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, | |
281 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, | |
282 | 282 | handle_level_irq); |
283 | 283 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
284 | 284 | disable_opsput_irq(M32R_IRQ_SIO0_S); |
285 | 285 | |
286 | 286 | /* SIO1 : receive */ |
287 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, | |
287 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, | |
288 | 288 | handle_level_irq); |
289 | 289 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
290 | 290 | disable_opsput_irq(M32R_IRQ_SIO1_R); |
291 | 291 | |
292 | 292 | /* SIO1 : send */ |
293 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, | |
293 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, | |
294 | 294 | handle_level_irq); |
295 | 295 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
296 | 296 | disable_opsput_irq(M32R_IRQ_SIO1_S); |
297 | 297 | |
298 | 298 | /* DMA1 : */ |
299 | - set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, | |
299 | + irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, | |
300 | 300 | handle_level_irq); |
301 | 301 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
302 | 302 | disable_opsput_irq(M32R_IRQ_DMA1); |
303 | 303 | |
304 | 304 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
305 | 305 | /* INT#1: SIO0 Receive on PLD */ |
306 | - set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, | |
306 | + irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, | |
307 | 307 | handle_level_irq); |
308 | 308 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
309 | 309 | disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); |
310 | 310 | |
311 | 311 | /* INT#1: SIO0 Send on PLD */ |
312 | - set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, | |
312 | + irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, | |
313 | 313 | handle_level_irq); |
314 | 314 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
315 | 315 | disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); |
316 | 316 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ |
317 | 317 | |
318 | 318 | /* INT#1: CFC IREQ on PLD */ |
319 | - set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, | |
319 | + irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, | |
320 | 320 | handle_level_irq); |
321 | 321 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
322 | 322 | disable_opsput_pld_irq(PLD_IRQ_CFIREQ); |
323 | 323 | |
324 | 324 | /* INT#1: CFC Insert on PLD */ |
325 | - set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, | |
325 | + irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, | |
326 | 326 | handle_level_irq); |
327 | 327 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
328 | 328 | disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); |
329 | 329 | |
330 | 330 | /* INT#1: CFC Eject on PLD */ |
331 | - set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, | |
331 | + irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, | |
332 | 332 | handle_level_irq); |
333 | 333 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
334 | 334 | disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); |
... | ... | @@ -349,7 +349,7 @@ |
349 | 349 | |
350 | 350 | #if defined(CONFIG_USB) |
351 | 351 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
352 | - set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, | |
352 | + irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, | |
353 | 353 | &opsput_lcdpld_irq_type, handle_level_irq); |
354 | 354 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
355 | 355 | disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); |
... | ... | @@ -365,7 +365,7 @@ |
365 | 365 | /* |
366 | 366 | * INT3# is used for AR |
367 | 367 | */ |
368 | - set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, | |
368 | + irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, | |
369 | 369 | handle_level_irq); |
370 | 370 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
371 | 371 | disable_opsput_irq(M32R_IRQ_INT3); |
arch/m32r/platforms/usrv/setup.c
... | ... | @@ -138,32 +138,32 @@ |
138 | 138 | once++; |
139 | 139 | |
140 | 140 | /* MFT2 : system timer */ |
141 | - set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, | |
141 | + irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, | |
142 | 142 | handle_level_irq); |
143 | 143 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
144 | 144 | disable_mappi_irq(M32R_IRQ_MFT2); |
145 | 145 | |
146 | 146 | #if defined(CONFIG_SERIAL_M32R_SIO) |
147 | 147 | /* SIO0_R : uart receive data */ |
148 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, | |
148 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, | |
149 | 149 | handle_level_irq); |
150 | 150 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
151 | 151 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
152 | 152 | |
153 | 153 | /* SIO0_S : uart send data */ |
154 | - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, | |
154 | + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, | |
155 | 155 | handle_level_irq); |
156 | 156 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
157 | 157 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
158 | 158 | |
159 | 159 | /* SIO1_R : uart receive data */ |
160 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, | |
160 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, | |
161 | 161 | handle_level_irq); |
162 | 162 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
163 | 163 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
164 | 164 | |
165 | 165 | /* SIO1_S : uart send data */ |
166 | - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, | |
166 | + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, | |
167 | 167 | handle_level_irq); |
168 | 168 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
169 | 169 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
... | ... | @@ -171,7 +171,7 @@ |
171 | 171 | |
172 | 172 | /* INT#67-#71: CFC#0 IREQ on PLD */ |
173 | 173 | for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { |
174 | - set_irq_chip_and_handler(PLD_IRQ_CF0 + i, | |
174 | + irq_set_chip_and_handler(PLD_IRQ_CF0 + i, | |
175 | 175 | &m32700ut_pld_irq_type, |
176 | 176 | handle_level_irq); |
177 | 177 | pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr |
178 | 178 | |
... | ... | @@ -181,14 +181,14 @@ |
181 | 181 | |
182 | 182 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
183 | 183 | /* INT#76: 16552D#0 IREQ on PLD */ |
184 | - set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, | |
184 | + irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, | |
185 | 185 | handle_level_irq); |
186 | 186 | pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr |
187 | 187 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ |
188 | 188 | disable_m32700ut_pld_irq(PLD_IRQ_UART0); |
189 | 189 | |
190 | 190 | /* INT#77: 16552D#1 IREQ on PLD */ |
191 | - set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, | |
191 | + irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, | |
192 | 192 | handle_level_irq); |
193 | 193 | pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr |
194 | 194 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ |
... | ... | @@ -197,7 +197,7 @@ |
197 | 197 | |
198 | 198 | #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) |
199 | 199 | /* INT#80: AK4524 IREQ on PLD */ |
200 | - set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, | |
200 | + irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, | |
201 | 201 | handle_level_irq); |
202 | 202 | pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr |
203 | 203 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ |