Commit 2882b0c63ac6085fd5c18959240b6f7d6ffb8d5b
Committed by
Ralf Baechle
Ralf Baechle
1 parent
9d24bafb0d
Exists in
master
and in
4 other branches
MIPS: Alchemy: get rid of allow_au1k_wait
Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the Alchemy-specific wait code before timer initialization; if the C0 timer must be used for timekeeping the wait function is set to NULL which means no wait implementation is available. As a sideeffect, the 'wait instruction available' output in /proc/cpuinfo now correctly indicates whether 'wait' is usable. Run-tested on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Showing 2 changed files with 14 additions and 14 deletions Side-by-side Diff
arch/mips/alchemy/common/time.c
| ... | ... | @@ -36,14 +36,13 @@ |
| 36 | 36 | #include <linux/interrupt.h> |
| 37 | 37 | #include <linux/spinlock.h> |
| 38 | 38 | |
| 39 | +#include <asm/processor.h> | |
| 39 | 40 | #include <asm/time.h> |
| 40 | 41 | #include <asm/mach-au1x00/au1000.h> |
| 41 | 42 | |
| 42 | 43 | /* 32kHz clock enabled and detected */ |
| 43 | 44 | #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) |
| 44 | 45 | |
| 45 | -extern int allow_au1k_wait; /* default off for CP0 Counter */ | |
| 46 | - | |
| 47 | 46 | static cycle_t au1x_counter1_read(struct clocksource *cs) |
| 48 | 47 | { |
| 49 | 48 | return au_readl(SYS_RTCREAD); |
| 50 | 49 | |
| 51 | 50 | |
| ... | ... | @@ -153,14 +152,18 @@ |
| 153 | 152 | |
| 154 | 153 | printk(KERN_INFO "Alchemy clocksource installed\n"); |
| 155 | 154 | |
| 156 | - /* can now use 'wait' */ | |
| 157 | - allow_au1k_wait = 1; | |
| 158 | 155 | return; |
| 159 | 156 | |
| 160 | 157 | cntr_err: |
| 161 | - /* counters unusable, use C0 counter */ | |
| 158 | + /* | |
| 159 | + * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this | |
| 160 | + * function is called. Because the Alchemy counters are unusable | |
| 161 | + * the C0 timekeeping code is installed and use of the 'wait' | |
| 162 | + * instruction must be prohibited, which is done most easily by | |
| 163 | + * assigning NULL to cpu_wait. | |
| 164 | + */ | |
| 165 | + cpu_wait = NULL; | |
| 162 | 166 | r4k_clockevent_init(); |
| 163 | 167 | init_r4k_clocksource(); |
| 164 | - allow_au1k_wait = 0; | |
| 165 | 168 | } |
arch/mips/kernel/cpu-probe.c
| ... | ... | @@ -91,16 +91,13 @@ |
| 91 | 91 | local_irq_enable(); |
| 92 | 92 | } |
| 93 | 93 | |
| 94 | -/* The Au1xxx wait is available only if using 32khz counter or | |
| 95 | - * external timer source, but specifically not CP0 Counter. */ | |
| 96 | -int allow_au1k_wait; | |
| 97 | - | |
| 94 | +/* | |
| 95 | + * The Au1xxx wait is available only if using 32khz counter or | |
| 96 | + * external timer source, but specifically not CP0 Counter. | |
| 97 | + * alchemy/common/time.c may override cpu_wait! | |
| 98 | + */ | |
| 98 | 99 | static void au1k_wait(void) |
| 99 | 100 | { |
| 100 | - if (!allow_au1k_wait) | |
| 101 | - return; | |
| 102 | - | |
| 103 | - /* using the wait instruction makes CP0 counter unusable */ | |
| 104 | 101 | __asm__(" .set mips3 \n" |
| 105 | 102 | " cache 0x14, 0(%0) \n" |
| 106 | 103 | " cache 0x14, 32(%0) \n" |