Commit 2ab9b41a1ac235c81f20bfebec69d4eb7021b275

Authored by Patil, Rachna
1 parent 2e8d35ab98

input: ti_tsc: Handle fifo 0 underflow and overflow interrupts

Since TSC is configured to use FIFO 0 to store the touch data,
enable FIFO 0 underflow and overflow interrupts, so that all states of
FIFO can be addressed.

Signed-off-by: Patil, Rachna <rachna@ti.com>

Showing 2 changed files with 22 additions and 3 deletions Side-by-side Diff

drivers/input/touchscreen/ti_tsc.c
... ... @@ -157,7 +157,7 @@
157 157 unsigned int cur_diff_x = 0, cur_diff_y = 0;
158 158 unsigned int val_x = 0, val_y = 0, diffx = 0, diffy = 0;
159 159 unsigned int z1 = 0, z2 = 0, z = 0;
160   - unsigned int channel;
  160 + unsigned int channel, config;
161 161  
162 162 status = tscadc_readl(ts_dev, TSCADC_REG_IRQSTATUS);
163 163  
... ... @@ -172,7 +172,23 @@
172 172 (status & TSCADC_IRQENB_FIFO1OVRRUN) ||
173 173 (status & TSCADC_IRQENB_FIFO1UNDRFLW))
174 174 return IRQ_NONE;
175   - else if (status & TSCADC_IRQENB_FIFO0THRES) {
  175 + else if ((status & TSCADC_IRQENB_FIFO0OVRRUN) ||
  176 + (status & TSCADC_IRQENB_FIFO0UNDRFLW)) {
  177 + config = tscadc_readl(ts_dev, TSCADC_REG_CTRL);
  178 + config &= ~(TSCADC_CNTRLREG_TSCSSENB);
  179 + tscadc_writel(ts_dev, TSCADC_REG_CTRL, config);
  180 +
  181 + if (status & TSCADC_IRQENB_FIFO0UNDRFLW)
  182 + tscadc_writel(ts_dev, TSCADC_REG_IRQSTATUS,
  183 + (status | TSCADC_IRQENB_FIFO0UNDRFLW));
  184 + else
  185 + tscadc_writel(ts_dev, TSCADC_REG_IRQSTATUS,
  186 + (status | TSCADC_IRQENB_FIFO0OVRRUN));
  187 +
  188 + tscadc_writel(ts_dev, TSCADC_REG_CTRL,
  189 + (config | TSCADC_CNTRLREG_TSCSSENB));
  190 + return IRQ_HANDLED;
  191 + } else if (status & TSCADC_IRQENB_FIFO0THRES) {
176 192 for (i = 0; i < ts_dev->steps_to_config; i++) {
177 193 readx1 = tscadc_readl(ts_dev, TSCADC_REG_FIFO0);
178 194 channel = readx1 & 0xf0000;
... ... @@ -342,7 +358,8 @@
342 358 ts_dev->steps_to_config = pdata->tsc_init->steps_to_configure;
343 359  
344 360 /* IRQ Enable */
345   - irqenable = TSCADC_IRQENB_FIFO0THRES;
  361 + irqenable = TSCADC_IRQENB_FIFO0THRES | TSCADC_IRQENB_FIFO0OVRRUN |
  362 + TSCADC_IRQENB_FIFO0UNDRFLW;
346 363 tscadc_writel(ts_dev, TSCADC_REG_IRQENABLE, irqenable);
347 364  
348 365 tsc_step_config(ts_dev);
include/linux/mfd/ti_tscadc.h
... ... @@ -50,6 +50,8 @@
50 50 /* IRQ enable */
51 51 #define TSCADC_IRQENB_HW_PEN BIT(0)
52 52 #define TSCADC_IRQENB_FIFO0THRES BIT(2)
  53 +#define TSCADC_IRQENB_FIFO0OVRRUN BIT(3)
  54 +#define TSCADC_IRQENB_FIFO0UNDRFLW BIT(4)
53 55 #define TSCADC_IRQENB_FIFO1THRES BIT(5)
54 56 #define TSCADC_IRQENB_FIFO1OVRRUN BIT(6)
55 57 #define TSCADC_IRQENB_FIFO1UNDRFLW BIT(7)