Eric Lee / linux-smarc-t335x-v3.2

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Commit 370630359cb8db711cf0941cd2a242e28ccfb61e

Authored by Manjunathappa, Prakash
1 parent 94082f3588
Exists in master

video: da8xx-fb: reset LCDC only if functional clock changes with DVFS 

LCDC functional clock may or may not be derived from CPU/MPU DPLL,
For example,
AM335x => Separate independent DPLL for LCDC
Davinci => Same DPLL as MPU

So, on platforms where LCDC functional clock is not derived from CPU/MPU
PLL it is not required to reset LCDC module as its functional clock does
not change with DVFS.

This patch adds check to do reset only if functional clock changes
between pre and post notifier callbacks with DVFS.

Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>

Showing 1 changed file with 10 additions and 5 deletions Side-by-side Diff

drivers/video/da8xx-fb.c
Diff comments   View file @ 3706303
... ... @@ -172,6 +172,7 @@
172 172 unsigned int which_dma_channel_done;
173 173 #ifdef CONFIG_CPU_FREQ
174 174 struct notifier_block freq_transition;
  175 + unsigned int lcd_fck_rate;
175 176 #endif
176 177 void (*panel_power_ctrl)(int);
177 178 };
... ... @@ -955,11 +956,12 @@
955 956 struct da8xx_fb_par *par;
956 957  
957 958 par = container_of(nb, struct da8xx_fb_par, freq_transition);
958   - if (val == CPUFREQ_PRECHANGE) {
959   - lcd_disable_raster();
960   - } else if (val == CPUFREQ_POSTCHANGE) {
961   - lcd_calc_clk_divider(par);
962   - lcd_enable_raster();
  959 + if (val == CPUFREQ_POSTCHANGE) {
  960 + if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
  961 + lcd_disable_raster();
  962 + lcd_calc_clk_divider(par);
  963 + lcd_enable_raster();
  964 + }
963 965 }
964 966  
965 967 return 0;
... ... @@ -1302,6 +1304,9 @@
1302 1304  
1303 1305 par = da8xx_fb_info->par;
1304 1306 par->lcdc_clk = fb_clk;
  1307 +#ifdef CONFIG_CPU_FREQ
  1308 + par->lcd_fck_rate = clk_get_rate(fb_clk);
  1309 +#endif
1305 1310 par->pxl_clk = lcdc_info->pxl_clk;
1306 1311 if (fb_pdata->panel_power_ctrl) {
1307 1312 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;