OMAP3: Add support for DPLL3 divisor values higher than 2

Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com>

OMAP3: Add support for DPLL3 divisor values higher than 2
Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <tero.kristo@nokia.com>
Tero Kristo · paul
1 parent df14e4747a
Showing 4 changed files with 15 additions and 14 deletions Side-by-side Diff
arch/arm/mach-omap2/clock34xx.c
arch/arm/mach-omap2/sram34xx.S
arch/arm/plat-omap/include/mach/sram.h
arch/arm/plat-omap/sram.c
@@ -739,9 +739,9 @@
  
 	sdrcrate = sdrc_ick.rate;
 	if (rate > clk->rate)
-		sdrcrate <<= ((rate / clk->rate) - 1);
+		sdrcrate <<= ((rate / clk->rate) >> 1);
 	else
-		sdrcrate >>= ((clk->rate / rate) - 1);
+		sdrcrate >>= ((clk->rate / rate) >> 1);
  
 	sp = omap2_sdrc_get_params(sdrcrate);
 	if (!sp)
  
@@ -768,12 +768,9 @@
 	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
 		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
  
-	/* REVISIT: SRAM code doesn't support other M2 divisors yet */
-	WARN_ON(new_div != 1 && new_div != 2);
-
 	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
 				  sp->actim_ctrlb, new_div, unlock_dll, c,
-				  sp->mr);
+				  sp->mr, rate > clk->rate);
  
 	return 0;
 }
@@ -70,6 +70,7 @@
  * r5 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
  * r6 = new SDRC_MR_0 register value
+ * r7 = increasing SDRC rate? (1 = yes, 0 = no)
  *
  */
 ENTRY(omap3_sram_configure_core_dpll)
  
@@ -77,9 +78,10 @@
 	ldr	r4, [sp, #52]		@ pull extra args off the stack
 	ldr	r5, [sp, #56]		@ load extra args from the stack
 	ldr	r6, [sp, #60]		@ load extra args from the stack
+	ldr	r7, [sp, #64]		@ load extra args from the stack
 	dsb				@ flush buffered writes to interconnect
-	cmp	r3, #0x2		@ if increasing SDRC clk rate,
-	blne	configure_sdrc		@ program the SDRC regs early (for RFR)
+	cmp	r7, #1			@ if increasing SDRC clk rate,
+	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
 	cmp	r4, #SDRC_UNLOCK_DLL	@ set the intended DLL state
 	bleq	unlock_dll
 	blne	lock_dll
@@ -89,7 +91,7 @@
 	cmp	r4, #SDRC_UNLOCK_DLL	@ wait for DLL status to change
 	bleq	wait_dll_unlock
 	blne	wait_dll_lock
-	cmp	r3, #0x1		@ if increasing SDRC clk rate,
+	cmp	r7, #1			@ if increasing SDRC clk rate,
 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
 	bl	configure_sdrc		@ reprogram SDRC regs now
 	mov	r12, r5
@@ -24,7 +24,8 @@
 extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
 				     u32 sdrc_actim_ctrla,
 				     u32 sdrc_actim_ctrlb, u32 m2,
-				     u32 unlock_dll, u32 f, u32 sdrc_mr);
+				     u32 unlock_dll, u32 f, u32 sdrc_mr,
+				     u32 inc);
  
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -62,7 +63,8 @@
 extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
 					  u32 sdrc_actim_ctrla,
 					  u32 sdrc_actim_ctrlb, u32 m2,
-					  u32 unlock_dll, u32 f, u32 sdrc_mr);
+					  u32 unlock_dll, u32 f, u32 sdrc_mr,
+					  u32 inc);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
  
 #endif
@@ -372,16 +372,16 @@
 					      u32 sdrc_actim_ctrla,
 					      u32 sdrc_actim_ctrlb,
 					      u32 m2, u32 unlock_dll,
-					      u32 f, u32 sdrc_mr);
+					      u32 f, u32 sdrc_mr, u32 inc);
 u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
 			      u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-			      u32 f, u32 sdrc_mr)
+			      u32 f, u32 sdrc_mr, u32 inc)
 {
 	BUG_ON(!_omap3_sram_configure_core_dpll);
 	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
 					       sdrc_actim_ctrla,
 					       sdrc_actim_ctrlb, m2,
-					       unlock_dll, f, sdrc_mr);
+					       unlock_dll, f, sdrc_mr, inc);
 }
  
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
...	...	@@ -739,9 +739,9 @@
739	739
740	740	sdrcrate = sdrc_ick.rate;
741	741	if (rate > clk->rate)
742		- sdrcrate <<= ((rate / clk->rate) - 1);
	742	+ sdrcrate <<= ((rate / clk->rate) >> 1);
743	743	else
744		- sdrcrate >>= ((clk->rate / rate) - 1);
	744	+ sdrcrate >>= ((clk->rate / rate) >> 1);
745	745
746	746	sp = omap2_sdrc_get_params(sdrcrate);
747	747	if (!sp)
748	748
...	...	@@ -768,12 +768,9 @@
768	768	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
769	769	sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
770	770
771		- /* REVISIT: SRAM code doesn't support other M2 divisors yet */
772		- WARN_ON(new_div != 1 && new_div != 2);
773		-
774	771	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
775	772	sp->actim_ctrlb, new_div, unlock_dll, c,
776		- sp->mr);
	773	+ sp->mr, rate > clk->rate);
777	774
778	775	return 0;
779	776	}
...	...	@@ -70,6 +70,7 @@
70	70	* r5 = number of MPU cycles to wait for SDRC to stabilize after
71	71	* reprogramming the SDRC when switching to a slower MPU speed
72	72	* r6 = new SDRC_MR_0 register value
	73	+ * r7 = increasing SDRC rate? (1 = yes, 0 = no)
73	74	*
74	75	*/
75	76	ENTRY(omap3_sram_configure_core_dpll)
76	77
...	...	@@ -77,9 +78,10 @@
77	78	ldr r4, [sp, #52] @ pull extra args off the stack
78	79	ldr r5, [sp, #56] @ load extra args from the stack
79	80	ldr r6, [sp, #60] @ load extra args from the stack
	81	+ ldr r7, [sp, #64] @ load extra args from the stack
80	82	dsb @ flush buffered writes to interconnect
81		- cmp r3, #0x2 @ if increasing SDRC clk rate,
82		- blne configure_sdrc @ program the SDRC regs early (for RFR)
	83	+ cmp r7, #1 @ if increasing SDRC clk rate,
	84	+ bleq configure_sdrc @ program the SDRC regs early (for RFR)
83	85	cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
84	86	bleq unlock_dll
85	87	blne lock_dll
...	...	@@ -89,7 +91,7 @@
89	91	cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
90	92	bleq wait_dll_unlock
91	93	blne wait_dll_lock
92		- cmp r3, #0x1 @ if increasing SDRC clk rate,
	94	+ cmp r7, #1 @ if increasing SDRC clk rate,
93	95	beq return_to_sdram @ return to SDRAM code, otherwise,
94	96	bl configure_sdrc @ reprogram SDRC regs now
95	97	mov r12, r5
...	...	@@ -24,7 +24,8 @@
24	24	extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25	25	u32 sdrc_actim_ctrla,
26	26	u32 sdrc_actim_ctrlb, u32 m2,
27		- u32 unlock_dll, u32 f, u32 sdrc_mr);
	27	+ u32 unlock_dll, u32 f, u32 sdrc_mr,
	28	+ u32 inc);
28	29
29	30	/* Do not use these */
30	31	extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
...	...	@@ -62,7 +63,8 @@
62	63	extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
63	64	u32 sdrc_actim_ctrla,
64	65	u32 sdrc_actim_ctrlb, u32 m2,
65		- u32 unlock_dll, u32 f, u32 sdrc_mr);
	66	+ u32 unlock_dll, u32 f, u32 sdrc_mr,
	67	+ u32 inc);
66	68	extern unsigned long omap3_sram_configure_core_dpll_sz;
67	69
68	70	#endif
...	...	@@ -372,16 +372,16 @@
372	372	u32 sdrc_actim_ctrla,
373	373	u32 sdrc_actim_ctrlb,
374	374	u32 m2, u32 unlock_dll,
375		- u32 f, u32 sdrc_mr);
	375	+ u32 f, u32 sdrc_mr, u32 inc);
376	376	u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
377	377	u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
378		- u32 f, u32 sdrc_mr)
	378	+ u32 f, u32 sdrc_mr, u32 inc)
379	379	{
380	380	BUG_ON(!_omap3_sram_configure_core_dpll);
381	381	return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
382	382	sdrc_actim_ctrla,
383	383	sdrc_actim_ctrlb, m2,
384		- unlock_dll, f, sdrc_mr);
	384	+ unlock_dll, f, sdrc_mr, inc);
385	385	}
386	386
387	387	/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */