Eric Lee / linux-smarc-t335x-v3.2

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Commit 4be2ce1b85bcec765a05f3034a7eded78d6293f7

Authored by Patil, Rachna
1 parent 2ab9b41a1a
Exists in v3.2_SMARCT335xPSP_04.06.00.11 and in 3 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN

ARM: OMAP: AM33XX: PM: Fix TSC disable in standby path 

Touchscreen once enabled in standby needs to be disabled again.
Writing 0x02 will only re-enable touchscreen. Fix the same by writing
0x00 to the registers.

Signed-off-by: Patil, Rachna <rachna@ti.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/arm/mach-omap2/pm33xx.c
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1 /* 1 /*
2 * AM33XX Power Management Routines 2 * AM33XX Power Management Routines
3 * 3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2. 8 * published by the Free Software Foundation version 2.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 #include <linux/kernel.h> 16 #include <linux/kernel.h>
17 #include <linux/init.h> 17 #include <linux/init.h>
18 #include <linux/clk.h> 18 #include <linux/clk.h>
19 #include <linux/console.h> 19 #include <linux/console.h>
20 #include <linux/err.h> 20 #include <linux/err.h>
21 #include <linux/firmware.h> 21 #include <linux/firmware.h>
22 #include <linux/io.h> 22 #include <linux/io.h>
23 #include <linux/platform_device.h> 23 #include <linux/platform_device.h>
24 #include <linux/sched.h> 24 #include <linux/sched.h>
25 #include <linux/suspend.h> 25 #include <linux/suspend.h>
26 #include <linux/completion.h> 26 #include <linux/completion.h>
27 #include <linux/pm_runtime.h> 27 #include <linux/pm_runtime.h>
28 28
29 #include <mach/board-am335xevm.h> 29 #include <mach/board-am335xevm.h>
30 #include <plat/prcm.h> 30 #include <plat/prcm.h>
31 #include <plat/mailbox.h> 31 #include <plat/mailbox.h>
32 #include <plat/sram.h> 32 #include <plat/sram.h>
33 #include <plat/omap_hwmod.h> 33 #include <plat/omap_hwmod.h>
34 #include <plat/omap_device.h> 34 #include <plat/omap_device.h>
35 #include <plat/emif.h> 35 #include <plat/emif.h>
36 36
37 #include <asm/suspend.h> 37 #include <asm/suspend.h>
38 #include <asm/proc-fns.h> 38 #include <asm/proc-fns.h>
39 #include <asm/sizes.h> 39 #include <asm/sizes.h>
40 40
41 #include "pm.h" 41 #include "pm.h"
42 #include "cm33xx.h" 42 #include "cm33xx.h"
43 #include "pm33xx.h" 43 #include "pm33xx.h"
44 #include "control.h" 44 #include "control.h"
45 #include "clockdomain.h" 45 #include "clockdomain.h"
46 #include "powerdomain.h" 46 #include "powerdomain.h"
47 47
48 void (*am33xx_do_wfi_sram)(u32 *); 48 void (*am33xx_do_wfi_sram)(u32 *);
49 49
50 #define DS_MODE DS0_ID /* DS0/1_ID */ 50 #define DS_MODE DS0_ID /* DS0/1_ID */
51 #define MODULE_DISABLE 0x0 51 #define MODULE_DISABLE 0x0
52 #define MODULE_ENABLE 0x2 52 #define MODULE_ENABLE 0x2
53 53
54 #ifdef CONFIG_SUSPEND 54 #ifdef CONFIG_SUSPEND
55 void __iomem *ipc_regs; 55 void __iomem *ipc_regs;
56 void __iomem *m3_eoi; 56 void __iomem *m3_eoi;
57 void __iomem *m3_code; 57 void __iomem *m3_code;
58 u32 suspend_cfg_param_list[SUSPEND_CFG_PARAMS_END]; 58 u32 suspend_cfg_param_list[SUSPEND_CFG_PARAMS_END];
59 59
60 bool enable_deep_sleep = true; 60 bool enable_deep_sleep = true;
61 static suspend_state_t suspend_state = PM_SUSPEND_ON; 61 static suspend_state_t suspend_state = PM_SUSPEND_ON;
62 62
63 static struct device *mpu_dev; 63 static struct device *mpu_dev;
64 static struct omap_mbox *m3_mbox; 64 static struct omap_mbox *m3_mbox;
65 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm; 65 static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm;
66 static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm; 66 static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
67 67
68 static int m3_state = M3_STATE_UNKNOWN; 68 static int m3_state = M3_STATE_UNKNOWN;
69 static int m3_version = M3_VERSION_UNKNOWN; 69 static int m3_version = M3_VERSION_UNKNOWN;
70 70
71 static int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *); 71 static int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *);
72 static int am33xx_verify_lp_state(int); 72 static int am33xx_verify_lp_state(int);
73 static void am33xx_m3_state_machine_reset(void); 73 static void am33xx_m3_state_machine_reset(void);
74 74
75 static DECLARE_COMPLETION(a8_m3_sync); 75 static DECLARE_COMPLETION(a8_m3_sync);
76 76
77 static int am33xx_pm_prepare_late(void) 77 static int am33xx_pm_prepare_late(void)
78 { 78 {
79 int ret = 0; 79 int ret = 0;
80 80
81 am335x_save_padconf(); 81 am335x_save_padconf();
82 am33xx_setup_pinmux_on_suspend(); 82 am33xx_setup_pinmux_on_suspend();
83 am33xx_standby_setup(suspend_state); 83 am33xx_standby_setup(suspend_state);
84 84
85 return ret; 85 return ret;
86 } 86 }
87 87
88 static void am33xx_pm_finish(void) 88 static void am33xx_pm_finish(void)
89 { 89 {
90 am33xx_standby_release(suspend_state); 90 am33xx_standby_release(suspend_state);
91 am335x_restore_padconf(); 91 am335x_restore_padconf();
92 } 92 }
93 93
94 static int am33xx_do_sram_idle(long unsigned int state) 94 static int am33xx_do_sram_idle(long unsigned int state)
95 { 95 {
96 am33xx_do_wfi_sram(&suspend_cfg_param_list[0]); 96 am33xx_do_wfi_sram(&suspend_cfg_param_list[0]);
97 97
98 return 0; 98 return 0;
99 } 99 }
100 100
101 static int am33xx_pm_suspend(void) 101 static int am33xx_pm_suspend(void)
102 { 102 {
103 int state, ret = 0; 103 int state, ret = 0;
104 104
105 struct omap_hwmod *gpmc_oh, *usb_oh, *gpio1_oh; 105 struct omap_hwmod *gpmc_oh, *usb_oh, *gpio1_oh;
106 106
107 usb_oh = omap_hwmod_lookup("usb_otg_hs"); 107 usb_oh = omap_hwmod_lookup("usb_otg_hs");
108 gpmc_oh = omap_hwmod_lookup("gpmc"); 108 gpmc_oh = omap_hwmod_lookup("gpmc");
109 gpio1_oh = omap_hwmod_lookup("gpio1"); /* WKUP domain GPIO */ 109 gpio1_oh = omap_hwmod_lookup("gpio1"); /* WKUP domain GPIO */
110 110
111 omap_hwmod_enable(usb_oh); 111 omap_hwmod_enable(usb_oh);
112 omap_hwmod_enable(gpmc_oh); 112 omap_hwmod_enable(gpmc_oh);
113 113
114 /* 114 /*
115 * Keep USB module enabled during standby 115 * Keep USB module enabled during standby
116 * to enable USB remote wakeup 116 * to enable USB remote wakeup
117 * Note: This will result in hard-coding USB state 117 * Note: This will result in hard-coding USB state
118 * during standby 118 * during standby
119 */ 119 */
120 if (suspend_state != PM_SUSPEND_STANDBY) 120 if (suspend_state != PM_SUSPEND_STANDBY)
121 omap_hwmod_idle(usb_oh); 121 omap_hwmod_idle(usb_oh);
122 122
123 omap_hwmod_idle(gpmc_oh); 123 omap_hwmod_idle(gpmc_oh);
124 124
125 /* 125 /*
126 * Disable the GPIO module. This ensure that 126 * Disable the GPIO module. This ensure that
127 * only sWAKEUP interrupts to Cortex-M3 get generated 127 * only sWAKEUP interrupts to Cortex-M3 get generated
128 * 128 *
129 * XXX: EVM_SK uses a GPIO0 pin for VTP control 129 * XXX: EVM_SK uses a GPIO0 pin for VTP control
130 * in suspend and hence we can't do this for EVM_SK 130 * in suspend and hence we can't do this for EVM_SK
131 * alone. The side-effect of this is that GPIO wakeup 131 * alone. The side-effect of this is that GPIO wakeup
132 * might have issues. Refer to commit 672639b for the 132 * might have issues. Refer to commit 672639b for the
133 * details 133 * details
134 */ 134 */
135 /* 135 /*
136 * Keep GPIO0 module enabled during standby to 136 * Keep GPIO0 module enabled during standby to
137 * support wakeup via GPIO0 keys. 137 * support wakeup via GPIO0 keys.
138 */ 138 */
139 if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) && 139 if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) &&
140 (suspend_state != PM_SUSPEND_STANDBY)) 140 (suspend_state != PM_SUSPEND_STANDBY))
141 omap_hwmod_idle(gpio1_oh); 141 omap_hwmod_idle(gpio1_oh);
142 /* 142 /*
143 * Update Suspend_State value to be used in sleep33xx.S to keep 143 * Update Suspend_State value to be used in sleep33xx.S to keep
144 * GPIO0 module enabled during standby for EVM-SK 144 * GPIO0 module enabled during standby for EVM-SK
145 */ 145 */
146 if (suspend_state == PM_SUSPEND_STANDBY) 146 if (suspend_state == PM_SUSPEND_STANDBY)
147 suspend_cfg_param_list[SUSPEND_STATE] = PM_STANDBY; 147 suspend_cfg_param_list[SUSPEND_STATE] = PM_STANDBY;
148 else 148 else
149 suspend_cfg_param_list[SUSPEND_STATE] = PM_DS0; 149 suspend_cfg_param_list[SUSPEND_STATE] = PM_DS0;
150 150
151 /* 151 /*
152 * Keep Touchscreen module enabled during standby 152 * Keep Touchscreen module enabled during standby
153 * to enable wakeup from standby. 153 * to enable wakeup from standby.
154 */ 154 */
155 if (suspend_state == PM_SUSPEND_STANDBY) 155 if (suspend_state == PM_SUSPEND_STANDBY)
156 writel(0x2, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL); 156 writel(0x2, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL);
157 157
158 if (gfx_l3_clkdm && gfx_l4ls_clkdm) { 158 if (gfx_l3_clkdm && gfx_l4ls_clkdm) {
159 clkdm_sleep(gfx_l3_clkdm); 159 clkdm_sleep(gfx_l3_clkdm);
160 clkdm_sleep(gfx_l4ls_clkdm); 160 clkdm_sleep(gfx_l4ls_clkdm);
161 } 161 }
162 162
163 /* Try to put GFX to sleep */ 163 /* Try to put GFX to sleep */
164 if (gfx_pwrdm) 164 if (gfx_pwrdm)
165 pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF); 165 pwrdm_set_next_pwrst(gfx_pwrdm, PWRDM_POWER_OFF);
166 else 166 else
167 pr_err("Could not program GFX to low power state\n"); 167 pr_err("Could not program GFX to low power state\n");
168 168
169 omap3_intc_suspend(); 169 omap3_intc_suspend();
170 170
171 writel(0x0, AM33XX_CM_MPU_MPU_CLKCTRL); 171 writel(0x0, AM33XX_CM_MPU_MPU_CLKCTRL);
172 172
173 ret = cpu_suspend(0, am33xx_do_sram_idle); 173 ret = cpu_suspend(0, am33xx_do_sram_idle);
174 174
175 writel(0x2, AM33XX_CM_MPU_MPU_CLKCTRL); 175 writel(0x2, AM33XX_CM_MPU_MPU_CLKCTRL);
176 176
177 if (gfx_pwrdm) { 177 if (gfx_pwrdm) {
178 state = pwrdm_read_pwrst(gfx_pwrdm); 178 state = pwrdm_read_pwrst(gfx_pwrdm);
179 if (state != PWRDM_POWER_OFF) 179 if (state != PWRDM_POWER_OFF)
180 pr_err("GFX domain did not transition to low power state\n"); 180 pr_err("GFX domain did not transition to low power state\n");
181 else 181 else
182 pr_info("GFX domain entered low power state\n"); 182 pr_info("GFX domain entered low power state\n");
183 } 183 }
184 184
185 /* XXX: Why do we need to wakeup the clockdomains? */ 185 /* XXX: Why do we need to wakeup the clockdomains? */
186 if(gfx_l3_clkdm && gfx_l4ls_clkdm) { 186 if(gfx_l3_clkdm && gfx_l4ls_clkdm) {
187 clkdm_wakeup(gfx_l3_clkdm); 187 clkdm_wakeup(gfx_l3_clkdm);
188 clkdm_wakeup(gfx_l4ls_clkdm); 188 clkdm_wakeup(gfx_l4ls_clkdm);
189 } 189 }
190 190
191 /* 191 /*
192 * Touchscreen module was enabled during standby 192 * Touchscreen module was enabled during standby
193 * Disable it here. 193 * Disable it here.
194 */ 194 */
195 if (suspend_state == PM_SUSPEND_STANDBY) 195 if (suspend_state == PM_SUSPEND_STANDBY)
196 writel(0x2, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL); 196 writel(0x0, AM33XX_CM_WKUP_ADC_TSC_CLKCTRL);
197 197
198 /* 198 /*
199 * Put USB module to idle on resume from standby 199 * Put USB module to idle on resume from standby
200 */ 200 */
201 if (suspend_state == PM_SUSPEND_STANDBY) 201 if (suspend_state == PM_SUSPEND_STANDBY)
202 omap_hwmod_idle(usb_oh); 202 omap_hwmod_idle(usb_oh);
203 203
204 ret = am33xx_verify_lp_state(ret); 204 ret = am33xx_verify_lp_state(ret);
205 205
206 /* 206 /*
207 * Enable the GPIO module. Once the driver is 207 * Enable the GPIO module. Once the driver is
208 * fully adapted to runtime PM this will go away 208 * fully adapted to runtime PM this will go away
209 */ 209 */
210 /* 210 /*
211 * During standby, GPIO was not disabled. Hence no 211 * During standby, GPIO was not disabled. Hence no
212 * need to enable it here. 212 * need to enable it here.
213 */ 213 */
214 if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) && 214 if ((suspend_cfg_param_list[EVM_ID] != EVM_SK) &&
215 (suspend_state != PM_SUSPEND_STANDBY)) 215 (suspend_state != PM_SUSPEND_STANDBY))
216 omap_hwmod_enable(gpio1_oh); 216 omap_hwmod_enable(gpio1_oh);
217 217
218 return ret; 218 return ret;
219 } 219 }
220 220
221 static int am33xx_pm_enter(suspend_state_t unused) 221 static int am33xx_pm_enter(suspend_state_t unused)
222 { 222 {
223 int ret = 0; 223 int ret = 0;
224 224
225 switch (suspend_state) { 225 switch (suspend_state) {
226 case PM_SUSPEND_STANDBY: 226 case PM_SUSPEND_STANDBY:
227 case PM_SUSPEND_MEM: 227 case PM_SUSPEND_MEM:
228 ret = am33xx_pm_suspend(); 228 ret = am33xx_pm_suspend();
229 break; 229 break;
230 default: 230 default:
231 ret = -EINVAL; 231 ret = -EINVAL;
232 } 232 }
233 233
234 return ret; 234 return ret;
235 } 235 }
236 236
237 static int am33xx_pm_begin(suspend_state_t state) 237 static int am33xx_pm_begin(suspend_state_t state)
238 { 238 {
239 int ret = 0; 239 int ret = 0;
240 int state_id = 0; 240 int state_id = 0;
241 241
242 disable_hlt(); 242 disable_hlt();
243 243
244 switch (state) { 244 switch (state) {
245 case PM_SUSPEND_STANDBY: 245 case PM_SUSPEND_STANDBY:
246 state_id = 0xb; 246 state_id = 0xb;
247 break; 247 break;
248 case PM_SUSPEND_MEM: 248 case PM_SUSPEND_MEM:
249 state_id = 0x3; 249 state_id = 0x3;
250 break; 250 break;
251 } 251 }
252 252
253 /* 253 /*
254 * Populate the resume address as part of IPC data 254 * Populate the resume address as part of IPC data
255 * The offset to be added comes from sleep33xx.S 255 * The offset to be added comes from sleep33xx.S
256 * Add 4 bytes to ensure that resume happens from 256 * Add 4 bytes to ensure that resume happens from
257 * the word *after* the word which holds the resume offset 257 * the word *after* the word which holds the resume offset
258 */ 258 */
259 am33xx_lp_ipc.resume_addr = (DS_RESUME_BASE + am33xx_resume_offset + 4); 259 am33xx_lp_ipc.resume_addr = (DS_RESUME_BASE + am33xx_resume_offset + 4);
260 am33xx_lp_ipc.sleep_mode = state_id; 260 am33xx_lp_ipc.sleep_mode = state_id;
261 am33xx_lp_ipc.ipc_data1 = DS_IPC_DEFAULT; 261 am33xx_lp_ipc.ipc_data1 = DS_IPC_DEFAULT;
262 am33xx_lp_ipc.ipc_data2 = DS_IPC_DEFAULT; 262 am33xx_lp_ipc.ipc_data2 = DS_IPC_DEFAULT;
263 263
264 am33xx_ipc_cmd(&am33xx_lp_ipc); 264 am33xx_ipc_cmd(&am33xx_lp_ipc);
265 265
266 m3_state = M3_STATE_MSG_FOR_LP; 266 m3_state = M3_STATE_MSG_FOR_LP;
267 267
268 omap_mbox_enable_irq(m3_mbox, IRQ_RX); 268 omap_mbox_enable_irq(m3_mbox, IRQ_RX);
269 269
270 ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD); 270 ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
271 if (ret) { 271 if (ret) {
272 pr_err("A8<->CM3 MSG for LP failed\n"); 272 pr_err("A8<->CM3 MSG for LP failed\n");
273 am33xx_m3_state_machine_reset(); 273 am33xx_m3_state_machine_reset();
274 ret = -1; 274 ret = -1;
275 } 275 }
276 276
277 if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000))) { 277 if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000))) {
278 pr_err("A8<->CM3 sync failure\n"); 278 pr_err("A8<->CM3 sync failure\n");
279 am33xx_m3_state_machine_reset(); 279 am33xx_m3_state_machine_reset();
280 ret = -1; 280 ret = -1;
281 } else { 281 } else {
282 pr_debug("Message sent for entering %s\n", 282 pr_debug("Message sent for entering %s\n",
283 (DS_MODE == DS0_ID ? "DS0" : "DS1")); 283 (DS_MODE == DS0_ID ? "DS0" : "DS1"));
284 omap_mbox_disable_irq(m3_mbox, IRQ_RX); 284 omap_mbox_disable_irq(m3_mbox, IRQ_RX);
285 } 285 }
286 286
287 suspend_state = state; 287 suspend_state = state;
288 return ret; 288 return ret;
289 } 289 }
290 290
291 static void am33xx_m3_state_machine_reset(void) 291 static void am33xx_m3_state_machine_reset(void)
292 { 292 {
293 int ret = 0; 293 int ret = 0;
294 294
295 am33xx_lp_ipc.resume_addr = 0x0; 295 am33xx_lp_ipc.resume_addr = 0x0;
296 am33xx_lp_ipc.sleep_mode = 0xe; 296 am33xx_lp_ipc.sleep_mode = 0xe;
297 am33xx_lp_ipc.ipc_data1 = DS_IPC_DEFAULT; 297 am33xx_lp_ipc.ipc_data1 = DS_IPC_DEFAULT;
298 am33xx_lp_ipc.ipc_data2 = DS_IPC_DEFAULT; 298 am33xx_lp_ipc.ipc_data2 = DS_IPC_DEFAULT;
299 299
300 am33xx_ipc_cmd(&am33xx_lp_ipc); 300 am33xx_ipc_cmd(&am33xx_lp_ipc);
301 301
302 m3_state = M3_STATE_MSG_FOR_RESET; 302 m3_state = M3_STATE_MSG_FOR_RESET;
303 303
304 ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD); 304 ret = omap_mbox_msg_send(m3_mbox, 0xABCDABCD);
305 if (!ret) { 305 if (!ret) {
306 pr_debug("Message sent for resetting M3 state machine\n"); 306 pr_debug("Message sent for resetting M3 state machine\n");
307 if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000))) 307 if (!wait_for_completion_timeout(&a8_m3_sync, msecs_to_jiffies(5000)))
308 pr_err("A8<->CM3 sync failure\n"); 308 pr_err("A8<->CM3 sync failure\n");
309 } else { 309 } else {
310 pr_err("Could not reset M3 state machine!!!\n"); 310 pr_err("Could not reset M3 state machine!!!\n");
311 m3_state = M3_STATE_UNKNOWN; 311 m3_state = M3_STATE_UNKNOWN;
312 } 312 }
313 } 313 }
314 314
315 static void am33xx_pm_end(void) 315 static void am33xx_pm_end(void)
316 { 316 {
317 suspend_state = PM_SUSPEND_ON; 317 suspend_state = PM_SUSPEND_ON;
318 318
319 omap_mbox_enable_irq(m3_mbox, IRQ_RX); 319 omap_mbox_enable_irq(m3_mbox, IRQ_RX);
320 320
321 am33xx_m3_state_machine_reset(); 321 am33xx_m3_state_machine_reset();
322 322
323 enable_hlt(); 323 enable_hlt();
324 324
325 return; 325 return;
326 } 326 }
327 327
328 static int am33xx_pm_valid(suspend_state_t state) 328 static int am33xx_pm_valid(suspend_state_t state)
329 { 329 {
330 switch (state) { 330 switch (state) {
331 case PM_SUSPEND_STANDBY: 331 case PM_SUSPEND_STANDBY:
332 case PM_SUSPEND_MEM: 332 case PM_SUSPEND_MEM:
333 return 1; 333 return 1;
334 default: 334 default:
335 return 0; 335 return 0;
336 } 336 }
337 } 337 }
338 338
339 static const struct platform_suspend_ops am33xx_pm_ops = { 339 static const struct platform_suspend_ops am33xx_pm_ops = {
340 .begin = am33xx_pm_begin, 340 .begin = am33xx_pm_begin,
341 .end = am33xx_pm_end, 341 .end = am33xx_pm_end,
342 .enter = am33xx_pm_enter, 342 .enter = am33xx_pm_enter,
343 .valid = am33xx_pm_valid, 343 .valid = am33xx_pm_valid,
344 .prepare = am33xx_pm_prepare_late, 344 .prepare = am33xx_pm_prepare_late,
345 .finish = am33xx_pm_finish, 345 .finish = am33xx_pm_finish,
346 }; 346 };
347 347
348 int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *data) 348 int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *data)
349 { 349 {
350 writel(data->resume_addr, ipc_regs); 350 writel(data->resume_addr, ipc_regs);
351 writel(data->sleep_mode, ipc_regs + 0x4); 351 writel(data->sleep_mode, ipc_regs + 0x4);
352 writel(data->ipc_data1, ipc_regs + 0x8); 352 writel(data->ipc_data1, ipc_regs + 0x8);
353 writel(data->ipc_data2, ipc_regs + 0xc); 353 writel(data->ipc_data2, ipc_regs + 0xc);
354 354
355 return 0; 355 return 0;
356 } 356 }
357 357
358 /* return 0 if no reset M3 needed, 1 otherwise */ 358 /* return 0 if no reset M3 needed, 1 otherwise */
359 static int am33xx_verify_lp_state(int core_suspend_stat) 359 static int am33xx_verify_lp_state(int core_suspend_stat)
360 { 360 {
361 int status, ret = 0; 361 int status, ret = 0;
362 362
363 if (core_suspend_stat) { 363 if (core_suspend_stat) {
364 pr_err("Kernel core reported suspend failure\n"); 364 pr_err("Kernel core reported suspend failure\n");
365 ret = -1; 365 ret = -1;
366 goto clear_old_status; 366 goto clear_old_status;
367 } 367 }
368 368
369 status = readl(ipc_regs + 0x4); 369 status = readl(ipc_regs + 0x4);
370 status &= 0xffff0000; 370 status &= 0xffff0000;
371 371
372 if (status == 0x0) { 372 if (status == 0x0) {
373 pr_info("Successfully transitioned all domains to low power state\n"); 373 pr_info("Successfully transitioned all domains to low power state\n");
374 if (am33xx_lp_ipc.sleep_mode == DS0_ID) 374 if (am33xx_lp_ipc.sleep_mode == DS0_ID)
375 per_pwrdm->ret_logic_off_counter++; 375 per_pwrdm->ret_logic_off_counter++;
376 goto clear_old_status; 376 goto clear_old_status;
377 } else if (status == 0x10000) { 377 } else if (status == 0x10000) {
378 pr_err("Could not enter low power state\n" 378 pr_err("Could not enter low power state\n"
379 "Please check for active clocks in PER domain\n"); 379 "Please check for active clocks in PER domain\n");
380 ret = -1; 380 ret = -1;
381 goto clear_old_status; 381 goto clear_old_status;
382 } else { 382 } else {
383 pr_err("Something is terribly wrong :(\nStatus = %0x\n", 383 pr_err("Something is terribly wrong :(\nStatus = %0x\n",
384 status); 384 status);
385 ret = -1; 385 ret = -1;
386 } 386 }
387 387
388 clear_old_status: 388 clear_old_status:
389 /* After decoding write back the bad status */ 389 /* After decoding write back the bad status */
390 status = readl(ipc_regs + 0x4); 390 status = readl(ipc_regs + 0x4);
391 status &= 0xffff0000; 391 status &= 0xffff0000;
392 status |= 0x10000; 392 status |= 0x10000;
393 writel(status, ipc_regs + 0x4); 393 writel(status, ipc_regs + 0x4);
394 394
395 return ret; 395 return ret;
396 } 396 }
397 397
398 /* 398 /*
399 * Dummy notifier for the mailbox 399 * Dummy notifier for the mailbox
400 * TODO: Can this be completely removed? 400 * TODO: Can this be completely removed?
401 */ 401 */
402 int wkup_m3_mbox_msg(struct notifier_block *self, unsigned long len, void *msg) 402 int wkup_m3_mbox_msg(struct notifier_block *self, unsigned long len, void *msg)
403 { 403 {
404 return 0; 404 return 0;
405 } 405 }
406 406
407 static struct notifier_block wkup_m3_mbox_notifier = { 407 static struct notifier_block wkup_m3_mbox_notifier = {
408 .notifier_call = wkup_m3_mbox_msg, 408 .notifier_call = wkup_m3_mbox_msg,
409 }; 409 };
410 410
411 static irqreturn_t wkup_m3_txev_handler(int irq, void *unused) 411 static irqreturn_t wkup_m3_txev_handler(int irq, void *unused)
412 { 412 {
413 writel(0x1, m3_eoi); 413 writel(0x1, m3_eoi);
414 414
415 if (m3_state == M3_STATE_RESET) { 415 if (m3_state == M3_STATE_RESET) {
416 m3_state = M3_STATE_INITED; 416 m3_state = M3_STATE_INITED;
417 m3_version = readl(ipc_regs + 0x8); 417 m3_version = readl(ipc_regs + 0x8);
418 m3_version &= 0x0000ffff; 418 m3_version &= 0x0000ffff;
419 if (m3_version == M3_VERSION_UNKNOWN) { 419 if (m3_version == M3_VERSION_UNKNOWN) {
420 pr_warning("Unable to read CM3 firmware version\n"); 420 pr_warning("Unable to read CM3 firmware version\n");
421 } else { 421 } else {
422 pr_info("Cortex M3 Firmware Version = 0x%x\n", 422 pr_info("Cortex M3 Firmware Version = 0x%x\n",
423 m3_version); 423 m3_version);
424 } 424 }
425 } else if (m3_state == M3_STATE_MSG_FOR_RESET) { 425 } else if (m3_state == M3_STATE_MSG_FOR_RESET) {
426 m3_state = M3_STATE_INITED; 426 m3_state = M3_STATE_INITED;
427 omap_mbox_msg_rx_flush(m3_mbox); 427 omap_mbox_msg_rx_flush(m3_mbox);
428 if (m3_mbox->ops->ack_irq) 428 if (m3_mbox->ops->ack_irq)
429 m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); 429 m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
430 complete(&a8_m3_sync); 430 complete(&a8_m3_sync);
431 } else if (m3_state == M3_STATE_MSG_FOR_LP) { 431 } else if (m3_state == M3_STATE_MSG_FOR_LP) {
432 omap_mbox_msg_rx_flush(m3_mbox); 432 omap_mbox_msg_rx_flush(m3_mbox);
433 if (m3_mbox->ops->ack_irq) 433 if (m3_mbox->ops->ack_irq)
434 m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); 434 m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
435 complete(&a8_m3_sync); 435 complete(&a8_m3_sync);
436 } else if (m3_state == M3_STATE_UNKNOWN) { 436 } else if (m3_state == M3_STATE_UNKNOWN) {
437 pr_err("IRQ %d with CM3 in unknown state\n", irq); 437 pr_err("IRQ %d with CM3 in unknown state\n", irq);
438 omap_mbox_msg_rx_flush(m3_mbox); 438 omap_mbox_msg_rx_flush(m3_mbox);
439 if (m3_mbox->ops->ack_irq) 439 if (m3_mbox->ops->ack_irq)
440 m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX); 440 m3_mbox->ops->ack_irq(m3_mbox, IRQ_RX);
441 return IRQ_NONE; 441 return IRQ_NONE;
442 } 442 }
443 443
444 writel(0x0, m3_eoi); 444 writel(0x0, m3_eoi);
445 445
446 return IRQ_HANDLED; 446 return IRQ_HANDLED;
447 } 447 }
448 448
449 /* Initiliaze WKUP_M3, load the binary blob and let it run */ 449 /* Initiliaze WKUP_M3, load the binary blob and let it run */
450 static int wkup_m3_init(void) 450 static int wkup_m3_init(void)
451 { 451 {
452 struct clk *m3_clk; 452 struct clk *m3_clk;
453 struct omap_hwmod *wkup_m3_oh; 453 struct omap_hwmod *wkup_m3_oh;
454 const struct firmware *firmware; 454 const struct firmware *firmware;
455 int ret = 0; 455 int ret = 0;
456 int ipc_reg_r = 0; 456 int ipc_reg_r = 0;
457 457
458 wkup_m3_oh = omap_hwmod_lookup("wkup_m3"); 458 wkup_m3_oh = omap_hwmod_lookup("wkup_m3");
459 459
460 if (!wkup_m3_oh) { 460 if (!wkup_m3_oh) {
461 pr_err("%s: could not find omap_hwmod\n", __func__); 461 pr_err("%s: could not find omap_hwmod\n", __func__);
462 ret = -ENODEV; 462 ret = -ENODEV;
463 goto exit; 463 goto exit;
464 } 464 }
465 465
466 ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8); 466 ipc_regs = ioremap(A8_M3_IPC_REGS, 0x4*8);
467 if (!ipc_regs) { 467 if (!ipc_regs) {
468 pr_err("Could not ioremap the IPC area\b"); 468 pr_err("Could not ioremap the IPC area\b");
469 ret = -ENOMEM; 469 ret = -ENOMEM;
470 goto exit; 470 goto exit;
471 } 471 }
472 472
473 m3_eoi = ioremap(M3_TXEV_EOI, 0x4); 473 m3_eoi = ioremap(M3_TXEV_EOI, 0x4);
474 if (!m3_eoi) { 474 if (!m3_eoi) {
475 pr_err("Could not ioremap the EOI register\n"); 475 pr_err("Could not ioremap the EOI register\n");
476 ret = -ENOMEM; 476 ret = -ENOMEM;
477 goto err1; 477 goto err1;
478 } 478 }
479 479
480 /* Reserve the MBOX for sending messages to M3 */ 480 /* Reserve the MBOX for sending messages to M3 */
481 m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier); 481 m3_mbox = omap_mbox_get("wkup_m3", &wkup_m3_mbox_notifier);
482 if (IS_ERR(m3_mbox)) { 482 if (IS_ERR(m3_mbox)) {
483 pr_err("Could not reserve mailbox for A8->M3 IPC\n"); 483 pr_err("Could not reserve mailbox for A8->M3 IPC\n");
484 ret = -ENODEV; 484 ret = -ENODEV;
485 goto err2; 485 goto err2;
486 } 486 }
487 487
488 /* Enable access to the M3 code and data area from A8 */ 488 /* Enable access to the M3 code and data area from A8 */
489 m3_clk = clk_get(NULL, "wkup_m3_fck"); 489 m3_clk = clk_get(NULL, "wkup_m3_fck");
490 if (IS_ERR(m3_clk)) { 490 if (IS_ERR(m3_clk)) {
491 pr_err("%s failed to enable WKUP_M3 clock\n", __func__); 491 pr_err("%s failed to enable WKUP_M3 clock\n", __func__);
492 goto err3; 492 goto err3;
493 } 493 }
494 494
495 if (clk_enable(m3_clk)) { 495 if (clk_enable(m3_clk)) {
496 pr_err("%s WKUP_M3: clock enable Failed\n", __func__); 496 pr_err("%s WKUP_M3: clock enable Failed\n", __func__);
497 goto err4; 497 goto err4;
498 } 498 }
499 499
500 m3_code = ioremap(M3_UMEM, SZ_16K); 500 m3_code = ioremap(M3_UMEM, SZ_16K);
501 if (!m3_code) { 501 if (!m3_code) {
502 pr_err("%s Could not ioremap M3 code space\n", __func__); 502 pr_err("%s Could not ioremap M3 code space\n", __func__);
503 ret = -ENOMEM; 503 ret = -ENOMEM;
504 goto err5; 504 goto err5;
505 } 505 }
506 506
507 pr_info("Trying to load am335x-pm-firmware.bin (60 secs timeout)\n"); 507 pr_info("Trying to load am335x-pm-firmware.bin (60 secs timeout)\n");
508 508
509 ret = request_firmware(&firmware, "am335x-pm-firmware.bin", mpu_dev); 509 ret = request_firmware(&firmware, "am335x-pm-firmware.bin", mpu_dev);
510 if (ret < 0) { 510 if (ret < 0) {
511 dev_err(mpu_dev, "request_firmware failed\n"); 511 dev_err(mpu_dev, "request_firmware failed\n");
512 goto err6; 512 goto err6;
513 } else { 513 } else {
514 memcpy(m3_code, firmware->data, firmware->size); 514 memcpy(m3_code, firmware->data, firmware->size);
515 pr_info("Copied the M3 firmware to UMEM\n"); 515 pr_info("Copied the M3 firmware to UMEM\n");
516 } 516 }
517 517
518 ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler, 518 ret = request_irq(AM33XX_IRQ_M3_M3SP_TXEV, wkup_m3_txev_handler,
519 IRQF_DISABLED, "wkup_m3_txev", NULL); 519 IRQF_DISABLED, "wkup_m3_txev", NULL);
520 if (ret) { 520 if (ret) {
521 pr_err("%s request_irq failed for 0x%x\n", __func__, 521 pr_err("%s request_irq failed for 0x%x\n", __func__,
522 AM33XX_IRQ_M3_M3SP_TXEV); 522 AM33XX_IRQ_M3_M3SP_TXEV);
523 goto err6; 523 goto err6;
524 } 524 }
525 525
526 m3_state = M3_STATE_RESET; 526 m3_state = M3_STATE_RESET;
527 527
528 /* 528 /*
529 * Invalidate M3 firmware version before hardreset. 529 * Invalidate M3 firmware version before hardreset.
530 * Write invalid version in lower 4 nibbles of parameter 530 * Write invalid version in lower 4 nibbles of parameter
531 * register (ipc_regs + 0x8). 531 * register (ipc_regs + 0x8).
532 */ 532 */
533 ipc_reg_r = readl(ipc_regs + 0x8); 533 ipc_reg_r = readl(ipc_regs + 0x8);
534 ipc_reg_r &= 0xffff0000; 534 ipc_reg_r &= 0xffff0000;
535 m3_version |= ipc_reg_r; 535 m3_version |= ipc_reg_r;
536 writel(m3_version, ipc_regs + 0x8); 536 writel(m3_version, ipc_regs + 0x8);
537 537
538 ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3"); 538 ret = omap_hwmod_deassert_hardreset(wkup_m3_oh, "wkup_m3");
539 if (ret) { 539 if (ret) {
540 pr_err("Could not deassert the reset for WKUP_M3\n"); 540 pr_err("Could not deassert the reset for WKUP_M3\n");
541 goto err6; 541 goto err6;
542 } else { 542 } else {
543 return 0; 543 return 0;
544 } 544 }
545 545
546 err6: 546 err6:
547 release_firmware(firmware); 547 release_firmware(firmware);
548 iounmap(m3_code); 548 iounmap(m3_code);
549 err5: 549 err5:
550 clk_disable(m3_clk); 550 clk_disable(m3_clk);
551 err4: 551 err4:
552 clk_put(m3_clk); 552 clk_put(m3_clk);
553 err3: 553 err3:
554 omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier); 554 omap_mbox_put(m3_mbox, &wkup_m3_mbox_notifier);
555 err2: 555 err2:
556 iounmap(m3_eoi); 556 iounmap(m3_eoi);
557 err1: 557 err1:
558 iounmap(ipc_regs); 558 iounmap(ipc_regs);
559 exit: 559 exit:
560 return ret; 560 return ret;
561 } 561 }
562 562
563 /* 563 /*
564 * Initiate sleep transition for other clockdomains, if 564 * Initiate sleep transition for other clockdomains, if
565 * they are not used 565 * they are not used
566 */ 566 */
567 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) 567 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
568 { 568 {
569 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 569 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
570 atomic_read(&clkdm->usecount) == 0) 570 atomic_read(&clkdm->usecount) == 0)
571 clkdm_sleep(clkdm); 571 clkdm_sleep(clkdm);
572 return 0; 572 return 0;
573 } 573 }
574 #endif /* CONFIG_SUSPEND */ 574 #endif /* CONFIG_SUSPEND */
575 575
576 /* 576 /*
577 * Push the minimal suspend-resume code to SRAM 577 * Push the minimal suspend-resume code to SRAM
578 */ 578 */
579 void am33xx_push_sram_idle(void) 579 void am33xx_push_sram_idle(void)
580 { 580 {
581 am33xx_do_wfi_sram = (void *)omap_sram_push 581 am33xx_do_wfi_sram = (void *)omap_sram_push
582 (am33xx_do_wfi, am33xx_do_wfi_sz); 582 (am33xx_do_wfi, am33xx_do_wfi_sz);
583 } 583 }
584 584
585 static int __init am33xx_pm_init(void) 585 static int __init am33xx_pm_init(void)
586 { 586 {
587 int ret; 587 int ret;
588 #ifdef CONFIG_SUSPEND 588 #ifdef CONFIG_SUSPEND
589 void __iomem *base; 589 void __iomem *base;
590 u32 reg; 590 u32 reg;
591 u32 evm_id; 591 u32 evm_id;
592 592
593 #endif 593 #endif
594 if (!cpu_is_am33xx()) 594 if (!cpu_is_am33xx())
595 return -ENODEV; 595 return -ENODEV;
596 596
597 pr_info("Power Management for AM33XX family\n"); 597 pr_info("Power Management for AM33XX family\n");
598 598
599 #ifdef CONFIG_SUSPEND 599 #ifdef CONFIG_SUSPEND
600 /* Read SDRAM_CONFIG register to determine Memory Type */ 600 /* Read SDRAM_CONFIG register to determine Memory Type */
601 base = am33xx_get_ram_base(); 601 base = am33xx_get_ram_base();
602 reg = readl(base + EMIF4_0_SDRAM_CONFIG); 602 reg = readl(base + EMIF4_0_SDRAM_CONFIG);
603 reg = (reg & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT; 603 reg = (reg & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
604 suspend_cfg_param_list[MEMORY_TYPE] = reg; 604 suspend_cfg_param_list[MEMORY_TYPE] = reg;
605 605
606 /* 606 /*
607 * vtp_ctrl register value for DDR2 and DDR3 as suggested 607 * vtp_ctrl register value for DDR2 and DDR3 as suggested
608 * by h/w team 608 * by h/w team
609 */ 609 */
610 if (reg == MEM_TYPE_DDR2) 610 if (reg == MEM_TYPE_DDR2)
611 suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR2; 611 suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR2;
612 else 612 else
613 suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR3; 613 suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR3;
614 614
615 615
616 /* Get Board Id */ 616 /* Get Board Id */
617 evm_id = am335x_evm_get_id(); 617 evm_id = am335x_evm_get_id();
618 if (evm_id != -EINVAL) 618 if (evm_id != -EINVAL)
619 suspend_cfg_param_list[EVM_ID] = evm_id; 619 suspend_cfg_param_list[EVM_ID] = evm_id;
620 else 620 else
621 suspend_cfg_param_list[EVM_ID] = 0xff; 621 suspend_cfg_param_list[EVM_ID] = 0xff;
622 622
623 /* CPU Revision */ 623 /* CPU Revision */
624 reg = omap_rev(); 624 reg = omap_rev();
625 if (reg == AM335X_REV_ES2_0) 625 if (reg == AM335X_REV_ES2_0)
626 suspend_cfg_param_list[CPU_REV] = CPU_REV_2; 626 suspend_cfg_param_list[CPU_REV] = CPU_REV_2;
627 else 627 else
628 suspend_cfg_param_list[CPU_REV] = CPU_REV_1; 628 suspend_cfg_param_list[CPU_REV] = CPU_REV_1;
629 629
630 (void) clkdm_for_each(clkdms_setup, NULL); 630 (void) clkdm_for_each(clkdms_setup, NULL);
631 631
632 /* CEFUSE domain should be turned off post bootup */ 632 /* CEFUSE domain should be turned off post bootup */
633 cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm"); 633 cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
634 if (cefuse_pwrdm == NULL) 634 if (cefuse_pwrdm == NULL)
635 pr_err("Failed to get cefuse_pwrdm\n"); 635 pr_err("Failed to get cefuse_pwrdm\n");
636 else 636 else
637 pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF); 637 pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
638 638
639 gfx_pwrdm = pwrdm_lookup("gfx_pwrdm"); 639 gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
640 if (gfx_pwrdm == NULL) 640 if (gfx_pwrdm == NULL)
641 pr_err("Failed to get gfx_pwrdm\n"); 641 pr_err("Failed to get gfx_pwrdm\n");
642 642
643 per_pwrdm = pwrdm_lookup("per_pwrdm"); 643 per_pwrdm = pwrdm_lookup("per_pwrdm");
644 if (per_pwrdm == NULL) 644 if (per_pwrdm == NULL)
645 pr_err("Failed to get per_pwrdm\n"); 645 pr_err("Failed to get per_pwrdm\n");
646 646
647 gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm"); 647 gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
648 if (gfx_l3_clkdm == NULL) 648 if (gfx_l3_clkdm == NULL)
649 pr_err("Failed to get gfx_l3_clkdm\n"); 649 pr_err("Failed to get gfx_l3_clkdm\n");
650 650
651 gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm"); 651 gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
652 if (gfx_l4ls_clkdm == NULL) 652 if (gfx_l4ls_clkdm == NULL)
653 pr_err("Failed to get gfx_l4ls_gfx_clkdm\n"); 653 pr_err("Failed to get gfx_l4ls_gfx_clkdm\n");
654 654
655 mpu_dev = omap_device_get_by_hwmod_name("mpu"); 655 mpu_dev = omap_device_get_by_hwmod_name("mpu");
656 656
657 if (!mpu_dev) { 657 if (!mpu_dev) {
658 pr_warning("%s: unable to get the mpu device\n", __func__); 658 pr_warning("%s: unable to get the mpu device\n", __func__);
659 return -EINVAL; 659 return -EINVAL;
660 } 660 }
661 661
662 ret = wkup_m3_init(); 662 ret = wkup_m3_init();
663 663
664 if (ret) { 664 if (ret) {
665 pr_err("Could not initialise WKUP_M3. " 665 pr_err("Could not initialise WKUP_M3. "
666 "Power management will be compromised\n"); 666 "Power management will be compromised\n");
667 enable_deep_sleep = false; 667 enable_deep_sleep = false;
668 } 668 }
669 669
670 if (enable_deep_sleep) 670 if (enable_deep_sleep)
671 suspend_set_ops(&am33xx_pm_ops); 671 suspend_set_ops(&am33xx_pm_ops);
672 #endif /* CONFIG_SUSPEND */ 672 #endif /* CONFIG_SUSPEND */
673 673
674 return ret; 674 return ret;
675 } 675 }
676 late_initcall(am33xx_pm_init); 676 late_initcall(am33xx_pm_init);
677 677