Eric Lee / linux-smarc-t335x-v3.2

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Commit 4c10c937cc2eb197db565392db91d429eec71176

Authored by Linus Torvalds
2 parents 9bb676966a 950f564b70
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-next-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-next-2.6: (49 commits)
  drivers/ide: Fix continuation line formats
  ide: fixed section mismatch warning in cmd640.c
  ide: ide_timing_compute() fixup
  ide: make ide_get_best_pio_mode() static
  via82cxxx: use ->pio_mode value to determine pair device speed
  tx493xide: use ->pio_mode value to determine pair device speed
  siimage: use ->pio_mode value to determine pair device speed
  palm_bk3710: use ->pio_mode value to determine pair device speed
  it821x: use ->pio_mode value to determine pair device speed
  cs5536: use ->pio_mode value to determine pair device speed
  cs5535: use ->pio_mode value to determine pair device speed
  cmd64x: fix handling of address setup timings
  amd74xx: use ->pio_mode value to determine pair device speed
  alim15x3: fix handling of UDMA enable bit
  alim15x3: fix handling of DMA timings
  alim15x3: fix handling of command timings
  alim15x3: fix handling of address setup timings
  ide-timings: use ->pio_mode value to determine fastest PIO speed
  ide: change ->set_dma_mode method parameters
  ide: change ->set_pio_mode method parameters
  ...

Showing 52 changed files Side-by-side Diff

Documentation/cdrom/ide-cd
Diff comments   View file @ 4c10c93
... ... @@ -159,42 +159,7 @@
159 159 to change. If the slot number is -1, the drive is unloaded.
160 160  
161 161  
162   -4. Compilation options
163   -----------------------
164   -
165   -There are a few additional options which can be set when compiling the
166   -driver. Most people should not need to mess with any of these; they
167   -are listed here simply for completeness. A compilation option can be
168   -enabled by adding a line of the form `#define <option> 1' to the top
169   -of ide-cd.c. All these options are disabled by default.
170   -
171   -VERBOSE_IDE_CD_ERRORS
172   - If this is set, ATAPI error codes will be translated into textual
173   - descriptions. In addition, a dump is made of the command which
174   - provoked the error. This is off by default to save the memory used
175   - by the (somewhat long) table of error descriptions.
176   -
177   -STANDARD_ATAPI
178   - If this is set, the code needed to deal with certain drives which do
179   - not properly implement the ATAPI spec will be disabled. If you know
180   - your drive implements ATAPI properly, you can turn this on to get a
181   - slightly smaller kernel.
182   -
183   -NO_DOOR_LOCKING
184   - If this is set, the driver will never attempt to lock the door of
185   - the drive.
186   -
187   -CDROM_NBLOCKS_BUFFER
188   - This sets the size of the buffer to be used for a CDROMREADAUDIO
189   - ioctl. The default is 8.
190   -
191   -TEST
192   - This currently enables an additional ioctl which enables a user-mode
193   - program to execute an arbitrary packet command. See the source for
194   - details. This should be left off unless you know what you're doing.
195   -
196   -
197   -5. Common problems
  162 +4. Common problems
198 163 ------------------
199 164  
200 165 This section discusses some common problems encountered when trying to
... ... @@ -371,7 +336,7 @@
371 336 expense of low system performance.
372 337  
373 338  
374   -6. cdchange.c
  339 +5. cdchange.c
375 340 -------------
376 341  
377 342 /*
drivers/ide/aec62xx.c
Diff comments   View file @ 4c10c93
... ... @@ -81,15 +81,15 @@
81 81 return chipset_table->ultra_settings;
82 82 }
83 83  
84   -static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
  84 +static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85 85 {
86   - ide_hwif_t *hwif = drive->hwif;
87 86 struct pci_dev *dev = to_pci_dev(hwif->dev);
88 87 struct ide_host *host = pci_get_drvdata(dev);
89 88 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
90 89 u16 d_conf = 0;
91 90 u8 ultra = 0, ultra_conf = 0;
92 91 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
  92 + const u8 speed = drive->dma_mode;
93 93 unsigned long flags;
94 94  
95 95 local_irq_save(flags);
96 96  
97 97  
... ... @@ -109,15 +109,15 @@
109 109 local_irq_restore(flags);
110 110 }
111 111  
112   -static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
  112 +static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
113 113 {
114   - ide_hwif_t *hwif = drive->hwif;
115 114 struct pci_dev *dev = to_pci_dev(hwif->dev);
116 115 struct ide_host *host = pci_get_drvdata(dev);
117 116 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
118 117 u8 unit = drive->dn & 1;
119 118 u8 tmp1 = 0, tmp2 = 0;
120 119 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
  120 + const u8 speed = drive->dma_mode;
121 121 unsigned long flags;
122 122  
123 123 local_irq_save(flags);
124 124  
... ... @@ -134,9 +134,10 @@
134 134 local_irq_restore(flags);
135 135 }
136 136  
137   -static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
  137 +static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
138 138 {
139   - drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0);
  139 + drive->dma_mode = drive->pio_mode;
  140 + hwif->port_ops->set_dma_mode(hwif, drive);
140 141 }
141 142  
142 143 static int init_chipset_aec62xx(struct pci_dev *dev)
drivers/ide/ali14xx.c
Diff comments   View file @ 4c10c93
... ... @@ -109,13 +109,14 @@
109 109 * This function computes timing parameters
110 110 * and sets controller registers accordingly.
111 111 */
112   -static void ali14xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
  112 +static void ali14xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
113 113 {
114 114 int driveNum;
115 115 int time1, time2;
116 116 u8 param1, param2, param3, param4;
117 117 unsigned long flags;
118 118 int bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
  119 + const u8 pio = drive->pio_mode - XFER_PIO_0;
119 120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
120 121  
121 122 /* calculate timing, according to PIO mode */
drivers/ide/alim15x3.c
Diff comments   View file @ 4c10c93
... ... @@ -8,7 +8,7 @@
8 8 * Copyright (C) 2002 Alan Cox
9 9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
10 10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11   - * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
  11 + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
12 12 *
13 13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 14 *
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
23 23  
... ... @@ -48,61 +48,84 @@
48 48 static u8 chip_is_1543c_e;
49 49 static struct pci_dev *isa_dev;
50 50  
  51 +static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on)
  52 +{
  53 + struct pci_dev *pdev = to_pci_dev(hwif->dev);
  54 + int pio_fifo = 0x54 + hwif->channel;
  55 + u8 fifo;
  56 + int shift = 4 * (drive->dn & 1);
  57 +
  58 + pci_read_config_byte(pdev, pio_fifo, &fifo);
  59 + fifo &= ~(0x0F << shift);
  60 + fifo |= (on << shift);
  61 + pci_write_config_byte(pdev, pio_fifo, fifo);
  62 +}
  63 +
  64 +static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive,
  65 + struct ide_timing *t, u8 ultra)
  66 +{
  67 + struct pci_dev *dev = to_pci_dev(hwif->dev);
  68 + int port = hwif->channel ? 0x5c : 0x58;
  69 + int udmat = 0x56 + hwif->channel;
  70 + u8 unit = drive->dn & 1, udma;
  71 + int shift = 4 * unit;
  72 +
  73 + /* Set up the UDMA */
  74 + pci_read_config_byte(dev, udmat, &udma);
  75 + udma &= ~(0x0F << shift);
  76 + udma |= ultra << shift;
  77 + pci_write_config_byte(dev, udmat, udma);
  78 +
  79 + if (t == NULL)
  80 + return;
  81 +
  82 + t->setup = clamp_val(t->setup, 1, 8) & 7;
  83 + t->act8b = clamp_val(t->act8b, 1, 8) & 7;
  84 + t->rec8b = clamp_val(t->rec8b, 1, 16) & 15;
  85 + t->active = clamp_val(t->active, 1, 8) & 7;
  86 + t->recover = clamp_val(t->recover, 1, 16) & 15;
  87 +
  88 + pci_write_config_byte(dev, port, t->setup);
  89 + pci_write_config_byte(dev, port + 1, (t->act8b << 4) | t->rec8b);
  90 + pci_write_config_byte(dev, port + unit + 2,
  91 + (t->active << 4) | t->recover);
  92 +}
  93 +
51 94 /**
52 95 * ali_set_pio_mode - set host controller for PIO mode
  96 + * @hwif: port
53 97 * @drive: drive
54   - * @pio: PIO mode number
55 98 *
56 99 * Program the controller for the given PIO mode.
57 100 */
58 101  
59   -static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
  102 +static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
60 103 {
61   - ide_hwif_t *hwif = drive->hwif;
62   - struct pci_dev *dev = to_pci_dev(hwif->dev);
63   - struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
64   - int s_time = t->setup, a_time = t->active, c_time = t->cycle;
65   - u8 s_clc, a_clc, r_clc;
66   - unsigned long flags;
  104 + ide_drive_t *pair = ide_get_pair_dev(drive);
67 105 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
68   - int port = hwif->channel ? 0x5c : 0x58;
69   - int portFIFO = hwif->channel ? 0x55 : 0x54;
70   - u8 cd_dma_fifo = 0, unit = drive->dn & 1;
  106 + unsigned long T = 1000000 / bus_speed; /* PCI clock based */
  107 + struct ide_timing t;
71 108  
72   - if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
73   - s_clc = 0;
74   - if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
75   - a_clc = 0;
  109 + ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
  110 + if (pair) {
  111 + struct ide_timing p;
76 112  
77   - if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
78   - r_clc = 1;
79   - } else {
80   - if (r_clc >= 16)
81   - r_clc = 0;
  113 + ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
  114 + ide_timing_merge(&p, &t, &t,
  115 + IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  116 + if (pair->dma_mode) {
  117 + ide_timing_compute(pair, pair->dma_mode, &p, T, 1);
  118 + ide_timing_merge(&p, &t, &t,
  119 + IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  120 + }
82 121 }
83   - local_irq_save(flags);
84   -
  122 +
85 123 /*
86 124 * PIO mode => ATA FIFO on, ATAPI FIFO off
87 125 */
88   - pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
89   - if (drive->media==ide_disk) {
90   - if (unit) {
91   - pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
92   - } else {
93   - pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
94   - }
95   - } else {
96   - if (unit) {
97   - pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
98   - } else {
99   - pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
100   - }
101   - }
102   -
103   - pci_write_config_byte(dev, port, s_clc);
104   - pci_write_config_byte(dev, port + unit + 2, (a_clc << 4) | r_clc);
105   - local_irq_restore(flags);
  126 + ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00);
  127 +
  128 + ali_program_timings(hwif, drive, &t, 0);
106 129 }
107 130  
108 131 /**
109 132  
110 133  
111 134  
112 135  
113 136  
114 137  
115 138  
116 139  
117 140  
... ... @@ -132,44 +155,42 @@
132 155  
133 156 /**
134 157 * ali_set_dma_mode - set host controller for DMA mode
  158 + * @hwif: port
135 159 * @drive: drive
136   - * @speed: DMA mode
137 160 *
138 161 * Configure the hardware for the desired IDE transfer mode.
139 162 */
140 163  
141   -static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
  164 +static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
142 165 {
143   - ide_hwif_t *hwif = drive->hwif;
  166 + static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD };
144 167 struct pci_dev *dev = to_pci_dev(hwif->dev);
145   - u8 speed1 = speed;
146   - u8 unit = drive->dn & 1;
  168 + ide_drive_t *pair = ide_get_pair_dev(drive);
  169 + int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  170 + unsigned long T = 1000000 / bus_speed; /* PCI clock based */
  171 + const u8 speed = drive->dma_mode;
147 172 u8 tmpbyte = 0x00;
148   - int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
  173 + struct ide_timing t;
149 174  
150   - if (speed == XFER_UDMA_6)
151   - speed1 = 0x47;
152   -
153 175 if (speed < XFER_UDMA_0) {
154   - u8 ultra_enable = (unit) ? 0x7f : 0xf7;
155   - /*
156   - * clear "ultra enable" bit
157   - */
158   - pci_read_config_byte(dev, m5229_udma, &tmpbyte);
159   - tmpbyte &= ultra_enable;
160   - pci_write_config_byte(dev, m5229_udma, tmpbyte);
  176 + ide_timing_compute(drive, drive->dma_mode, &t, T, 1);
  177 + if (pair) {
  178 + struct ide_timing p;
161 179  
162   - /*
163   - * FIXME: Oh, my... DMA timings are never set.
164   - */
  180 + ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
  181 + ide_timing_merge(&p, &t, &t,
  182 + IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  183 + if (pair->dma_mode) {
  184 + ide_timing_compute(pair, pair->dma_mode,
  185 + &p, T, 1);
  186 + ide_timing_merge(&p, &t, &t,
  187 + IDE_TIMING_SETUP | IDE_TIMING_8BIT);
  188 + }
  189 + }
  190 + ali_program_timings(hwif, drive, &t, 0);
165 191 } else {
166   - pci_read_config_byte(dev, m5229_udma, &tmpbyte);
167   - tmpbyte &= (0x0f << ((1-unit) << 2));
168   - /*
169   - * enable ultra dma and set timing
170   - */
171   - tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
172   - pci_write_config_byte(dev, m5229_udma, tmpbyte);
  192 + ali_program_timings(hwif, drive, NULL,
  193 + udma_timing[speed - XFER_UDMA_0]);
173 194 if (speed >= XFER_UDMA_3) {
174 195 pci_read_config_byte(dev, 0x4b, &tmpbyte);
175 196 tmpbyte |= 1;
176 197  
177 198  
... ... @@ -355,19 +376,13 @@
355 376 *
356 377 * This checks if the controller and the cable are capable
357 378 * of UDMA66 transfers. It doesn't check the drives.
358   - * But see note 2 below!
359   - *
360   - * FIXME: frobs bits that are not defined on newer ALi devicea
361 379 */
362 380  
363 381 static u8 ali_cable_detect(ide_hwif_t *hwif)
364 382 {
365 383 struct pci_dev *dev = to_pci_dev(hwif->dev);
366   - unsigned long flags;
367 384 u8 cbl = ATA_CBL_PATA40, tmpbyte;
368 385  
369   - local_irq_save(flags);
370   -
371 386 if (m5229_revision >= 0xC2) {
372 387 /*
373 388 * m5229 80-pin cable detection (from Host View)
... ... @@ -387,8 +402,6 @@
387 402 }
388 403 }
389 404  
390   - local_irq_restore(flags);
391   -
392 405 return cbl;
393 406 }
394 407  
... ... @@ -584,7 +597,7 @@
584 597 module_init(ali15x3_ide_init);
585 598 module_exit(ali15x3_ide_exit);
586 599  
587   -MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
  600 +MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz");
588 601 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
589 602 MODULE_LICENSE("GPL");
drivers/ide/amd74xx.c
Diff comments   View file @ 4c10c93
... ... @@ -3,7 +3,7 @@
3 3 * IDE driver for Linux.
4 4 *
5 5 * Copyright (c) 2000-2002 Vojtech Pavlik
6   - * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
  6 + * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
7 7 *
8 8 * Based on the work of:
9 9 * Andre Hedrick
... ... @@ -70,7 +70,8 @@
70 70 default: return;
71 71 }
72 72  
73   - pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
  73 + if (timing->udma)
  74 + pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t);
74 75 }
75 76  
76 77 /*
77 78  
78 79  
... ... @@ -78,14 +79,14 @@
78 79 * to a desired transfer mode. It also can be called by upper layers.
79 80 */
80 81  
81   -static void amd_set_drive(ide_drive_t *drive, const u8 speed)
  82 +static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
82 83 {
83   - ide_hwif_t *hwif = drive->hwif;
84 84 struct pci_dev *dev = to_pci_dev(hwif->dev);
85 85 ide_drive_t *peer = ide_get_pair_dev(drive);
86 86 struct ide_timing t, p;
87 87 int T, UT;
88 88 u8 udma_mask = hwif->ultra_mask;
  89 + const u8 speed = drive->dma_mode;
89 90  
90 91 T = 1000000000 / amd_clock;
91 92 UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
... ... @@ -93,7 +94,7 @@
93 94 ide_timing_compute(drive, speed, &t, T, UT);
94 95  
95 96 if (peer) {
96   - ide_timing_compute(peer, peer->current_speed, &p, T, UT);
  97 + ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
97 98 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
98 99 }
99 100  
100 101  
... ... @@ -107,9 +108,10 @@
107 108 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
108 109 */
109 110  
110   -static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
  111 +static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
111 112 {
112   - amd_set_drive(drive, XFER_PIO_0 + pio);
  113 + drive->dma_mode = drive->pio_mode;
  114 + amd_set_drive(hwif, drive);
113 115 }
114 116  
115 117 static void amd7409_cable_detect(struct pci_dev *dev)
... ... @@ -340,7 +342,7 @@
340 342 module_init(amd74xx_ide_init);
341 343 module_exit(amd74xx_ide_exit);
342 344  
343   -MODULE_AUTHOR("Vojtech Pavlik");
  345 +MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz");
344 346 MODULE_DESCRIPTION("AMD PCI IDE driver");
345 347 MODULE_LICENSE("GPL");
drivers/ide/at91_ide.c
Diff comments   View file @ 4c10c93
... ... @@ -172,11 +172,12 @@
172 172 leave_16bit(chipselect, mode);
173 173 }
174 174  
175   -static void at91_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
  175 +static void at91_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
176 176 {
177 177 struct ide_timing *timing;
178   - u8 chipselect = drive->hwif->select_data;
  178 + u8 chipselect = hwif->select_data;
179 179 int use_iordy = 0;
  180 + const u8 pio = drive->pio_mode - XFER_PIO_0;
180 181  
181 182 pdbg("chipselect %u pio %u\n", chipselect, pio);
182 183  
drivers/ide/atiixp.c
Diff comments   View file @ 4c10c93
... ... @@ -42,19 +42,20 @@
42 42  
43 43 /**
44 44 * atiixp_set_pio_mode - set host controller for PIO mode
  45 + * @hwif: port
45 46 * @drive: drive
46   - * @pio: PIO mode number
47 47 *
48 48 * Set the interface PIO mode.
49 49 */
50 50  
51   -static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
  51 +static void atiixp_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
52 52 {
53   - struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  53 + struct pci_dev *dev = to_pci_dev(hwif->dev);
54 54 unsigned long flags;
55 55 int timing_shift = (drive->dn ^ 1) * 8;
56 56 u32 pio_timing_data;
57 57 u16 pio_mode_data;
  58 + const u8 pio = drive->pio_mode - XFER_PIO_0;
58 59  
59 60 spin_lock_irqsave(&atiixp_lock, flags);
60 61  
61 62  
62 63  
63 64  
64 65  
... ... @@ -74,21 +75,22 @@
74 75  
75 76 /**
76 77 * atiixp_set_dma_mode - set host controller for DMA mode
  78 + * @hwif: port
77 79 * @drive: drive
78   - * @speed: DMA mode
79 80 *
80 81 * Set a ATIIXP host controller to the desired DMA mode. This involves
81 82 * programming the right timing data into the PCI configuration space.
82 83 */
83 84  
84   -static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
  85 +static void atiixp_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85 86 {
86   - struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  87 + struct pci_dev *dev = to_pci_dev(hwif->dev);
87 88 unsigned long flags;
88 89 int timing_shift = (drive->dn ^ 1) * 8;
89 90 u32 tmp32;
90 91 u16 tmp16;
91 92 u16 udma_ctl = 0;
  93 + const u8 speed = drive->dma_mode;
92 94  
93 95 spin_lock_irqsave(&atiixp_lock, flags);
94 96  
drivers/ide/au1xxx-ide.c
Diff comments   View file @ 4c10c93
... ... @@ -99,12 +99,11 @@
99 99 }
100 100 #endif
101 101  
102   -static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
  102 +static void au1xxx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
103 103 {
104 104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
105 105  
106   - /* set pio mode! */
107   - switch(pio) {
  106 + switch (drive->pio_mode - XFER_PIO_0) {
108 107 case 0:
109 108 mem_sttime = SBC_IDE_TIMING(PIO0);
110 109  
111 110  
... ... @@ -161,11 +160,11 @@
161 160 au_writel(mem_stcfg,MEM_STCFG2);
162 161 }
163 162  
164   -static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
  163 +static void auide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
165 164 {
166 165 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
167 166  
168   - switch(speed) {
  167 + switch (drive->dma_mode) {
169 168 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170 169 case XFER_MW_DMA_2:
171 170 mem_sttime = SBC_IDE_TIMING(MDMA2);
... ... @@ -297,8 +296,8 @@
297 296 */
298 297 drive->waiting_for_dma++;
299 298 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
300   - printk(KERN_WARNING "%s: timeout waiting for ddma to \
301   - complete\n", drive->name);
  299 + printk(KERN_WARNING "%s: timeout waiting for ddma to complete\n",
  300 + drive->name);
302 301 return 1;
303 302 }
304 303 udelay(10);
drivers/ide/cmd640.c
Diff comments   View file @ 4c10c93
... ... @@ -572,9 +572,10 @@
572 572 program_drive_counts(drive, index);
573 573 }
574 574  
575   -static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio)
  575 +static void cmd640_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
576 576 {
577 577 unsigned int index = 0, cycle_time;
  578 + const u8 pio = drive->pio_mode - XFER_PIO_0;
578 579 u8 b;
579 580  
580 581 switch (pio) {
... ... @@ -605,7 +606,7 @@
605 606 }
606 607 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
607 608  
608   -static void cmd640_init_dev(ide_drive_t *drive)
  609 +static void __init cmd640_init_dev(ide_drive_t *drive)
609 610 {
610 611 unsigned int i = drive->hwif->channel * 2 + (drive->dn & 1);
611 612  
drivers/ide/cmd64x.c
Diff comments   View file @ 4c10c93
... ... @@ -7,6 +7,7 @@
7 7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 8 *
9 9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
  10 + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
10 11 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
11 12 */
12 13  
13 14  
14 15  
15 16  
16 17  
17 18  
18 19  
19 20  
20 21  
21 22  
22 23  
... ... @@ -50,73 +51,43 @@
50 51 #define UDIDETCR1 0x7B
51 52 #define DTPR1 0x7C
52 53  
53   -static u8 quantize_timing(int timing, int quant)
  54 +static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
54 55 {
55   - return (timing + quant - 1) / quant;
56   -}
57   -
58   -/*
59   - * This routine calculates active/recovery counts and then writes them into
60   - * the chipset registers.
61   - */
62   -static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
63   -{
  56 + ide_hwif_t *hwif = drive->hwif;
64 57 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
65   - int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
66   - u8 cycle_count, active_count, recovery_count, drwtim;
  58 + int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  59 + const unsigned long T = 1000000 / bus_speed;
67 60 static const u8 recovery_values[] =
68 61 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
  62 + static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
  63 + static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
69 64 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
  65 + struct ide_timing t;
  66 + u8 arttim = 0;
70 67  
71   - cycle_count = quantize_timing( cycle_time, clock_time);
72   - active_count = quantize_timing(active_time, clock_time);
73   - recovery_count = cycle_count - active_count;
  68 + ide_timing_compute(drive, mode, &t, T, 0);
74 69  
75 70 /*
76 71 * In case we've got too long recovery phase, try to lengthen
77 72 * the active phase
78 73 */
79   - if (recovery_count > 16) {
80   - active_count += recovery_count - 16;
81   - recovery_count = 16;
  74 + if (t.recover > 16) {
  75 + t.active += t.recover - 16;
  76 + t.recover = 16;
82 77 }
83   - if (active_count > 16) /* shouldn't actually happen... */
84   - active_count = 16;
  78 + if (t.active > 16) /* shouldn't actually happen... */
  79 + t.active = 16;
85 80  
86 81 /*
87 82 * Convert values to internal chipset representation
88 83 */
89   - recovery_count = recovery_values[recovery_count];
90   - active_count &= 0x0f;
  84 + t.recover = recovery_values[t.recover];
  85 + t.active &= 0x0f;
91 86  
92 87 /* Program the active/recovery counts into the DRWTIM register */
93   - drwtim = (active_count << 4) | recovery_count;
94   - (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
95   -}
  88 + pci_write_config_byte(dev, drwtim_regs[drive->dn],
  89 + (t.active << 4) | t.recover);
96 90  
97   -/*
98   - * This routine writes into the chipset registers
99   - * PIO setup/active/recovery timings.
100   - */
101   -static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
102   -{
103   - ide_hwif_t *hwif = drive->hwif;
104   - struct pci_dev *dev = to_pci_dev(hwif->dev);
105   - struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
106   - unsigned long setup_count;
107   - unsigned int cycle_time;
108   - u8 arttim = 0;
109   -
110   - static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
111   - static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
112   -
113   - cycle_time = ide_pio_cycle_time(drive, pio);
114   -
115   - program_cycle_times(drive, cycle_time, t->active);
116   -
117   - setup_count = quantize_timing(t->setup,
118   - 1000 / (ide_pci_clk ? ide_pci_clk : 33));
119   -
120 91 /*
121 92 * The primary channel has individual address setup timing registers
122 93 * for each drive and the hardware selects the slowest timing itself.
123 94  
124 95  
... ... @@ -126,15 +97,21 @@
126 97 if (hwif->channel) {
127 98 ide_drive_t *pair = ide_get_pair_dev(drive);
128 99  
129   - ide_set_drivedata(drive, (void *)setup_count);
  100 + if (pair) {
  101 + struct ide_timing tp;
130 102  
131   - if (pair)
132   - setup_count = max_t(u8, setup_count,
133   - (unsigned long)ide_get_drivedata(pair));
  103 + ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
  104 + ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
  105 + if (pair->dma_mode) {
  106 + ide_timing_compute(pair, pair->dma_mode,
  107 + &tp, T, 0);
  108 + ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
  109 + }
  110 + }
134 111 }
135 112  
136   - if (setup_count > 5) /* shouldn't actually happen... */
137   - setup_count = 5;
  113 + if (t.setup > 5) /* shouldn't actually happen... */
  114 + t.setup = 5;
138 115  
139 116 /*
140 117 * Program the address setup clocks into the ARTTIM registers.
... ... @@ -144,7 +121,7 @@
144 121 if (hwif->channel)
145 122 arttim &= ~ARTTIM23_INTR_CH1;
146 123 arttim &= ~0xc0;
147   - arttim |= setup_values[setup_count];
  124 + arttim |= setup_values[t.setup];
148 125 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
149 126 }
150 127  
151 128  
... ... @@ -153,8 +130,10 @@
153 130 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
154 131 */
155 132  
156   -static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
  133 +static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
157 134 {
  135 + const u8 pio = drive->pio_mode - XFER_PIO_0;
  136 +
158 137 /*
159 138 * Filter out the prefetch control values
160 139 * to prevent PIO5 from being programmed
161 140  
162 141  
163 142  
164 143  
... ... @@ -162,20 +141,18 @@
162 141 if (pio == 8 || pio == 9)
163 142 return;
164 143  
165   - cmd64x_tune_pio(drive, pio);
  144 + cmd64x_program_timings(drive, XFER_PIO_0 + pio);
166 145 }
167 146  
168   -static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
  147 +static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
169 148 {
170   - ide_hwif_t *hwif = drive->hwif;
171 149 struct pci_dev *dev = to_pci_dev(hwif->dev);
172 150 u8 unit = drive->dn & 0x01;
173 151 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
  152 + const u8 speed = drive->dma_mode;
174 153  
175   - if (speed >= XFER_SW_DMA_0) {
176   - (void) pci_read_config_byte(dev, pciU, &regU);
177   - regU &= ~(unit ? 0xCA : 0x35);
178   - }
  154 + pci_read_config_byte(dev, pciU, &regU);
  155 + regU &= ~(unit ? 0xCA : 0x35);
179 156  
180 157 switch(speed) {
181 158 case XFER_UDMA_5:
182 159  
183 160  
184 161  
... ... @@ -197,18 +174,13 @@
197 174 regU |= unit ? 0xC2 : 0x31;
198 175 break;
199 176 case XFER_MW_DMA_2:
200   - program_cycle_times(drive, 120, 70);
201   - break;
202 177 case XFER_MW_DMA_1:
203   - program_cycle_times(drive, 150, 80);
204   - break;
205 178 case XFER_MW_DMA_0:
206   - program_cycle_times(drive, 480, 215);
  179 + cmd64x_program_timings(drive, speed);
207 180 break;
208 181 }
209 182  
210   - if (speed >= XFER_SW_DMA_0)
211   - (void) pci_write_config_byte(dev, pciU, regU);
  183 + pci_write_config_byte(dev, pciU, regU);
212 184 }
213 185  
214 186 static void cmd648_clear_irq(ide_drive_t *drive)
... ... @@ -471,7 +443,7 @@
471 443 module_init(cmd64x_ide_init);
472 444 module_exit(cmd64x_ide_exit);
473 445  
474   -MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
  446 +MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
475 447 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
476 448 MODULE_LICENSE("GPL");
drivers/ide/cs5520.c
Diff comments   View file @ 4c10c93
... ... @@ -57,11 +57,11 @@
57 57 {1, 2, 1}
58 58 };
59 59  
60   -static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
  60 +static void cs5520_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
61 61 {
62   - ide_hwif_t *hwif = drive->hwif;
63 62 struct pci_dev *pdev = to_pci_dev(hwif->dev);
64 63 int controller = drive->dn > 1 ? 1 : 0;
  64 + const u8 pio = drive->pio_mode - XFER_PIO_0;
65 65  
66 66 /* 8bit CAT/CRT - 8bit command timing for channel */
67 67 pci_write_config_byte(pdev, 0x62 + controller,
68 68  
... ... @@ -81,11 +81,12 @@
81 81 (cs5520_pio_clocks[pio].assert));
82 82 }
83 83  
84   -static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed)
  84 +static void cs5520_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85 85 {
86 86 printk(KERN_ERR "cs55x0: bad ide timing.\n");
87 87  
88   - cs5520_set_pio_mode(drive, 0);
  88 + drive->pio_mode = XFER_PIO_0 + 0;
  89 + cs5520_set_pio_mode(hwif, drive);
89 90 }
90 91  
91 92 static const struct ide_port_ops cs5520_port_ops = {
drivers/ide/cs5530.c
Diff comments   View file @ 4c10c93
... ... @@ -41,8 +41,8 @@
41 41  
42 42 /**
43 43 * cs5530_set_pio_mode - set host controller for PIO mode
  44 + * @hwif: port
44 45 * @drive: drive
45   - * @pio: PIO mode number
46 46 *
47 47 * Handles setting of PIO mode for the chipset.
48 48 *
49 49  
50 50  
... ... @@ -50,10 +50,11 @@
50 50 * will have valid default PIO timings set up before we get here.
51 51 */
52 52  
53   -static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
  53 +static void cs5530_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
54 54 {
55   - unsigned long basereg = CS5530_BASEREG(drive->hwif);
  55 + unsigned long basereg = CS5530_BASEREG(hwif);
56 56 unsigned int format = (inl(basereg + 4) >> 31) & 1;
  57 + const u8 pio = drive->pio_mode - XFER_PIO_0;
57 58  
58 59 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
59 60 }
60 61  
... ... @@ -99,12 +100,12 @@
99 100 return mask;
100 101 }
101 102  
102   -static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
  103 +static void cs5530_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
103 104 {
104 105 unsigned long basereg;
105 106 unsigned int reg, timings = 0;
106 107  
107   - switch (mode) {
  108 + switch (drive->dma_mode) {
108 109 case XFER_UDMA_0: timings = 0x00921250; break;
109 110 case XFER_UDMA_1: timings = 0x00911140; break;
110 111 case XFER_UDMA_2: timings = 0x00911030; break;
... ... @@ -112,7 +113,7 @@
112 113 case XFER_MW_DMA_1: timings = 0x00012121; break;
113 114 case XFER_MW_DMA_2: timings = 0x00002020; break;
114 115 }
115   - basereg = CS5530_BASEREG(drive->hwif);
  116 + basereg = CS5530_BASEREG(hwif);
116 117 reg = inl(basereg + 4); /* get drive0 config register */
117 118 timings |= reg & 0x80000000; /* preserve PIO format bit */
118 119 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
drivers/ide/cs5535.c
Diff comments   View file @ 4c10c93
... ... @@ -86,7 +86,7 @@
86 86 cmd = pioa = speed - XFER_PIO_0;
87 87  
88 88 if (pair) {
89   - u8 piob = ide_get_best_pio_mode(pair, 255, 4);
  89 + u8 piob = pair->pio_mode - XFER_PIO_0;
90 90  
91 91 if (piob < cmd)
92 92 cmd = piob;
93 93  
94 94  
95 95  
96 96  
97 97  
98 98  
99 99  
... ... @@ -129,28 +129,28 @@
129 129  
130 130 /**
131 131 * cs5535_set_dma_mode - set host controller for DMA mode
  132 + * @hwif: port
132 133 * @drive: drive
133   - * @speed: DMA mode
134 134 *
135 135 * Programs the chipset for DMA mode.
136 136 */
137 137  
138   -static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
  138 +static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
139 139 {
140   - cs5535_set_speed(drive, speed);
  140 + cs5535_set_speed(drive, drive->dma_mode);
141 141 }
142 142  
143 143 /**
144 144 * cs5535_set_pio_mode - set host controller for PIO mode
  145 + * @hwif: port
145 146 * @drive: drive
146   - * @pio: PIO mode number
147 147 *
148 148 * A callback from the upper layers for PIO-only tuning.
149 149 */
150 150  
151   -static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
  151 +static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
152 152 {
153   - cs5535_set_speed(drive, XFER_PIO_0 + pio);
  153 + cs5535_set_speed(drive, drive->pio_mode);
154 154 }
155 155  
156 156 static u8 cs5535_cable_detect(ide_hwif_t *hwif)
drivers/ide/cs5536.c
Diff comments   View file @ 4c10c93
... ... @@ -125,11 +125,11 @@
125 125  
126 126 /**
127 127 * cs5536_set_pio_mode - PIO timing setup
  128 + * @hwif: ATA port
128 129 * @drive: ATA device
129   - * @pio: PIO mode number
130 130 */
131 131  
132   -static void cs5536_set_pio_mode(ide_drive_t *drive, const u8 pio)
  132 +static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
133 133 {
134 134 static const u8 drv_timings[5] = {
135 135 0x98, 0x55, 0x32, 0x21, 0x20,
136 136  
137 137  
... ... @@ -143,15 +143,16 @@
143 143 0x99, 0x92, 0x90, 0x22, 0x20,
144 144 };
145 145  
146   - struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
  146 + struct pci_dev *pdev = to_pci_dev(hwif->dev);
147 147 ide_drive_t *pair = ide_get_pair_dev(drive);
148 148 int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
149 149 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
150 150 u32 cast;
  151 + const u8 pio = drive->pio_mode - XFER_PIO_0;
151 152 u8 cmd_pio = pio;
152 153  
153 154 if (pair)
154   - cmd_pio = min(pio, ide_get_best_pio_mode(pair, 255, 4));
  155 + cmd_pio = min_t(u8, pio, pair->pio_mode - XFER_PIO_0);
155 156  
156 157 timings &= (IDE_DRV_MASK << 8);
157 158 timings |= drv_timings[pio];
158 159  
159 160  
... ... @@ -172,11 +173,11 @@
172 173  
173 174 /**
174 175 * cs5536_set_dma_mode - DMA timing setup
  176 + * @hwif: ATA port
175 177 * @drive: ATA device
176   - * @mode: DMA mode
177 178 */
178 179  
179   -static void cs5536_set_dma_mode(ide_drive_t *drive, const u8 mode)
  180 +static void cs5536_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
180 181 {
181 182 static const u8 udma_timings[6] = {
182 183 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
183 184  
... ... @@ -186,10 +187,11 @@
186 187 0x67, 0x21, 0x20,
187 188 };
188 189  
189   - struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
  190 + struct pci_dev *pdev = to_pci_dev(hwif->dev);
190 191 int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
191 192 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
192 193 u32 etc;
  194 + const u8 mode = drive->dma_mode;
193 195  
194 196 cs5536_read(pdev, ETC, &etc);
195 197  
drivers/ide/cy82c693.c
Diff comments   View file @ 4c10c93
1 1 /*
2 2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
3 3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
  4 + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
4 5 *
5 6 * CYPRESS CY82C693 chipset IDE controller
6 7 *
7 8 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
8   - * Writing the driver was quite simple, since most of the job is
9   - * done by the generic pci-ide support.
10   - * The hard part was finding the CY82C693's datasheet on Cypress's
11   - * web page :-(. But Altavista solved this problem :-).
12   - *
13   - *
14   - * Notes:
15   - * - I recently got a 16.8G IBM DTTA, so I was able to test it with
16   - * a large and fast disk - the results look great, so I'd say the
17   - * driver is working fine :-)
18   - * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
19   - * - this is my first linux driver, so there's probably a lot of room
20   - * for optimizations and bug fixing, so feel free to do it.
21   - * - if using PIO mode it's a good idea to set the PIO mode and
22   - * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
23   - * - I had some problems with my IBM DHEA with PIO modes < 2
24   - * (lost interrupts) ?????
25   - * - first tests with DMA look okay, they seem to work, but there is a
26   - * problem with sound - the BusMaster IDE TimeOut should fixed this
27   - *
28   - * Ancient History:
29   - * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
30   - * ASK@1999-01-23: v0.33 made a few minor code clean ups
31   - * removed DMA clock speed setting by default
32   - * added boot message
33   - * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
34   - * added support to set DMA Controller Clock Speed
35   - * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
36   - * on some drives.
37   - * ASK@1998-10-29: v0.3 added support to set DMA modes
38   - * ASK@1998-10-28: v0.2 added support to set PIO modes
39   - * ASK@1998-10-27: v0.1 first version - chipset detection
40   - *
41 9 */
42 10  
43 11 #include <linux/module.h>
44 12  
45 13  
46 14  
... ... @@ -81,87 +49,13 @@
81 49 #define CY82_INDEX_CHANNEL1 0x31
82 50 #define CY82_INDEX_TIMEOUT 0x32
83 51  
84   -/* the min and max PCI bus speed in MHz - from datasheet */
85   -#define CY82C963_MIN_BUS_SPEED 25
86   -#define CY82C963_MAX_BUS_SPEED 33
87   -
88   -/* the struct for the PIO mode timings */
89   -typedef struct pio_clocks_s {
90   - u8 address_time; /* Address setup (clocks) */
91   - u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
92   - u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
93   - u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
94   -} pio_clocks_t;
95   -
96 52 /*
97   - * calc clocks using bus_speed
98   - * returns (rounded up) time in bus clocks for time in ns
99   - */
100   -static int calc_clk(int time, int bus_speed)
101   -{
102   - int clocks;
103   -
104   - clocks = (time*bus_speed+999)/1000 - 1;
105   -
106   - if (clocks < 0)
107   - clocks = 0;
108   -
109   - if (clocks > 0x0F)
110   - clocks = 0x0F;
111   -
112   - return clocks;
113   -}
114   -
115   -/*
116   - * compute the values for the clock registers for PIO
117   - * mode and pci_clk [MHz] speed
118   - *
119   - * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
120   - * for mode 3 and 4 drives 8 and 16-bit timings are the same
121   - *
122   - */
123   -static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
124   -{
125   - struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
126   - int clk1, clk2;
127   - int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
128   -
129   - /* we don't check against CY82C693's min and max speed,
130   - * so you can play with the idebus=xx parameter
131   - */
132   -
133   - /* let's calc the address setup time clocks */
134   - p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
135   -
136   - /* let's calc the active and recovery time clocks */
137   - clk1 = calc_clk(t->active, bus_speed);
138   -
139   - /* calc recovery timing */
140   - clk2 = t->cycle - t->active - t->setup;
141   -
142   - clk2 = calc_clk(clk2, bus_speed);
143   -
144   - clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
145   -
146   - /* note: we use the same values for 16bit IOR and IOW
147   - * those are all the same, since I don't have other
148   - * timings than those from ide-lib.c
149   - */
150   -
151   - p_pclk->time_16r = (u8)clk1;
152   - p_pclk->time_16w = (u8)clk1;
153   -
154   - /* what are good values for 8bit ?? */
155   - p_pclk->time_8 = (u8)clk1;
156   -}
157   -
158   -/*
159 53 * set DMA mode a specific channel for CY82C693
160 54 */
161 55  
162   -static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
  56 +static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
163 57 {
164   - ide_hwif_t *hwif = drive->hwif;
  58 + const u8 mode = drive->dma_mode;
165 59 u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
166 60  
167 61 index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
168 62  
169 63  
170 64  
... ... @@ -186,12 +80,14 @@
186 80 outb(data, CY82_DATA_PORT);
187 81 }
188 82  
189   -static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
  83 +static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
190 84 {
191   - ide_hwif_t *hwif = drive->hwif;
192 85 struct pci_dev *dev = to_pci_dev(hwif->dev);
193   - pio_clocks_t pclk;
  86 + int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  87 + const unsigned long T = 1000000 / bus_speed;
194 88 unsigned int addrCtrl;
  89 + struct ide_timing t;
  90 + u8 time_16, time_8;
195 91  
196 92 /* select primary or secondary channel */
197 93 if (hwif->index > 0) { /* drive is on the secondary channel */
198 94  
... ... @@ -204,9 +100,13 @@
204 100 }
205 101 }
206 102  
207   - /* let's calc the values for this PIO mode */
208   - compute_clocks(pio, &pclk);
  103 + ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
209 104  
  105 + time_16 = clamp_val(t.recover - 1, 0, 15) |
  106 + (clamp_val(t.active - 1, 0, 15) << 4);
  107 + time_8 = clamp_val(t.act8b - 1, 0, 15) |
  108 + (clamp_val(t.rec8b - 1, 0, 15) << 4);
  109 +
210 110 /* now let's write the clocks registers */
211 111 if ((drive->dn & 1) == 0) {
212 112 /*
213 113  
... ... @@ -217,13 +117,13 @@
217 117 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
218 118  
219 119 addrCtrl &= (~0xF);
220   - addrCtrl |= (unsigned int)pclk.address_time;
  120 + addrCtrl |= clamp_val(t.setup - 1, 0, 15);
221 121 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
222 122  
223 123 /* now let's set the remaining registers */
224   - pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
225   - pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
226   - pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
  124 + pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
  125 + pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
  126 + pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
227 127 } else {
228 128 /*
229 129 * set slave drive
230 130  
... ... @@ -233,13 +133,13 @@
233 133 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
234 134  
235 135 addrCtrl &= (~0xF0);
236   - addrCtrl |= ((unsigned int)pclk.address_time<<4);
  136 + addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
237 137 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
238 138  
239 139 /* now let's set the remaining registers */
240   - pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
241   - pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
242   - pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
  140 + pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
  141 + pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
  142 + pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
243 143 }
244 144 }
245 145  
... ... @@ -325,7 +225,7 @@
325 225 module_init(cy82c693_ide_init);
326 226 module_exit(cy82c693_ide_exit);
327 227  
328   -MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
  228 +MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
329 229 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
330 230 MODULE_LICENSE("GPL");
drivers/ide/dtc2278.c
Diff comments   View file @ 4c10c93
... ... @@ -68,11 +68,11 @@
68 68  
69 69 static DEFINE_SPINLOCK(dtc2278_lock);
70 70  
71   -static void dtc2278_set_pio_mode(ide_drive_t *drive, const u8 pio)
  71 +static void dtc2278_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
72 72 {
73 73 unsigned long flags;
74 74  
75   - if (pio >= 3) {
  75 + if (drive->pio_mode >= XFER_PIO_3) {
76 76 spin_lock_irqsave(&dtc2278_lock, flags);
77 77 /*
78 78 * This enables PIO mode4 (3?) on the first interface
drivers/ide/hpt366.c
Diff comments   View file @ 4c10c93
... ... @@ -627,14 +627,14 @@
627 627 return info->timings->clock_table[info->clock][i];
628 628 }
629 629  
630   -static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
  630 +static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
631 631 {
632   - ide_hwif_t *hwif = drive->hwif;
633 632 struct pci_dev *dev = to_pci_dev(hwif->dev);
634 633 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
635 634 struct hpt_timings *t = info->timings;
636 635 u8 itr_addr = 0x40 + (drive->dn * 4);
637 636 u32 old_itr = 0;
  637 + const u8 speed = drive->dma_mode;
638 638 u32 new_itr = get_speed_setting(speed, info);
639 639 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
640 640 (speed < XFER_UDMA_0 ? t->dma_mask :
641 641  
... ... @@ -651,9 +651,10 @@
651 651 pci_write_config_dword(dev, itr_addr, new_itr);
652 652 }
653 653  
654   -static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
  654 +static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
655 655 {
656   - hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
  656 + drive->dma_mode = drive->pio_mode;
  657 + hpt3xx_set_mode(hwif, drive);
657 658 }
658 659  
659 660 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
drivers/ide/ht6560b.c
Diff comments   View file @ 4c10c93
... ... @@ -279,9 +279,10 @@
279 279 #endif
280 280 }
281 281  
282   -static void ht6560b_set_pio_mode(ide_drive_t *drive, const u8 pio)
  282 +static void ht6560b_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
283 283 {
284 284 unsigned long flags, config;
  285 + const u8 pio = drive->pio_mode - XFER_PIO_0;
285 286 u8 timing;
286 287  
287 288 switch (pio) {
drivers/ide/icside.c
Diff comments   View file @ 4c10c93
... ... @@ -65,6 +65,8 @@
65 65 };
66 66  
67 67 struct icside_state {
  68 + unsigned int channel;
  69 + unsigned int enabled;
68 70 void __iomem *irq_port;
69 71 void __iomem *ioc_base;
70 72 unsigned int sel;
71 73  
... ... @@ -114,11 +116,18 @@
114 116 struct icside_state *state = ec->irq_data;
115 117 void __iomem *base = state->irq_port;
116 118  
117   - writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
118   - readb(base + ICS_ARCIN_V6_INTROFFSET_2);
  119 + state->enabled = 1;
119 120  
120   - writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
121   - readb(base + ICS_ARCIN_V6_INTROFFSET_1);
  121 + switch (state->channel) {
  122 + case 0:
  123 + writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
  124 + readb(base + ICS_ARCIN_V6_INTROFFSET_2);
  125 + break;
  126 + case 1:
  127 + writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
  128 + readb(base + ICS_ARCIN_V6_INTROFFSET_1);
  129 + break;
  130 + }
122 131 }
123 132  
124 133 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
... ... @@ -128,6 +137,8 @@
128 137 {
129 138 struct icside_state *state = ec->irq_data;
130 139  
  140 + state->enabled = 0;
  141 +
131 142 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
132 143 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
133 144 }
... ... @@ -149,6 +160,44 @@
149 160 .irqpending = icside_irqpending_arcin_v6,
150 161 };
151 162  
  163 +/*
  164 + * Handle routing of interrupts. This is called before
  165 + * we write the command to the drive.
  166 + */
  167 +static void icside_maskproc(ide_drive_t *drive, int mask)
  168 +{
  169 + ide_hwif_t *hwif = drive->hwif;
  170 + struct expansion_card *ec = ECARD_DEV(hwif->dev);
  171 + struct icside_state *state = ecard_get_drvdata(ec);
  172 + unsigned long flags;
  173 +
  174 + local_irq_save(flags);
  175 +
  176 + state->channel = hwif->channel;
  177 +
  178 + if (state->enabled && !mask) {
  179 + switch (hwif->channel) {
  180 + case 0:
  181 + writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  182 + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  183 + break;
  184 + case 1:
  185 + writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  186 + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  187 + break;
  188 + }
  189 + } else {
  190 + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
  191 + readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
  192 + }
  193 +
  194 + local_irq_restore(flags);
  195 +}
  196 +
  197 +static const struct ide_port_ops icside_v6_no_dma_port_ops = {
  198 + .maskproc = icside_maskproc,
  199 +};
  200 +
152 201 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
153 202 /*
154 203 * SG-DMA support.
155 204  
... ... @@ -185,10 +234,11 @@
185 234 * MW1 80 50 50 150 C
186 235 * MW2 70 25 25 120 C
187 236 */
188   -static void icside_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
  237 +static void icside_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
189 238 {
190 239 unsigned long cycle_time;
191 240 int use_dma_info = 0;
  241 + const u8 xfer_mode = drive->dma_mode;
192 242  
193 243 switch (xfer_mode) {
194 244 case XFER_MW_DMA_2:
... ... @@ -228,6 +278,7 @@
228 278  
229 279 static const struct ide_port_ops icside_v6_port_ops = {
230 280 .set_dma_mode = icside_set_dma_mode,
  281 + .maskproc = icside_maskproc,
231 282 };
232 283  
233 284 static void icside_dma_host_set(ide_drive_t *drive, int on)
... ... @@ -272,6 +323,11 @@
272 323 BUG_ON(dma_channel_active(ec->dma));
273 324  
274 325 /*
  326 + * Ensure that we have the right interrupt routed.
  327 + */
  328 + icside_maskproc(drive, 0);
  329 +
  330 + /*
275 331 * Route the DMA signals to the correct interface.
276 332 */
277 333 writeb(state->sel | hwif->channel, state->ioc_base);
... ... @@ -399,6 +455,7 @@
399 455  
400 456 static const struct ide_port_info icside_v6_port_info __initdata = {
401 457 .init_dma = icside_dma_off_init,
  458 + .port_ops = &icside_v6_no_dma_port_ops,
402 459 .dma_ops = &icside_v6_dma_ops,
403 460 .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
404 461 .mwdma_mask = ATA_MWDMA2,
drivers/ide/ide-cs.c
Diff comments   View file @ 4c10c93
... ... @@ -121,19 +121,11 @@
121 121 static void ide_detach(struct pcmcia_device *link)
122 122 {
123 123 ide_info_t *info = link->priv;
124   - ide_hwif_t *hwif = info->host->ports[0];
125   - unsigned long data_addr, ctl_addr;
126 124  
127 125 dev_dbg(&link->dev, "ide_detach(0x%p)\n", link);
128 126  
129   - data_addr = hwif->io_ports.data_addr;
130   - ctl_addr = hwif->io_ports.ctl_addr;
131   -
132 127 ide_release(link);
133 128  
134   - release_region(ctl_addr, 1);
135   - release_region(data_addr, 8);
136   -
137 129 kfree(info);
138 130 } /* ide_detach */
139 131  
140 132  
141 133  
... ... @@ -354,12 +346,19 @@
354 346  
355 347 dev_dbg(&link->dev, "ide_release(0x%p)\n", link);
356 348  
357   - if (info->ndev)
358   - /* FIXME: if this fails we need to queue the cleanup somehow
359   - -- need to investigate the required PCMCIA magic */
  349 + if (info->ndev) {
  350 + ide_hwif_t *hwif = host->ports[0];
  351 + unsigned long data_addr, ctl_addr;
  352 +
  353 + data_addr = hwif->io_ports.data_addr;
  354 + ctl_addr = hwif->io_ports.ctl_addr;
  355 +
360 356 ide_host_remove(host);
  357 + info->ndev = 0;
361 358  
362   - info->ndev = 0;
  359 + release_region(ctl_addr, 1);
  360 + release_region(data_addr, 8);
  361 + }
363 362  
364 363 pcmcia_disable_device(link);
365 364 } /* ide_release */
drivers/ide/ide-devsets.c
Diff comments   View file @ 4c10c93
... ... @@ -105,15 +105,17 @@
105 105 return -ENOSYS;
106 106  
107 107 if (set_pio_mode_abuse(drive->hwif, arg)) {
  108 + drive->pio_mode = arg + XFER_PIO_0;
  109 +
108 110 if (arg == 8 || arg == 9) {
109 111 unsigned long flags;
110 112  
111 113 /* take lock for IDE_DFLAG_[NO_]UNMASK/[NO_]IO_32BIT */
112 114 spin_lock_irqsave(&hwif->lock, flags);
113   - port_ops->set_pio_mode(drive, arg);
  115 + port_ops->set_pio_mode(hwif, drive);
114 116 spin_unlock_irqrestore(&hwif->lock, flags);
115 117 } else
116   - port_ops->set_pio_mode(drive, arg);
  118 + port_ops->set_pio_mode(hwif, drive);
117 119 } else {
118 120 int keep_dma = !!(drive->dev_flags & IDE_DFLAG_USING_DMA);
119 121  
drivers/ide/ide-iops.c
Diff comments   View file @ 4c10c93
... ... @@ -231,7 +231,7 @@
231 231 u16 *id = drive->id;
232 232 int ivb = ide_in_drive_list(id, ivb_list);
233 233  
234   - if (hwif->cbl == ATA_CBL_PATA40_SHORT)
  234 + if (hwif->cbl == ATA_CBL_SATA || hwif->cbl == ATA_CBL_PATA40_SHORT)
235 235 return 1;
236 236  
237 237 if (ivb)
drivers/ide/ide-probe.c
Diff comments   View file @ 4c10c93
... ... @@ -1042,6 +1042,8 @@
1042 1042 if (hwif->host_flags & IDE_HFLAG_NO_UNMASK_IRQS)
1043 1043 drive->dev_flags |= IDE_DFLAG_NO_UNMASK;
1044 1044  
  1045 + drive->pio_mode = XFER_PIO_0;
  1046 +
1045 1047 if (port_ops && port_ops->init_dev)
1046 1048 port_ops->init_dev(drive);
1047 1049 }
drivers/ide/ide-tape.c
Diff comments   View file @ 4c10c93
... ... @@ -1365,7 +1365,7 @@
1365 1365 * supported here, and not in the corresponding block interface. Our own
1366 1366 * ide-tape ioctls are supported on both interfaces.
1367 1367 */
1368   -static int idetape_chrdev_ioctl(struct inode *inode, struct file *file,
  1368 +static long do_idetape_chrdev_ioctl(struct file *file,
1369 1369 unsigned int cmd, unsigned long arg)
1370 1370 {
1371 1371 struct ide_tape_obj *tape = file->private_data;
... ... @@ -1420,6 +1420,16 @@
1420 1420 }
1421 1421 }
1422 1422  
  1423 +static long idetape_chrdev_ioctl(struct file *file,
  1424 + unsigned int cmd, unsigned long arg)
  1425 +{
  1426 + long ret;
  1427 + lock_kernel();
  1428 + ret = do_idetape_chrdev_ioctl(file, cmd, arg);
  1429 + unlock_kernel();
  1430 + return ret;
  1431 +}
  1432 +
1423 1433 /*
1424 1434 * Do a mode sense page 0 with block descriptor and if it succeeds set the tape
1425 1435 * block size with the reported value.
... ... @@ -1888,7 +1898,7 @@
1888 1898 .owner = THIS_MODULE,
1889 1899 .read = idetape_chrdev_read,
1890 1900 .write = idetape_chrdev_write,
1891   - .ioctl = idetape_chrdev_ioctl,
  1901 + .unlocked_ioctl = idetape_chrdev_ioctl,
1892 1902 .open = idetape_chrdev_open,
1893 1903 .release = idetape_chrdev_release,
1894 1904 };
drivers/ide/ide-timings.c
Diff comments   View file @ 4c10c93
... ... @@ -166,12 +166,13 @@
166 166 if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
167 167 memset(&p, 0, sizeof(p));
168 168  
169   - if (speed <= XFER_PIO_2)
170   - p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
171   - else if ((speed <= XFER_PIO_4) ||
172   - (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
173   - p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
174   - else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
  169 + if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
  170 + if (speed <= XFER_PIO_2)
  171 + p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
  172 + else if ((speed <= XFER_PIO_4) ||
  173 + (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
  174 + p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
  175 + } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
175 176 p.cycle = id[ATA_ID_EIDE_DMA_MIN];
176 177  
177 178 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
178 179  
... ... @@ -185,11 +186,10 @@
185 186 /*
186 187 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
187 188 * S.M.A.R.T and some other commands. We have to ensure that the
188   - * DMA cycle timing is slower/equal than the fastest PIO timing.
  189 + * DMA cycle timing is slower/equal than the current PIO timing.
189 190 */
190 191 if (speed >= XFER_SW_DMA_0) {
191   - u8 pio = ide_get_best_pio_mode(drive, 255, 5);
192   - ide_timing_compute(drive, XFER_PIO_0 + pio, &p, T, UT);
  192 + ide_timing_compute(drive, drive->pio_mode, &p, T, UT);
193 193 ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
194 194 }
195 195  
drivers/ide/ide-xfer-mode.c
Diff comments   View file @ 4c10c93
... ... @@ -58,7 +58,7 @@
58 58 * This is used by most chipset support modules when "auto-tuning".
59 59 */
60 60  
61   -u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode)
  61 +static u8 ide_get_best_pio_mode(ide_drive_t *drive, u8 mode_wanted, u8 max_mode)
62 62 {
63 63 u16 *id = drive->id;
64 64 int pio_mode = -1, overridden = 0;
... ... @@ -105,7 +105,6 @@
105 105  
106 106 return pio_mode;
107 107 }
108   -EXPORT_SYMBOL_GPL(ide_get_best_pio_mode);
109 108  
110 109 int ide_pio_need_iordy(ide_drive_t *drive, const u8 pio)
111 110 {
112 111  
113 112  
... ... @@ -135,17 +134,20 @@
135 134 * set transfer mode on the device in ->set_pio_mode method...
136 135 */
137 136 if (port_ops->set_dma_mode == NULL) {
138   - port_ops->set_pio_mode(drive, mode - XFER_PIO_0);
  137 + drive->pio_mode = mode;
  138 + port_ops->set_pio_mode(hwif, drive);
139 139 return 0;
140 140 }
141 141  
142 142 if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) {
143 143 if (ide_config_drive_speed(drive, mode))
144 144 return -1;
145   - port_ops->set_pio_mode(drive, mode - XFER_PIO_0);
  145 + drive->pio_mode = mode;
  146 + port_ops->set_pio_mode(hwif, drive);
146 147 return 0;
147 148 } else {
148   - port_ops->set_pio_mode(drive, mode - XFER_PIO_0);
  149 + drive->pio_mode = mode;
  150 + port_ops->set_pio_mode(hwif, drive);
149 151 return ide_config_drive_speed(drive, mode);
150 152 }
151 153 }
152 154  
... ... @@ -164,10 +166,12 @@
164 166 if (hwif->host_flags & IDE_HFLAG_POST_SET_MODE) {
165 167 if (ide_config_drive_speed(drive, mode))
166 168 return -1;
167   - port_ops->set_dma_mode(drive, mode);
  169 + drive->dma_mode = mode;
  170 + port_ops->set_dma_mode(hwif, drive);
168 171 return 0;
169 172 } else {
170   - port_ops->set_dma_mode(drive, mode);
  173 + drive->dma_mode = mode;
  174 + port_ops->set_dma_mode(hwif, drive);
171 175 return ide_config_drive_speed(drive, mode);
172 176 }
173 177 }
drivers/ide/it8172.c
Diff comments   View file @ 4c10c93
... ... @@ -37,12 +37,12 @@
37 37  
38 38 #define DRV_NAME "IT8172"
39 39  
40   -static void it8172_set_pio_mode(ide_drive_t *drive, const u8 pio)
  40 +static void it8172_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
41 41 {
42   - ide_hwif_t *hwif = drive->hwif;
43 42 struct pci_dev *dev = to_pci_dev(hwif->dev);
44 43 u16 drive_enables;
45 44 u32 drive_timing;
  45 + const u8 pio = drive->pio_mode - XFER_PIO_0;
46 46  
47 47 /*
48 48 * The highest value of DIOR/DIOW pulse width and recovery time
49 49  
50 50  
... ... @@ -77,14 +77,14 @@
77 77 pci_write_config_dword(dev, 0x44, drive_timing);
78 78 }
79 79  
80   -static void it8172_set_dma_mode(ide_drive_t *drive, const u8 speed)
  80 +static void it8172_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
81 81 {
82   - ide_hwif_t *hwif = drive->hwif;
83 82 struct pci_dev *dev = to_pci_dev(hwif->dev);
84 83 int a_speed = 3 << (drive->dn * 4);
85 84 int u_flag = 1 << drive->dn;
86 85 int u_speed = 0;
87 86 u8 reg48, reg4a;
  87 + const u8 speed = drive->dma_mode;
88 88  
89 89 pci_read_config_byte(dev, 0x48, &reg48);
90 90 pci_read_config_byte(dev, 0x4a, &reg4a);
91 91  
92 92  
... ... @@ -98,14 +98,14 @@
98 98 pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
99 99 } else {
100 100 const u8 mwdma_to_pio[] = { 0, 3, 4 };
101   - u8 pio;
102 101  
103 102 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
104 103 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
105 104  
106   - pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
  105 + drive->pio_mode =
  106 + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
107 107  
108   - it8172_set_pio_mode(drive, pio);
  108 + it8172_set_pio_mode(hwif, drive);
109 109 }
110 110 }
111 111  
drivers/ide/it8213.c
Diff comments   View file @ 4c10c93
... ... @@ -17,15 +17,14 @@
17 17  
18 18 /**
19 19 * it8213_set_pio_mode - set host controller for PIO mode
  20 + * @hwif: port
20 21 * @drive: drive
21   - * @pio: PIO mode number
22 22 *
23 23 * Set the interface PIO mode.
24 24 */
25 25  
26   -static void it8213_set_pio_mode(ide_drive_t *drive, const u8 pio)
  26 +static void it8213_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
27 27 {
28   - ide_hwif_t *hwif = drive->hwif;
29 28 struct pci_dev *dev = to_pci_dev(hwif->dev);
30 29 int is_slave = drive->dn & 1;
31 30 int master_port = 0x40;
... ... @@ -35,6 +34,7 @@
35 34 u8 slave_data;
36 35 static DEFINE_SPINLOCK(tune_lock);
37 36 int control = 0;
  37 + const u8 pio = drive->pio_mode - XFER_PIO_0;
38 38  
39 39 static const u8 timings[][2] = {
40 40 { 0, 0 },
41 41  
42 42  
43 43  
... ... @@ -74,15 +74,14 @@
74 74  
75 75 /**
76 76 * it8213_set_dma_mode - set host controller for DMA mode
  77 + * @hwif: port
77 78 * @drive: drive
78   - * @speed: DMA mode
79 79 *
80 80 * Tune the ITE chipset for the DMA mode.
81 81 */
82 82  
83   -static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
  83 +static void it8213_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
84 84 {
85   - ide_hwif_t *hwif = drive->hwif;
86 85 struct pci_dev *dev = to_pci_dev(hwif->dev);
87 86 u8 maslave = 0x40;
88 87 int a_speed = 3 << (drive->dn * 4);
... ... @@ -92,6 +91,7 @@
92 91 int u_speed = 0;
93 92 u16 reg4042, reg4a;
94 93 u8 reg48, reg54, reg55;
  94 + const u8 speed = drive->dma_mode;
95 95  
96 96 pci_read_config_word(dev, maslave, &reg4042);
97 97 pci_read_config_byte(dev, 0x48, &reg48);
... ... @@ -120,7 +120,6 @@
120 120 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
121 121 } else {
122 122 const u8 mwdma_to_pio[] = { 0, 3, 4 };
123   - u8 pio;
124 123  
125 124 if (reg48 & u_flag)
126 125 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
127 126  
128 127  
... ... @@ -132,11 +131,12 @@
132 131 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
133 132  
134 133 if (speed >= XFER_MW_DMA_0)
135   - pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
  134 + drive->pio_mode =
  135 + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
136 136 else
137   - pio = 2; /* only SWDMA2 is allowed */
  137 + drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
138 138  
139   - it8213_set_pio_mode(drive, pio);
  139 + it8213_set_pio_mode(hwif, drive);
140 140 }
141 141 }
142 142  
drivers/ide/it821x.c
Diff comments   View file @ 4c10c93
... ... @@ -228,18 +228,18 @@
228 228  
229 229 /**
230 230 * it821x_set_pio_mode - set host controller for PIO mode
  231 + * @hwif: port
231 232 * @drive: drive
232   - * @pio: PIO mode number
233 233 *
234 234 * Tune the host to the desired PIO mode taking into the consideration
235 235 * the maximum PIO mode supported by the other device on the cable.
236 236 */
237 237  
238   -static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
  238 +static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
239 239 {
240   - ide_hwif_t *hwif = drive->hwif;
241 240 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
242 241 ide_drive_t *pair = ide_get_pair_dev(drive);
  242 + const u8 pio = drive->pio_mode - XFER_PIO_0;
243 243 u8 unit = drive->dn & 1, set_pio = pio;
244 244  
245 245 /* Spec says 89 ref driver uses 88 */
... ... @@ -252,7 +252,7 @@
252 252 * on the cable.
253 253 */
254 254 if (pair) {
255   - u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
  255 + u8 pair_pio = pair->pio_mode - XFER_PIO_0;
256 256 /* trim PIO to the slowest of the master/slave */
257 257 if (pair_pio < set_pio)
258 258 set_pio = pair_pio;
259 259  
260 260  
261 261  
... ... @@ -393,14 +393,16 @@
393 393  
394 394 /**
395 395 * it821x_set_dma_mode - set host controller for DMA mode
  396 + * @hwif: port
396 397 * @drive: drive
397   - * @speed: DMA mode
398 398 *
399 399 * Tune the ITE chipset for the desired DMA mode.
400 400 */
401 401  
402   -static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed)
  402 +static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
403 403 {
  404 + const u8 speed = drive->dma_mode;
  405 +
404 406 /*
405 407 * MWDMA tuning is really hard because our MWDMA and PIO
406 408 * timings are kept in the same place. We can switch in the
drivers/ide/jmicron.c
Diff comments   View file @ 4c10c93
... ... @@ -80,19 +80,19 @@
80 80 return ATA_CBL_PATA80;
81 81 }
82 82  
83   -static void jmicron_set_pio_mode(ide_drive_t *drive, const u8 pio)
  83 +static void jmicron_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
84 84 {
85 85 }
86 86  
87 87 /**
88 88 * jmicron_set_dma_mode - set host controller for DMA mode
  89 + * @hwif: port
89 90 * @drive: drive
90   - * @mode: DMA mode
91 91 *
92 92 * As the JMicron snoops for timings we don't need to do anything here.
93 93 */
94 94  
95   -static void jmicron_set_dma_mode(ide_drive_t *drive, const u8 mode)
  95 +static void jmicron_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
96 96 {
97 97 }
98 98  
drivers/ide/opti621.c
Diff comments   View file @ 4c10c93
... ... @@ -8,77 +8,6 @@
8 8 * Jan Harkes <jaharkes@cwi.nl>,
9 9 * Mark Lord <mlord@pobox.com>
10 10 * Some parts of code are from ali14xx.c and from rz1000.c.
11   - *
12   - * OPTi is trademark of OPTi, Octek is trademark of Octek.
13   - *
14   - * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
15   - * and disassembled/traced setupvic.exe (DOS program).
16   - * It increases kernel code about 2 kB.
17   - * I don't have this card no more, but I hope I can get some in case
18   - * of needed development.
19   - * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
20   - * It has a place for a secondary connector in circuit, but nothing
21   - * is there. Also BIOS says no address for
22   - * secondary controller (see bellow in ide_init_opti621).
23   - * I've only tested this on my system, which only has one disk.
24   - * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
25   - * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
26   - * lockups). I tried the OCTEK double speed CD-ROM and
27   - * it does not work! But I can't boot DOS also, so it's probably
28   - * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
29   - * problems) and Seagate 1GB (as slave, WD as master). My experiences
30   - * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
31   - * it slows to about 100kB/s! I don't know why and I have
32   - * not this drive now, so I can't try it again.
33   - * I write this driver because I lost the paper ("manual") with
34   - * settings of jumpers on the card and I have to boot Linux with
35   - * Loadlin except LILO, cause I have to run the setupvic.exe program
36   - * already or I get disk errors (my test: rpm -Vf
37   - * /usr/X11R6/bin/XF86_SVGA - or any big file).
38   - * Some numbers from hdparm -t /dev/hda:
39   - * Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
40   - * Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
41   - * I have 4 Megs/s before, but I don't know why (maybe changes
42   - * in hdparm test).
43   - * After release of 0.1, I got some successful reports, so it might work.
44   - *
45   - * The main problem with OPTi is that some timings for master
46   - * and slave must be the same. For example, if you have master
47   - * PIO 3 and slave PIO 0, driver have to set some timings of
48   - * master for PIO 0. Second problem is that opti621_set_pio_mode
49   - * got only one drive to set, but have to set both drives.
50   - * This is solved in compute_pios. If you don't set
51   - * the second drive, compute_pios use ide_get_best_pio_mode
52   - * for autoselect mode (you can change it to PIO 0, if you want).
53   - * If you then set the second drive to another PIO, the old value
54   - * (automatically selected) will be overrided by yours.
55   - * There is a 25/33MHz switch in configuration
56   - * register, but driver is written for use at any frequency.
57   - *
58   - * Version 0.1, Nov 8, 1996
59   - * by Jaromir Koutek, for 2.1.8.
60   - * Initial version of driver.
61   - *
62   - * Version 0.2
63   - * Number 0.2 skipped.
64   - *
65   - * Version 0.3, Nov 29, 1997
66   - * by Mark Lord (probably), for 2.1.68
67   - * Updates for use with new IDE block driver.
68   - *
69   - * Version 0.4, Dec 14, 1997
70   - * by Jan Harkes
71   - * Fixed some errors and cleaned the code.
72   - *
73   - * Version 0.5, Jan 2, 1998
74   - * by Jaromir Koutek
75   - * Updates for use with (again) new IDE block driver.
76   - * Update of documentation.
77   - *
78   - * Version 0.6, Jan 2, 1999
79   - * by Jaromir Koutek
80   - * Reversed to version 0.3 of the driver, because
81   - * 0.5 doesn't work.
82 11 */
83 12  
84 13 #include <linux/types.h>
85 14  
86 15  
... ... @@ -133,12 +62,12 @@
133 62 return ret;
134 63 }
135 64  
136   -static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
  65 +static void opti621_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
137 66 {
138   - ide_hwif_t *hwif = drive->hwif;
139 67 ide_drive_t *pair = ide_get_pair_dev(drive);
140 68 unsigned long flags;
141   - unsigned long mode = XFER_PIO_0 + pio, pair_mode;
  69 + unsigned long mode = drive->pio_mode, pair_mode;
  70 + const u8 pio = mode - XFER_PIO_0;
142 71 u8 tim, misc, addr_pio = pio, clk;
143 72  
144 73 /* DRDY is default 2 (by OPTi Databook) */
drivers/ide/palm_bk3710.c
Diff comments   View file @ 4c10c93
... ... @@ -166,7 +166,7 @@
166 166 writel(val32, base + BK3710_DATRCVR);
167 167  
168 168 if (mate) {
169   - u8 mode2 = ide_get_best_pio_mode(mate, 255, 4);
  169 + u8 mode2 = mate->pio_mode - XFER_PIO_0;
170 170  
171 171 if (mode2 < mode)
172 172 mode = mode2;
173 173  
... ... @@ -188,10 +188,11 @@
188 188 writel(val32, base + BK3710_REGRCVR);
189 189 }
190 190  
191   -static void palm_bk3710_set_dma_mode(ide_drive_t *drive, u8 xferspeed)
  191 +static void palm_bk3710_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
192 192 {
193 193 int is_slave = drive->dn & 1;
194   - void __iomem *base = (void *)drive->hwif->dma_base;
  194 + void __iomem *base = (void *)hwif->dma_base;
  195 + const u8 xferspeed = drive->dma_mode;
195 196  
196 197 if (xferspeed >= XFER_UDMA_0) {
197 198 palm_bk3710_setudmamode(base, is_slave,
198 199  
... ... @@ -203,12 +204,13 @@
203 204 }
204 205 }
205 206  
206   -static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
  207 +static void palm_bk3710_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
207 208 {
208 209 unsigned int cycle_time;
209 210 int is_slave = drive->dn & 1;
210 211 ide_drive_t *mate;
211   - void __iomem *base = (void *)drive->hwif->dma_base;
  212 + void __iomem *base = (void *)hwif->dma_base;
  213 + const u8 pio = drive->pio_mode - XFER_PIO_0;
212 214  
213 215 /*
214 216 * Obtain the drive PIO data for tuning the Palm Chip registers
drivers/ide/pdc202xx_new.c
Diff comments   View file @ 4c10c93
... ... @@ -129,11 +129,11 @@
129 129 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
130 130 };
131 131  
132   -static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
  132 +static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
133 133 {
134   - ide_hwif_t *hwif = drive->hwif;
135 134 struct pci_dev *dev = to_pci_dev(hwif->dev);
136 135 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
  136 + const u8 speed = drive->dma_mode;
137 137  
138 138 /*
139 139 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
140 140  
141 141  
... ... @@ -167,11 +167,11 @@
167 167 }
168 168 }
169 169  
170   -static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
  170 +static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
171 171 {
172   - ide_hwif_t *hwif = drive->hwif;
173 172 struct pci_dev *dev = to_pci_dev(hwif->dev);
174 173 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
  174 + const u8 pio = drive->pio_mode - XFER_PIO_0;
175 175  
176 176 if (max_dma_rate(dev) == 4) {
177 177 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
drivers/ide/pdc202xx_old.c
Diff comments   View file @ 4c10c93
1 1 /*
2 2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 3 * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
4   - * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  4 + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
5 5 *
6 6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 7 * Author: Frank Tiernan (frankt@promise.com)
8 8  
9 9  
10 10  
... ... @@ -21,23 +21,15 @@
21 21  
22 22 #define DRV_NAME "pdc202xx_old"
23 23  
24   -static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
25   -
26   -static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  24 +static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
27 25 {
28   - ide_hwif_t *hwif = drive->hwif;
29 26 struct pci_dev *dev = to_pci_dev(hwif->dev);
30 27 u8 drive_pci = 0x60 + (drive->dn << 2);
  28 + const u8 speed = drive->dma_mode;
31 29  
32 30 u8 AP = 0, BP = 0, CP = 0;
33 31 u8 TA = 0, TB = 0, TC = 0;
34 32  
35   - /*
36   - * TODO: do this once per channel
37   - */
38   - if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
39   - pdc_old_disable_66MHz_clock(hwif);
40   -
41 33 pci_read_config_byte(dev, drive_pci, &AP);
42 34 pci_read_config_byte(dev, drive_pci + 1, &BP);
43 35 pci_read_config_byte(dev, drive_pci + 2, &CP);
44 36  
... ... @@ -84,9 +76,10 @@
84 76 }
85 77 }
86 78  
87   -static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
  79 +static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
88 80 {
89   - pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
  81 + drive->dma_mode = drive->pio_mode;
  82 + pdc202xx_set_mode(hwif, drive);
90 83 }
91 84  
92 85 static int pdc202xx_test_irq(ide_hwif_t *hwif)
93 86  
... ... @@ -100,13 +93,13 @@
100 93 * bit 7: error, bit 6: interrupting,
101 94 * bit 5: FIFO full, bit 4: FIFO empty
102 95 */
103   - return ((sc1d & 0x50) == 0x40) ? 1 : 0;
  96 + return ((sc1d & 0x50) == 0x50) ? 1 : 0;
104 97 } else {
105 98 /*
106 99 * bit 3: error, bit 2: interrupting,
107 100 * bit 1: FIFO full, bit 0: FIFO empty
108 101 */
109   - return ((sc1d & 0x05) == 0x04) ? 1 : 0;
  102 + return ((sc1d & 0x05) == 0x05) ? 1 : 0;
110 103 }
111 104 }
112 105  
... ... @@ -145,6 +138,11 @@
145 138 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
146 139 }
147 140  
  141 +static void pdc2026x_init_hwif(ide_hwif_t *hwif)
  142 +{
  143 + pdc_old_disable_66MHz_clock(hwif);
  144 +}
  145 +
148 146 static void pdc202xx_dma_start(ide_drive_t *drive)
149 147 {
150 148 if (drive->current_speed > XFER_UDMA_2)
... ... @@ -261,6 +259,7 @@
261 259 { \
262 260 .name = DRV_NAME, \
263 261 .init_chipset = init_chipset_pdc202xx, \
  262 + .init_hwif = pdc2026x_init_hwif, \
264 263 .port_ops = &pdc2026x_port_ops, \
265 264 .dma_ops = &pdc2026x_dma_ops, \
266 265 .host_flags = IDE_HFLAGS_PDC202XX, \
... ... @@ -356,7 +355,7 @@
356 355 module_init(pdc202xx_ide_init);
357 356 module_exit(pdc202xx_ide_exit);
358 357  
359   -MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
  358 +MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
360 359 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
361 360 MODULE_LICENSE("GPL");
... ... @@ -59,15 +59,14 @@
59 59  
60 60 /**
61 61 * piix_set_pio_mode - set host controller for PIO mode
  62 + * @port: port
62 63 * @drive: drive
63   - * @pio: PIO mode number
64 64 *
65 65 * Set the interface PIO mode based upon the settings done by AMI BIOS.
66 66 */
67 67  
68   -static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
  68 +static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
69 69 {
70   - ide_hwif_t *hwif = drive->hwif;
71 70 struct pci_dev *dev = to_pci_dev(hwif->dev);
72 71 int is_slave = drive->dn & 1;
73 72 int master_port = hwif->channel ? 0x42 : 0x40;
... ... @@ -77,6 +76,7 @@
77 76 u8 slave_data;
78 77 static DEFINE_SPINLOCK(tune_lock);
79 78 int control = 0;
  79 + const u8 pio = drive->pio_mode - XFER_PIO_0;
80 80  
81 81 /* ISP RTC */
82 82 static const u8 timings[][2]= {
83 83  
84 84  
85 85  
... ... @@ -127,16 +127,15 @@
127 127  
128 128 /**
129 129 * piix_set_dma_mode - set host controller for DMA mode
  130 + * @hwif: port
130 131 * @drive: drive
131   - * @speed: DMA mode
132 132 *
133 133 * Set a PIIX host controller to the desired DMA mode. This involves
134 134 * programming the right timing data into the PCI configuration space.
135 135 */
136 136  
137   -static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
  137 +static void piix_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
138 138 {
139   - ide_hwif_t *hwif = drive->hwif;
140 139 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 140 u8 maslave = hwif->channel ? 0x42 : 0x40;
142 141 int a_speed = 3 << (drive->dn * 4);
... ... @@ -147,6 +146,7 @@
147 146 int sitre;
148 147 u16 reg4042, reg4a;
149 148 u8 reg48, reg54, reg55;
  149 + const u8 speed = drive->dma_mode;
150 150  
151 151 pci_read_config_word(dev, maslave, &reg4042);
152 152 sitre = (reg4042 & 0x4000) ? 1 : 0;
... ... @@ -176,7 +176,6 @@
176 176 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
177 177 } else {
178 178 const u8 mwdma_to_pio[] = { 0, 3, 4 };
179   - u8 pio;
180 179  
181 180 if (reg48 & u_flag)
182 181 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
183 182  
184 183  
... ... @@ -188,11 +187,12 @@
188 187 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
189 188  
190 189 if (speed >= XFER_MW_DMA_0)
191   - pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
  190 + drive->pio_mode =
  191 + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
192 192 else
193   - pio = 2; /* only SWDMA2 is allowed */
  193 + drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
194 194  
195   - piix_set_pio_mode(drive, pio);
  195 + piix_set_pio_mode(hwif, drive);
196 196 }
197 197 }
198 198  
... ... @@ -496,12 +496,11 @@
496 496 /*
497 497 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
498 498 */
499   -static void
500   -pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
  499 +static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
501 500 {
502   - ide_hwif_t *hwif = drive->hwif;
503 501 pmac_ide_hwif_t *pmif =
504 502 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
  503 + const u8 pio = drive->pio_mode - XFER_PIO_0;
505 504 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
506 505 u32 *timings, t;
507 506 unsigned accessTicks, recTicks;
508 507  
509 508  
... ... @@ -778,14 +777,14 @@
778 777 #endif
779 778 }
780 779  
781   -static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
  780 +static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
782 781 {
783   - ide_hwif_t *hwif = drive->hwif;
784 782 pmac_ide_hwif_t *pmif =
785 783 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
786 784 int ret = 0;
787 785 u32 *timings, *timings2, tl[2];
788 786 u8 unit = drive->dn & 1;
  787 + const u8 speed = drive->dma_mode;
789 788  
790 789 timings = &pmif->timings[unit];
791 790 timings2 = &pmif->timings[unit+2];
... ... @@ -1651,8 +1650,8 @@
1651 1650 if ((status & FLUSH) == 0)
1652 1651 break;
1653 1652 if (++timeout > 100) {
1654   - printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1655   - timeout flushing channel\n", hwif->index);
  1653 + printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
  1654 + hwif->index);
1656 1655 break;
1657 1656 }
1658 1657 }
drivers/ide/qd65xx.c
Diff comments   View file @ 4c10c93
... ... @@ -189,15 +189,13 @@
189 189 printk(KERN_DEBUG "%s: %#x\n", drive->name, timing);
190 190 }
191 191  
192   -static void qd6500_set_pio_mode(ide_drive_t *drive, const u8 pio)
  192 +static void qd6500_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
193 193 {
194 194 u16 *id = drive->id;
195 195 int active_time = 175;
196 196 int recovery_time = 415; /* worst case values from the dos driver */
197 197  
198   - /*
199   - * FIXME: use "pio" value
200   - */
  198 + /* FIXME: use drive->pio_mode value */
201 199 if (!qd_find_disk_type(drive, &active_time, &recovery_time) &&
202 200 (id[ATA_ID_OLD_PIO_MODES] & 0xff) && (id[ATA_ID_FIELD_VALID] & 2) &&
203 201 id[ATA_ID_EIDE_PIO] >= 240) {
204 202  
... ... @@ -211,9 +209,9 @@
211 209 active_time, recovery_time));
212 210 }
213 211  
214   -static void qd6580_set_pio_mode(ide_drive_t *drive, const u8 pio)
  212 +static void qd6580_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
215 213 {
216   - ide_hwif_t *hwif = drive->hwif;
  214 + const u8 pio = drive->pio_mode - XFER_PIO_0;
217 215 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
218 216 unsigned int cycle_time;
219 217 int active_time = 175;
drivers/ide/sc1200.c
Diff comments   View file @ 4c10c93
... ... @@ -122,13 +122,13 @@
122 122 return mask;
123 123 }
124 124  
125   -static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
  125 +static void sc1200_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
126 126 {
127   - ide_hwif_t *hwif = drive->hwif;
128 127 struct pci_dev *dev = to_pci_dev(hwif->dev);
129 128 unsigned int reg, timings;
130 129 unsigned short pci_clock;
131 130 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
  131 + const u8 mode = drive->dma_mode;
132 132  
133 133 static const u32 udma_timing[3][3] = {
134 134 { 0x00921250, 0x00911140, 0x00911030 },
135 135  
136 136  
... ... @@ -193,10 +193,10 @@
193 193 * will have valid default PIO timings set up before we get here.
194 194 */
195 195  
196   -static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
  196 +static void sc1200_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
197 197 {
198   - ide_hwif_t *hwif = drive->hwif;
199 198 int mode = -1;
  199 + const u8 pio = drive->pio_mode - XFER_PIO_0;
200 200  
201 201 /*
202 202 * bad abuse of ->set_pio_mode interface
drivers/ide/scc_pata.c
Diff comments   View file @ 4c10c93
... ... @@ -199,16 +199,15 @@
199 199  
200 200 /**
201 201 * scc_set_pio_mode - set host controller for PIO mode
  202 + * @hwif: port
202 203 * @drive: drive
203   - * @pio: PIO mode number
204 204 *
205 205 * Load the timing settings for this device mode into the
206 206 * controller.
207 207 */
208 208  
209   -static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
  209 +static void scc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
210 210 {
211   - ide_hwif_t *hwif = drive->hwif;
212 211 struct scc_ports *ports = ide_get_hwifdata(hwif);
213 212 unsigned long ctl_base = ports->ctl;
214 213 unsigned long cckctrl_port = ctl_base + 0xff0;
... ... @@ -216,6 +215,7 @@
216 215 unsigned long pioct_port = ctl_base + 0x004;
217 216 unsigned long reg;
218 217 int offset;
  218 + const u8 pio = drive->pio_mode - XFER_PIO_0;
219 219  
220 220 reg = in_be32((void __iomem *)cckctrl_port);
221 221 if (reg & CCKCTRL_ATACLKOEN) {
222 222  
223 223  
224 224  
... ... @@ -231,16 +231,15 @@
231 231  
232 232 /**
233 233 * scc_set_dma_mode - set host controller for DMA mode
  234 + * @hwif: port
234 235 * @drive: drive
235   - * @speed: DMA mode
236 236 *
237 237 * Load the timing settings for this device mode into the
238 238 * controller.
239 239 */
240 240  
241   -static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
  241 +static void scc_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
242 242 {
243   - ide_hwif_t *hwif = drive->hwif;
244 243 struct scc_ports *ports = ide_get_hwifdata(hwif);
245 244 unsigned long ctl_base = ports->ctl;
246 245 unsigned long cckctrl_port = ctl_base + 0xff0;
... ... @@ -254,6 +253,7 @@
254 253 int offset, idx;
255 254 unsigned long reg;
256 255 unsigned long jcactsel;
  256 + const u8 speed = drive->dma_mode;
257 257  
258 258 reg = in_be32((void __iomem *)cckctrl_port);
259 259 if (reg & CCKCTRL_ATACLKOEN) {
260 260  
261 261  
262 262  
263 263  
... ... @@ -872,20 +872,18 @@
872 872 .remove = __devexit_p(scc_remove),
873 873 };
874 874  
875   -static int scc_ide_init(void)
  875 +static int __init scc_ide_init(void)
876 876 {
877 877 return ide_pci_register_driver(&scc_pci_driver);
878 878 }
879 879  
880   -module_init(scc_ide_init);
881   -/* -- No exit code?
882   -static void scc_ide_exit(void)
  880 +static void __exit scc_ide_exit(void)
883 881 {
884   - ide_pci_unregister_driver(&scc_pci_driver);
  882 + pci_unregister_driver(&scc_pci_driver);
885 883 }
886   -module_exit(scc_ide_exit);
887   - */
888 884  
  885 +module_init(scc_ide_init);
  886 +module_exit(scc_ide_exit);
889 887  
890 888 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
891 889 MODULE_LICENSE("GPL");
drivers/ide/serverworks.c
Diff comments   View file @ 4c10c93
... ... @@ -2,7 +2,7 @@
2 2 * Copyright (C) 1998-2000 Michel Aubry
3 3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
4 4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5   - * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
  5 + * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
6 6 * Portions copyright (c) 2001 Sun Microsystems
7 7 *
8 8 *
... ... @@ -52,8 +52,6 @@
52 52 NULL
53 53 };
54 54  
55   -static struct pci_dev *isa_dev;
56   -
57 55 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
58 56 {
59 57 char *m = (char *)&drive->id[ATA_ID_PROD];
60 58  
61 59  
62 60  
... ... @@ -67,26 +65,14 @@
67 65 static u8 svwks_udma_filter(ide_drive_t *drive)
68 66 {
69 67 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
70   - u8 mask = 0;
71 68  
72   - if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  69 + if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
73 70 return 0x1f;
74   - if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
75   - u32 reg = 0;
76   - if (isa_dev)
77   - pci_read_config_dword(isa_dev, 0x64, &reg);
78   -
79   - /*
80   - * Don't enable UDMA on disk devices for the moment
81   - */
82   - if(drive->media == ide_disk)
83   - return 0;
84   - /* Check the OSB4 DMA33 enable bit */
85   - return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
86 71 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
87 72 return 0x07;
88   - } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
89   - u8 btr = 0, mode;
  73 + } else {
  74 + u8 btr = 0, mode, mask;
  75 +
90 76 pci_read_config_byte(dev, 0x5A, &btr);
91 77 mode = btr & 0x3;
92 78  
93 79  
... ... @@ -101,13 +87,9 @@
101 87 case 1: mask = 0x07; break;
102 88 default: mask = 0x00; break;
103 89 }
104   - }
105   - if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
106   - (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
107   - (!(PCI_FUNC(dev->devfn) & 1)))
108   - mask = 0x1f;
109 90  
110   - return mask;
  91 + return mask;
  92 + }
111 93 }
112 94  
113 95 static u8 svwks_csb_check (struct pci_dev *dev)
114 96  
... ... @@ -124,12 +106,13 @@
124 106 return 0;
125 107 }
126 108  
127   -static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
  109 +static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
128 110 {
129 111 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
130 112 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
131 113  
132   - struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  114 + struct pci_dev *dev = to_pci_dev(hwif->dev);
  115 + const u8 pio = drive->pio_mode - XFER_PIO_0;
133 116  
134 117 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
135 118  
136 119  
137 120  
... ... @@ -145,14 +128,14 @@
145 128 }
146 129 }
147 130  
148   -static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
  131 +static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
149 132 {
150 133 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
151 134 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
152 135 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
153 136  
154   - ide_hwif_t *hwif = drive->hwif;
155 137 struct pci_dev *dev = to_pci_dev(hwif->dev);
  138 + const u8 speed = drive->dma_mode;
156 139 u8 unit = drive->dn & 1;
157 140  
158 141 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
... ... @@ -185,8 +168,9 @@
185 168  
186 169 /* OSB4 : South Bridge and IDE */
187 170 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
188   - isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
189   - PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
  171 + struct pci_dev *isa_dev =
  172 + pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  173 + PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
190 174 if (isa_dev) {
191 175 pci_read_config_dword(isa_dev, 0x64, &reg);
192 176 reg &= ~0x00002000; /* disable 600ns interrupt mask */
... ... @@ -195,6 +179,7 @@
195 179 "enabled.\n", pci_name(dev));
196 180 reg |= 0x00004000; /* enable UDMA/33 support */
197 181 pci_write_config_dword(isa_dev, 0x64, reg);
  182 + pci_dev_put(isa_dev);
198 183 }
199 184 }
200 185  
... ... @@ -343,7 +328,6 @@
343 328 static const struct ide_port_ops osb4_port_ops = {
344 329 .set_pio_mode = svwks_set_pio_mode,
345 330 .set_dma_mode = svwks_set_dma_mode,
346   - .udma_filter = svwks_udma_filter,
347 331 };
348 332  
349 333 static const struct ide_port_ops svwks_port_ops = {
... ... @@ -460,7 +444,7 @@
460 444 module_init(svwks_ide_init);
461 445 module_exit(svwks_ide_exit);
462 446  
463   -MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
  447 +MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
464 448 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
465 449 MODULE_LICENSE("GPL");
drivers/ide/sgiioc4.c
Diff comments   View file @ 4c10c93
... ... @@ -255,7 +255,7 @@
255 255 return dma_stat;
256 256 }
257 257  
258   -static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
  258 +static void sgiioc4_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
259 259 {
260 260 }
261 261  
drivers/ide/siimage.c
Diff comments   View file @ 4c10c93
... ... @@ -229,19 +229,18 @@
229 229  
230 230 /**
231 231 * sil_set_pio_mode - set host controller for PIO mode
  232 + * @hwif: port
232 233 * @drive: drive
233   - * @pio: PIO mode number
234 234 *
235 235 * Load the timing settings for this device mode into the
236 236 * controller.
237 237 */
238 238  
239   -static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
  239 +static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
240 240 {
241 241 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
242 242 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
243 243  
244   - ide_hwif_t *hwif = drive->hwif;
245 244 struct pci_dev *dev = to_pci_dev(hwif->dev);
246 245 ide_drive_t *pair = ide_get_pair_dev(drive);
247 246 u32 speedt = 0;
... ... @@ -249,6 +248,7 @@
249 248 unsigned long addr = siimage_seldev(drive, 0x04);
250 249 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
251 250 unsigned long base = (unsigned long)hwif->hwif_data;
  251 + const u8 pio = drive->pio_mode - XFER_PIO_0;
252 252 u8 tf_pio = pio;
253 253 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
254 254 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
... ... @@ -258,7 +258,7 @@
258 258  
259 259 /* trim *taskfile* PIO to the slowest of the master/slave */
260 260 if (pair) {
261   - u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
  261 + u8 pair_pio = pair->pio_mode - XFER_PIO_0;
262 262  
263 263 if (pair_pio < tf_pio)
264 264 tf_pio = pair_pio;
265 265  
266 266  
267 267  
... ... @@ -289,19 +289,18 @@
289 289  
290 290 /**
291 291 * sil_set_dma_mode - set host controller for DMA mode
  292 + * @hwif: port
292 293 * @drive: drive
293   - * @speed: DMA mode
294 294 *
295 295 * Tune the SiI chipset for the desired DMA mode.
296 296 */
297 297  
298   -static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
  298 +static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
299 299 {
300 300 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
301 301 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
302 302 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
303 303  
304   - ide_hwif_t *hwif = drive->hwif;
305 304 struct pci_dev *dev = to_pci_dev(hwif->dev);
306 305 unsigned long base = (unsigned long)hwif->hwif_data;
307 306 u16 ultra = 0, multi = 0;
... ... @@ -311,6 +310,7 @@
311 310 : (mmio ? 0xB4 : 0x80);
312 311 unsigned long ma = siimage_seldev(drive, 0x08);
313 312 unsigned long ua = siimage_seldev(drive, 0x0C);
  313 + const u8 speed = drive->dma_mode;
314 314  
315 315 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
316 316 mode = sil_ioread8 (dev, base + addr_mask);
drivers/ide/sis5513.c
Diff comments   View file @ 4c10c93
... ... @@ -290,10 +290,10 @@
290 290 pci_write_config_byte(dev, 0x4b, rw_prefetch);
291 291 }
292 292  
293   -static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
  293 +static void sis_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
294 294 {
295 295 config_drive_art_rwp(drive);
296   - sis_program_timings(drive, XFER_PIO_0 + pio);
  296 + sis_program_timings(drive, drive->pio_mode);
297 297 }
298 298  
299 299 static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
300 300  
... ... @@ -340,8 +340,10 @@
340 340 sis_ata33_program_udma_timings(drive, mode);
341 341 }
342 342  
343   -static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
  343 +static void sis_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
344 344 {
  345 + const u8 speed = drive->dma_mode;
  346 +
345 347 if (speed >= XFER_UDMA_0)
346 348 sis_program_udma_timings(drive, speed);
347 349 else
drivers/ide/sl82c105.c
Diff comments   View file @ 4c10c93
... ... @@ -63,12 +63,13 @@
63 63 /*
64 64 * Configure the chipset for PIO mode.
65 65 */
66   -static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
  66 +static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
67 67 {
68   - struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
  68 + struct pci_dev *dev = to_pci_dev(hwif->dev);
69 69 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
70 70 int reg = 0x44 + drive->dn * 4;
71 71 u16 drv_ctrl;
  72 + const u8 pio = drive->pio_mode - XFER_PIO_0;
72 73  
73 74 drv_ctrl = get_pio_timings(drive, pio);
74 75  
75 76  
... ... @@ -91,11 +92,12 @@
91 92 /*
92 93 * Configure the chipset for DMA mode.
93 94 */
94   -static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
  95 +static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
95 96 {
96 97 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
97 98 unsigned long timings = (unsigned long)ide_get_drivedata(drive);
98 99 u16 drv_ctrl;
  100 + const u8 speed = drive->dma_mode;
99 101  
100 102 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
101 103  
drivers/ide/slc90e66.c
Diff comments   View file @ 4c10c93
... ... @@ -18,9 +18,8 @@
18 18  
19 19 static DEFINE_SPINLOCK(slc90e66_lock);
20 20  
21   -static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
  21 +static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
22 22 {
23   - ide_hwif_t *hwif = drive->hwif;
24 23 struct pci_dev *dev = to_pci_dev(hwif->dev);
25 24 int is_slave = drive->dn & 1;
26 25 int master_port = hwif->channel ? 0x42 : 0x40;
... ... @@ -29,6 +28,8 @@
29 28 u16 master_data;
30 29 u8 slave_data;
31 30 int control = 0;
  31 + const u8 pio = drive->pio_mode - XFER_PIO_0;
  32 +
32 33 /* ISP RTC */
33 34 static const u8 timings[][2] = {
34 35 { 0, 0 },
35 36  
36 37  
... ... @@ -71,14 +72,14 @@
71 72 spin_unlock_irqrestore(&slc90e66_lock, flags);
72 73 }
73 74  
74   -static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
  75 +static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
75 76 {
76   - ide_hwif_t *hwif = drive->hwif;
77 77 struct pci_dev *dev = to_pci_dev(hwif->dev);
78 78 u8 maslave = hwif->channel ? 0x42 : 0x40;
79 79 int sitre = 0, a_speed = 7 << (drive->dn * 4);
80 80 int u_speed = 0, u_flag = 1 << drive->dn;
81 81 u16 reg4042, reg44, reg48, reg4a;
  82 + const u8 speed = drive->dma_mode;
82 83  
83 84 pci_read_config_word(dev, maslave, &reg4042);
84 85 sitre = (reg4042 & 0x4000) ? 1 : 0;
... ... @@ -98,7 +99,6 @@
98 99 }
99 100 } else {
100 101 const u8 mwdma_to_pio[] = { 0, 3, 4 };
101   - u8 pio;
102 102  
103 103 if (reg48 & u_flag)
104 104 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
105 105  
106 106  
... ... @@ -106,11 +106,12 @@
106 106 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
107 107  
108 108 if (speed >= XFER_MW_DMA_0)
109   - pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
  109 + drive->pio_mode =
  110 + mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
110 111 else
111   - pio = 2; /* only SWDMA2 is allowed */
  112 + drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
112 113  
113   - slc90e66_set_pio_mode(drive, pio);
  114 + slc90e66_set_pio_mode(hwif, drive);
114 115 }
115 116 }
116 117  
drivers/ide/tc86c001.c
Diff comments   View file @ 4c10c93
... ... @@ -13,11 +13,11 @@
13 13  
14 14 #define DRV_NAME "tc86c001"
15 15  
16   -static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed)
  16 +static void tc86c001_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
17 17 {
18   - ide_hwif_t *hwif = drive->hwif;
19 18 unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00);
20 19 u16 mode, scr = inw(scr_port);
  20 + const u8 speed = drive->dma_mode;
21 21  
22 22 switch (speed) {
23 23 case XFER_UDMA_4: mode = 0x00c0; break;
24 24  
... ... @@ -41,9 +41,10 @@
41 41 outw(scr, scr_port);
42 42 }
43 43  
44   -static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio)
  44 +static void tc86c001_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
45 45 {
46   - tc86c001_set_mode(drive, XFER_PIO_0 + pio);
  46 + drive->dma_mode = drive->pio_mode;
  47 + tc86c001_set_mode(hwif, drive);
47 48 }
48 49  
49 50 /*
drivers/ide/triflex.c
Diff comments   View file @ 4c10c93
... ... @@ -34,9 +34,8 @@
34 34  
35 35 #define DRV_NAME "triflex"
36 36  
37   -static void triflex_set_mode(ide_drive_t *drive, const u8 speed)
  37 +static void triflex_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
38 38 {
39   - ide_hwif_t *hwif = drive->hwif;
40 39 struct pci_dev *dev = to_pci_dev(hwif->dev);
41 40 u32 triflex_timings = 0;
42 41 u16 timing = 0;
... ... @@ -44,7 +43,7 @@
44 43  
45 44 pci_read_config_dword(dev, channel_offset, &triflex_timings);
46 45  
47   - switch(speed) {
  46 + switch (drive->dma_mode) {
48 47 case XFER_MW_DMA_2:
49 48 timing = 0x0103;
50 49 break;
51 50  
... ... @@ -82,9 +81,10 @@
82 81 pci_write_config_dword(dev, channel_offset, triflex_timings);
83 82 }
84 83  
85   -static void triflex_set_pio_mode(ide_drive_t *drive, const u8 pio)
  84 +static void triflex_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
86 85 {
87   - triflex_set_mode(drive, XFER_PIO_0 + pio);
  86 + drive->dma_mode = drive->pio_mode;
  87 + triflex_set_mode(hwif, drive);
88 88 }
89 89  
90 90 static const struct ide_port_ops triflex_port_ops = {
drivers/ide/tx4938ide.c
Diff comments   View file @ 4c10c93
... ... @@ -56,16 +56,15 @@
56 56 &tx4938_ebuscptr->cr[ebus_ch]);
57 57 }
58 58  
59   -static void tx4938ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
  59 +static void tx4938ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
60 60 {
61   - ide_hwif_t *hwif = drive->hwif;
62 61 struct tx4938ide_platform_info *pdata = hwif->dev->platform_data;
63   - u8 safe = pio;
  62 + u8 safe = drive->pio_mode - XFER_PIO_0;
64 63 ide_drive_t *pair;
65 64  
66 65 pair = ide_get_pair_dev(drive);
67 66 if (pair)
68   - safe = min(safe, ide_get_best_pio_mode(pair, 255, 5));
  67 + safe = min(safe, pair->pio_mode - XFER_PIO_0);
69 68 tx4938ide_tune_ebusc(pdata->ebus_ch, pdata->gbus_clock, safe);
70 69 }
71 70  
drivers/ide/tx4939ide.c
Diff comments   View file @ 4c10c93
... ... @@ -104,17 +104,17 @@
104 104  
105 105 #define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
106 106  
107   -static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
  107 +static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
108 108 {
109   - ide_hwif_t *hwif = drive->hwif;
110 109 int is_slave = drive->dn;
111 110 u32 mask, val;
  111 + const u8 pio = drive->pio_mode - XFER_PIO_0;
112 112 u8 safe = pio;
113 113 ide_drive_t *pair;
114 114  
115 115 pair = ide_get_pair_dev(drive);
116 116 if (pair)
117   - safe = min(safe, ide_get_best_pio_mode(pair, 255, 4));
  117 + safe = min(safe, pair->pio_mode - XFER_PIO_0);
118 118 /*
119 119 * Update Command Transfer Mode for master/slave and Data
120 120 * Transfer Mode for this drive.
121 121  
122 122  
... ... @@ -125,10 +125,10 @@
125 125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
126 126 }
127 127  
128   -static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode)
  128 +static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
129 129 {
130   - ide_hwif_t *hwif = drive->hwif;
131 130 u32 mask, val;
  131 + const u8 mode = drive->dma_mode;
132 132  
133 133 /* Update Data Transfer Mode for this drive. */
134 134 if (mode >= XFER_UDMA_0)
drivers/ide/umc8672.c
Diff comments   View file @ 4c10c93
... ... @@ -104,10 +104,11 @@
104 104 speeds[0], speeds[1], speeds[2], speeds[3]);
105 105 }
106 106  
107   -static void umc_set_pio_mode(ide_drive_t *drive, const u8 pio)
  107 +static void umc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
108 108 {
109   - ide_hwif_t *hwif = drive->hwif, *mate = hwif->mate;
  109 + ide_hwif_t *mate = hwif->mate;
110 110 unsigned long uninitialized_var(flags);
  111 + const u8 pio = drive->pio_mode - XFER_PIO_0;
111 112  
112 113 printk("%s: setting umc8672 to PIO mode%d (speed %d)\n",
113 114 drive->name, pio, pio_to_umc[pio]);
drivers/ide/via82cxxx.c
Diff comments   View file @ 4c10c93
... ... @@ -6,7 +6,7 @@
6 6 * vt8235, vt8237, vt8237a
7 7 *
8 8 * Copyright (c) 2000-2002 Vojtech Pavlik
9   - * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
  9 + * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
10 10 *
11 11 * Based on the work of:
12 12 * Michel Aubry
13 13  
... ... @@ -54,7 +54,12 @@
54 54 #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
55 55 #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
56 56 #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
  57 +#define VIA_SATA_PATA 0x80 /* SATA/PATA combined configuration */
57 58  
  59 +enum {
  60 + VIA_IDFLAG_SINGLE = (1 << 1), /* single channel controller */
  61 +};
  62 +
58 63 /*
59 64 * VIA SouthBridge chips.
60 65 */
61 66  
... ... @@ -67,11 +72,13 @@
67 72 u8 udma_mask;
68 73 u8 flags;
69 74 } via_isa_bridges[] = {
70   - { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
71   - { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
72   - { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  75 + { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  76 + { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  77 + { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST | VIA_SATA_PATA },
  78 + { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
73 79 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
74 80 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
  81 + { "vt6415", PCI_DEVICE_ID_VIA_6410, 0x00, 0xff, ATA_UDMA6, VIA_BAD_AST },
75 82 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
76 83 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
77 84 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
... ... @@ -92,6 +99,7 @@
92 99 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
93 100 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
94 101 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
  102 + { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
95 103 { NULL }
96 104 };
97 105  
... ... @@ -102,6 +110,7 @@
102 110 {
103 111 struct via_isa_bridge *via_config;
104 112 unsigned int via_80w;
  113 + u8 cached_device[2];
105 114 };
106 115  
107 116 /**
108 117  
109 118  
110 119  
111 120  
112 121  
113 122  
... ... @@ -137,30 +146,45 @@
137 146 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
138 147 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
139 148 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
140   - default: return;
141 149 }
142 150  
143   - pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
  151 + /* Set UDMA unless device is not UDMA capable */
  152 + if (vdev->via_config->udma_mask) {
  153 + u8 udma_etc;
  154 +
  155 + pci_read_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, &udma_etc);
  156 +
  157 + /* clear transfer mode bit */
  158 + udma_etc &= ~0x20;
  159 +
  160 + if (timing->udma) {
  161 + /* preserve 80-wire cable detection bit */
  162 + udma_etc &= 0x10;
  163 + udma_etc |= t;
  164 + }
  165 +
  166 + pci_write_config_byte(dev, VIA_UDMA_TIMING + 3 - dn, udma_etc);
  167 + }
144 168 }
145 169  
146 170 /**
147 171 * via_set_drive - configure transfer mode
  172 + * @hwif: port
148 173 * @drive: Drive to set up
149   - * @speed: desired speed
150 174 *
151 175 * via_set_drive() computes timing values configures the chipset to
152 176 * a desired transfer mode. It also can be called by upper layers.
153 177 */
154 178  
155   -static void via_set_drive(ide_drive_t *drive, const u8 speed)
  179 +static void via_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
156 180 {
157   - ide_hwif_t *hwif = drive->hwif;
158 181 ide_drive_t *peer = ide_get_pair_dev(drive);
159 182 struct pci_dev *dev = to_pci_dev(hwif->dev);
160 183 struct ide_host *host = pci_get_drvdata(dev);
161 184 struct via82cxxx_dev *vdev = host->host_priv;
162 185 struct ide_timing t, p;
163 186 unsigned int T, UT;
  187 + const u8 speed = drive->dma_mode;
164 188  
165 189 T = 1000000000 / via_clock;
166 190  
... ... @@ -175,7 +199,7 @@
175 199 ide_timing_compute(drive, speed, &t, T, UT);
176 200  
177 201 if (peer) {
178   - ide_timing_compute(peer, peer->current_speed, &p, T, UT);
  202 + ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
179 203 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
180 204 }
181 205  
182 206  
183 207  
184 208  
185 209  
... ... @@ -184,22 +208,24 @@
184 208  
185 209 /**
186 210 * via_set_pio_mode - set host controller for PIO mode
  211 + * @hwif: port
187 212 * @drive: drive
188   - * @pio: PIO mode number
189 213 *
190 214 * A callback from the upper layers for PIO-only tuning.
191 215 */
192 216  
193   -static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
  217 +static void via_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
194 218 {
195   - via_set_drive(drive, XFER_PIO_0 + pio);
  219 + drive->dma_mode = drive->pio_mode;
  220 + via_set_drive(hwif, drive);
196 221 }
197 222  
198 223 static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
199 224 {
200 225 struct via_isa_bridge *via_config;
201 226  
202   - for (via_config = via_isa_bridges; via_config->id; via_config++)
  227 + for (via_config = via_isa_bridges;
  228 + via_config->id != PCI_DEVICE_ID_VIA_ANON; via_config++)
203 229 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
204 230 !!(via_config->flags & VIA_BAD_ID),
205 231 via_config->id, NULL))) {
... ... @@ -362,6 +388,9 @@
362 388 if (via_cable_override(pdev))
363 389 return ATA_CBL_PATA40_SHORT;
364 390  
  391 + if ((vdev->via_config->flags & VIA_SATA_PATA) && hwif->channel == 0)
  392 + return ATA_CBL_SATA;
  393 +
365 394 if ((vdev->via_80w >> hwif->channel) & 1)
366 395 return ATA_CBL_PATA80;
367 396 else
368 397  
... ... @@ -374,10 +403,66 @@
374 403 .cable_detect = via82cxxx_cable_detect,
375 404 };
376 405  
  406 +static void via_write_devctl(ide_hwif_t *hwif, u8 ctl)
  407 +{
  408 + struct via82cxxx_dev *vdev = hwif->host->host_priv;
  409 +
  410 + outb(ctl, hwif->io_ports.ctl_addr);
  411 + outb(vdev->cached_device[hwif->channel], hwif->io_ports.device_addr);
  412 +}
  413 +
  414 +static void __via_dev_select(ide_drive_t *drive, u8 select)
  415 +{
  416 + ide_hwif_t *hwif = drive->hwif;
  417 + struct via82cxxx_dev *vdev = hwif->host->host_priv;
  418 +
  419 + outb(select, hwif->io_ports.device_addr);
  420 + vdev->cached_device[hwif->channel] = select;
  421 +}
  422 +
  423 +static void via_dev_select(ide_drive_t *drive)
  424 +{
  425 + __via_dev_select(drive, drive->select | ATA_DEVICE_OBS);
  426 +}
  427 +
  428 +static void via_tf_load(ide_drive_t *drive, struct ide_taskfile *tf, u8 valid)
  429 +{
  430 + ide_hwif_t *hwif = drive->hwif;
  431 + struct ide_io_ports *io_ports = &hwif->io_ports;
  432 +
  433 + if (valid & IDE_VALID_FEATURE)
  434 + outb(tf->feature, io_ports->feature_addr);
  435 + if (valid & IDE_VALID_NSECT)
  436 + outb(tf->nsect, io_ports->nsect_addr);
  437 + if (valid & IDE_VALID_LBAL)
  438 + outb(tf->lbal, io_ports->lbal_addr);
  439 + if (valid & IDE_VALID_LBAM)
  440 + outb(tf->lbam, io_ports->lbam_addr);
  441 + if (valid & IDE_VALID_LBAH)
  442 + outb(tf->lbah, io_ports->lbah_addr);
  443 + if (valid & IDE_VALID_DEVICE)
  444 + __via_dev_select(drive, tf->device);
  445 +}
  446 +
  447 +const struct ide_tp_ops via_tp_ops = {
  448 + .exec_command = ide_exec_command,
  449 + .read_status = ide_read_status,
  450 + .read_altstatus = ide_read_altstatus,
  451 + .write_devctl = via_write_devctl,
  452 +
  453 + .dev_select = via_dev_select,
  454 + .tf_load = via_tf_load,
  455 + .tf_read = ide_tf_read,
  456 +
  457 + .input_data = ide_input_data,
  458 + .output_data = ide_output_data,
  459 +};
  460 +
377 461 static const struct ide_port_info via82cxxx_chipset __devinitdata = {
378 462 .name = DRV_NAME,
379 463 .init_chipset = init_chipset_via82cxxx,
380 464 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
  465 + .tp_ops = &via_tp_ops,
381 466 .port_ops = &via_port_ops,
382 467 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
383 468 IDE_HFLAG_POST_SET_MODE |
... ... @@ -402,11 +487,6 @@
402 487 * Find the ISA bridge and check we know what it is.
403 488 */
404 489 via_config = via_config_find(&isa);
405   - if (!via_config->id) {
406   - printk(KERN_WARNING DRV_NAME " %s: unknown chipset, skipping\n",
407   - pci_name(dev));
408   - return -ENODEV;
409   - }
410 490  
411 491 /*
412 492 * Print the boot message.
413 493  
414 494  
... ... @@ -436,11 +516,14 @@
436 516 via_clock = 33333;
437 517 }
438 518  
439   - if (idx == 0)
440   - d.host_flags |= IDE_HFLAG_NO_AUTODMA;
441   - else
  519 + if (idx == 1)
442 520 d.enablebits[1].reg = d.enablebits[0].reg = 0;
  521 + else
  522 + d.host_flags |= IDE_HFLAG_NO_AUTODMA;
443 523  
  524 + if (idx == VIA_IDFLAG_SINGLE)
  525 + d.host_flags |= IDE_HFLAG_SINGLE;
  526 +
444 527 if ((via_config->flags & VIA_NO_UNMASK) == 0)
445 528 d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
446 529  
447 530  
... ... @@ -475,8 +558,9 @@
475 558 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
476 559 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
477 560 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
478   - { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), 0 },
  561 + { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_VX855_IDE), VIA_IDFLAG_SINGLE },
479 562 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
  563 + { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6415), 1 },
480 564 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
481 565 { 0, },
482 566 };
... ... @@ -504,7 +588,7 @@
504 588 module_init(via_ide_init);
505 589 module_exit(via_ide_exit);
506 590  
507   -MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
  591 +MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz, Michel Aubry, Jeff Garzik, Andre Hedrick");
508 592 MODULE_DESCRIPTION("PCI driver module for VIA IDE");
509 593 MODULE_LICENSE("GPL");
... ... @@ -515,6 +515,8 @@
515 515 u8 init_speed; /* transfer rate set at boot */
516 516 u8 current_speed; /* current transfer rate set */
517 517 u8 desired_speed; /* desired transfer rate set */
  518 + u8 pio_mode; /* for ->set_pio_mode _only_ */
  519 + u8 dma_mode; /* for ->dma_pio_mode _only_ */
518 520 u8 dn; /* now wide spread use */
519 521 u8 acoustic; /* acoustic management */
520 522 u8 media; /* disk, cdrom, tape, floppy, ... */
... ... @@ -622,8 +624,8 @@
622 624 */
623 625 struct ide_port_ops {
624 626 void (*init_dev)(ide_drive_t *);
625   - void (*set_pio_mode)(ide_drive_t *, const u8);
626   - void (*set_dma_mode)(ide_drive_t *, const u8);
  627 + void (*set_pio_mode)(struct hwif_s *, ide_drive_t *);
  628 + void (*set_dma_mode)(struct hwif_s *, ide_drive_t *);
627 629 int (*reset_poll)(ide_drive_t *);
628 630 void (*pre_reset)(ide_drive_t *);
629 631 void (*resetproc)(ide_drive_t *);
... ... @@ -1494,7 +1496,6 @@
1494 1496 #ifdef CONFIG_IDE_XFER_MODE
1495 1497 int ide_scan_pio_blacklist(char *);
1496 1498 const char *ide_xfer_verbose(u8);
1497   -u8 ide_get_best_pio_mode(ide_drive_t *, u8, u8);
1498 1499 int ide_pio_need_iordy(ide_drive_t *, const u8);
1499 1500 int ide_set_pio_mode(ide_drive_t *, u8);
1500 1501 int ide_set_dma_mode(ide_drive_t *, u8);