MIPS: Octeon: Move some platform device registration to its own file.

There is a bunch of platform device registration in arch/mips/cavium-octeon/setup.c. We move it to its own file in preparation for adding more platform devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

MIPS: Octeon: Move some platform device registration to its own file.
There is a bunch of platform device registration in arch/mips/cavium-octeon/setup.c. We move it to its own file in preparation for adding more platform devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
David Daney · Ralf Baechle
1 parent 2ca2ebfd95
Showing 3 changed files with 166 additions and 148 deletions Side-by-side Diff
arch/mips/cavium-octeon/Makefile
arch/mips/cavium-octeon/octeon-platform.c
arch/mips/cavium-octeon/setup.c
@@ -6,10 +6,10 @@
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
 #
-# Copyright (C) 2005-2008 Cavium Networks
+# Copyright (C) 2005-2009 Cavium Networks
 #
  
-obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
+obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
  
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2009 Cavium Networks
+ * Copyright (C) 2008 Wind River Systems
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
+
+static struct octeon_cf_data octeon_cf_data;
+
+static int __init octeon_cf_device_init(void)
+{
+	union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
+	unsigned long base_ptr, region_base, region_size;
+	struct platform_device *pd;
+	struct resource cf_resources[3];
+	unsigned int num_resources;
+	int i;
+	int ret = 0;
+
+	/* Setup octeon-cf platform device if present. */
+	base_ptr = 0;
+	if (octeon_bootinfo->major_version == 1
+		&& octeon_bootinfo->minor_version >= 1) {
+		if (octeon_bootinfo->compact_flash_common_base_addr)
+			base_ptr =
+				octeon_bootinfo->compact_flash_common_base_addr;
+	} else {
+		base_ptr = 0x1d000800;
+	}
+
+	if (!base_ptr)
+		return ret;
+
+	/* Find CS0 region. */
+	for (i = 0; i < 8; i++) {
+		mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
+		region_base = mio_boot_reg_cfg.s.base << 16;
+		region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
+		if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
+		    && base_ptr < region_base + region_size)
+			break;
+	}
+	if (i >= 7) {
+		/* i and i + 1 are CS0 and CS1, both must be less than 8. */
+		goto out;
+	}
+	octeon_cf_data.base_region = i;
+	octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
+	octeon_cf_data.base_region_bias = base_ptr - region_base;
+	memset(cf_resources, 0, sizeof(cf_resources));
+	num_resources = 0;
+	cf_resources[num_resources].flags	= IORESOURCE_MEM;
+	cf_resources[num_resources].start	= region_base;
+	cf_resources[num_resources].end	= region_base + region_size - 1;
+	num_resources++;
+
+
+	if (!(base_ptr & 0xfffful)) {
+		/*
+		 * Boot loader signals availability of DMA (true_ide
+		 * mode) by setting low order bits of base_ptr to
+		 * zero.
+		 */
+
+		/* Asume that CS1 immediately follows. */
+		mio_boot_reg_cfg.u64 =
+			cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
+		region_base = mio_boot_reg_cfg.s.base << 16;
+		region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
+		if (!mio_boot_reg_cfg.s.en)
+			goto out;
+
+		cf_resources[num_resources].flags	= IORESOURCE_MEM;
+		cf_resources[num_resources].start	= region_base;
+		cf_resources[num_resources].end	= region_base + region_size - 1;
+		num_resources++;
+
+		octeon_cf_data.dma_engine = 0;
+		cf_resources[num_resources].flags	= IORESOURCE_IRQ;
+		cf_resources[num_resources].start	= OCTEON_IRQ_BOOTDMA;
+		cf_resources[num_resources].end	= OCTEON_IRQ_BOOTDMA;
+		num_resources++;
+	} else {
+		octeon_cf_data.dma_engine = -1;
+	}
+
+	pd = platform_device_alloc("pata_octeon_cf", -1);
+	if (!pd) {
+		ret = -ENOMEM;
+		goto out;
+	}
+	pd->dev.platform_data = &octeon_cf_data;
+
+	ret = platform_device_add_resources(pd, cf_resources, num_resources);
+	if (ret)
+		goto fail;
+
+	ret = platform_device_add(pd);
+	if (ret)
+		goto fail;
+
+	return ret;
+fail:
+	platform_device_put(pd);
+out:
+	return ret;
+}
+device_initcall(octeon_cf_device_init);
+
+/* Octeon Random Number Generator.  */
+static int __init octeon_rng_device_init(void)
+{
+	struct platform_device *pd;
+	int ret = 0;
+
+	struct resource rng_resources[] = {
+		{
+			.flags	= IORESOURCE_MEM,
+			.start	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
+			.end	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
+		}, {
+			.flags	= IORESOURCE_MEM,
+			.start	= cvmx_build_io_address(8, 0),
+			.end	= cvmx_build_io_address(8, 0) + 0x7
+		}
+	};
+
+	pd = platform_device_alloc("octeon_rng", -1);
+	if (!pd) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = platform_device_add_resources(pd, rng_resources,
+					    ARRAY_SIZE(rng_resources));
+	if (ret)
+		goto fail;
+
+	ret = platform_device_add(pd);
+	if (ret)
+		goto fail;
+
+	return ret;
+fail:
+	platform_device_put(pd);
+
+out:
+	return ret;
+}
+device_initcall(octeon_rng_device_init);
+
+MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Platform driver for Octeon SOC");
@@ -11,7 +11,6 @@
 #include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/irq.h>
 #include <linux/serial.h>
 #include <linux/smp.h>
 #include <linux/types.h>
@@ -33,7 +32,6 @@
 #include <asm/time.h>
  
 #include <asm/octeon/octeon.h>
-#include <asm/octeon/cvmx-rnm-defs.h>
  
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 extern void cvmx_interrupt_rsl_decode(void);
@@ -825,148 +823,4 @@
 	   CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
 	octeon_hal_setup_reserved32();
 }
-
-static struct octeon_cf_data octeon_cf_data;
-
-static int __init octeon_cf_device_init(void)
-{
-	union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
-	unsigned long base_ptr, region_base, region_size;
-	struct platform_device *pd;
-	struct resource cf_resources[3];
-	unsigned int num_resources;
-	int i;
-	int ret = 0;
-
-	/* Setup octeon-cf platform device if present. */
-	base_ptr = 0;
-	if (octeon_bootinfo->major_version == 1
-		&& octeon_bootinfo->minor_version >= 1) {
-		if (octeon_bootinfo->compact_flash_common_base_addr)
-			base_ptr =
-				octeon_bootinfo->compact_flash_common_base_addr;
-	} else {
-		base_ptr = 0x1d000800;
-	}
-
-	if (!base_ptr)
-		return ret;
-
-	/* Find CS0 region. */
-	for (i = 0; i < 8; i++) {
-		mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
-		region_base = mio_boot_reg_cfg.s.base << 16;
-		region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
-		if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
-		    && base_ptr < region_base + region_size)
-			break;
-	}
-	if (i >= 7) {
-		/* i and i + 1 are CS0 and CS1, both must be less than 8. */
-		goto out;
-	}
-	octeon_cf_data.base_region = i;
-	octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
-	octeon_cf_data.base_region_bias = base_ptr - region_base;
-	memset(cf_resources, 0, sizeof(cf_resources));
-	num_resources = 0;
-	cf_resources[num_resources].flags	= IORESOURCE_MEM;
-	cf_resources[num_resources].start	= region_base;
-	cf_resources[num_resources].end	= region_base + region_size - 1;
-	num_resources++;
-
-
-	if (!(base_ptr & 0xfffful)) {
-		/*
-		 * Boot loader signals availability of DMA (true_ide
-		 * mode) by setting low order bits of base_ptr to
-		 * zero.
-		 */
-
-		/* Asume that CS1 immediately follows. */
-		mio_boot_reg_cfg.u64 =
-			cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
-		region_base = mio_boot_reg_cfg.s.base << 16;
-		region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
-		if (!mio_boot_reg_cfg.s.en)
-			goto out;
-
-		cf_resources[num_resources].flags	= IORESOURCE_MEM;
-		cf_resources[num_resources].start	= region_base;
-		cf_resources[num_resources].end	= region_base + region_size - 1;
-		num_resources++;
-
-		octeon_cf_data.dma_engine = 0;
-		cf_resources[num_resources].flags	= IORESOURCE_IRQ;
-		cf_resources[num_resources].start	= OCTEON_IRQ_BOOTDMA;
-		cf_resources[num_resources].end	= OCTEON_IRQ_BOOTDMA;
-		num_resources++;
-	} else {
-		octeon_cf_data.dma_engine = -1;
-	}
-
-	pd = platform_device_alloc("pata_octeon_cf", -1);
-	if (!pd) {
-		ret = -ENOMEM;
-		goto out;
-	}
-	pd->dev.platform_data = &octeon_cf_data;
-
-	ret = platform_device_add_resources(pd, cf_resources, num_resources);
-	if (ret)
-		goto fail;
-
-	ret = platform_device_add(pd);
-	if (ret)
-		goto fail;
-
-	return ret;
-fail:
-	platform_device_put(pd);
-out:
-	return ret;
-}
-device_initcall(octeon_cf_device_init);
-
-/* Octeon Random Number Generator.  */
-static int __init octeon_rng_device_init(void)
-{
-	struct platform_device *pd;
-	int ret = 0;
-
-	struct resource rng_resources[] = {
-		{
-			.flags	= IORESOURCE_MEM,
-			.start	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
-			.end	= XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
-		}, {
-			.flags	= IORESOURCE_MEM,
-			.start	= cvmx_build_io_address(8, 0),
-			.end	= cvmx_build_io_address(8, 0) + 0x7
-		}
-	};
-
-	pd = platform_device_alloc("octeon_rng", -1);
-	if (!pd) {
-		ret = -ENOMEM;
-		goto out;
-	}
-
-	ret = platform_device_add_resources(pd, rng_resources,
-					    ARRAY_SIZE(rng_resources));
-	if (ret)
-		goto fail;
-
-	ret = platform_device_add(pd);
-	if (ret)
-		goto fail;
-
-	return ret;
-fail:
-	platform_device_put(pd);
-
-out:
-	return ret;
-}
-device_initcall(octeon_rng_device_init);
...	...	@@ -6,10 +6,10 @@
6	6	# License. See the file "COPYING" in the main directory of this archive
7	7	# for more details.
8	8	#
9		-# Copyright (C) 2005-2008 Cavium Networks
	9	+# Copyright (C) 2005-2009 Cavium Networks
10	10	#
11	11
12		-obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
	12	+obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
13	13	obj-y += dma-octeon.o flash_setup.o
14	14	obj-y += octeon-memcpy.o
15	15
	1	+/*
	2	+ * This file is subject to the terms and conditions of the GNU General Public
	3	+ * License. See the file "COPYING" in the main directory of this archive
	4	+ * for more details.
	5	+ *
	6	+ * Copyright (C) 2004-2009 Cavium Networks
	7	+ * Copyright (C) 2008 Wind River Systems
	8	+ */
	9	+
	10	+#include <linux/init.h>
	11	+#include <linux/irq.h>
	12	+#include <linux/module.h>
	13	+#include <linux/platform_device.h>
	14	+
	15	+#include <asm/octeon/octeon.h>
	16	+#include <asm/octeon/cvmx-rnm-defs.h>
	17	+
	18	+static struct octeon_cf_data octeon_cf_data;
	19	+
	20	+static int __init octeon_cf_device_init(void)
	21	+{
	22	+ union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
	23	+ unsigned long base_ptr, region_base, region_size;
	24	+ struct platform_device *pd;
	25	+ struct resource cf_resources[3];
	26	+ unsigned int num_resources;
	27	+ int i;
	28	+ int ret = 0;
	29	+
	30	+ /* Setup octeon-cf platform device if present. */
	31	+ base_ptr = 0;
	32	+ if (octeon_bootinfo->major_version == 1
	33	+ && octeon_bootinfo->minor_version >= 1) {
	34	+ if (octeon_bootinfo->compact_flash_common_base_addr)
	35	+ base_ptr =
	36	+ octeon_bootinfo->compact_flash_common_base_addr;
	37	+ } else {
	38	+ base_ptr = 0x1d000800;
	39	+ }
	40	+
	41	+ if (!base_ptr)
	42	+ return ret;
	43	+
	44	+ /* Find CS0 region. */
	45	+ for (i = 0; i < 8; i++) {
	46	+ mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
	47	+ region_base = mio_boot_reg_cfg.s.base << 16;
	48	+ region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
	49	+ if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
	50	+ && base_ptr < region_base + region_size)
	51	+ break;
	52	+ }
	53	+ if (i >= 7) {
	54	+ /* i and i + 1 are CS0 and CS1, both must be less than 8. */
	55	+ goto out;
	56	+ }
	57	+ octeon_cf_data.base_region = i;
	58	+ octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
	59	+ octeon_cf_data.base_region_bias = base_ptr - region_base;
	60	+ memset(cf_resources, 0, sizeof(cf_resources));
	61	+ num_resources = 0;
	62	+ cf_resources[num_resources].flags = IORESOURCE_MEM;
	63	+ cf_resources[num_resources].start = region_base;
	64	+ cf_resources[num_resources].end = region_base + region_size - 1;
	65	+ num_resources++;
	66	+
	67	+
	68	+ if (!(base_ptr & 0xfffful)) {
	69	+ /*
	70	+ * Boot loader signals availability of DMA (true_ide
	71	+ * mode) by setting low order bits of base_ptr to
	72	+ * zero.
	73	+ */
	74	+
	75	+ /* Asume that CS1 immediately follows. */
	76	+ mio_boot_reg_cfg.u64 =
	77	+ cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
	78	+ region_base = mio_boot_reg_cfg.s.base << 16;
	79	+ region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
	80	+ if (!mio_boot_reg_cfg.s.en)
	81	+ goto out;
	82	+
	83	+ cf_resources[num_resources].flags = IORESOURCE_MEM;
	84	+ cf_resources[num_resources].start = region_base;
	85	+ cf_resources[num_resources].end = region_base + region_size - 1;
	86	+ num_resources++;
	87	+
	88	+ octeon_cf_data.dma_engine = 0;
	89	+ cf_resources[num_resources].flags = IORESOURCE_IRQ;
	90	+ cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
	91	+ cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
	92	+ num_resources++;
	93	+ } else {
	94	+ octeon_cf_data.dma_engine = -1;
	95	+ }
	96	+
	97	+ pd = platform_device_alloc("pata_octeon_cf", -1);
	98	+ if (!pd) {
	99	+ ret = -ENOMEM;
	100	+ goto out;
	101	+ }
	102	+ pd->dev.platform_data = &octeon_cf_data;
	103	+
	104	+ ret = platform_device_add_resources(pd, cf_resources, num_resources);
	105	+ if (ret)
	106	+ goto fail;
	107	+
	108	+ ret = platform_device_add(pd);
	109	+ if (ret)
	110	+ goto fail;
	111	+
	112	+ return ret;
	113	+fail:
	114	+ platform_device_put(pd);
	115	+out:
	116	+ return ret;
	117	+}
	118	+device_initcall(octeon_cf_device_init);
	119	+
	120	+/* Octeon Random Number Generator. */
	121	+static int __init octeon_rng_device_init(void)
	122	+{
	123	+ struct platform_device *pd;
	124	+ int ret = 0;
	125	+
	126	+ struct resource rng_resources[] = {
	127	+ {
	128	+ .flags = IORESOURCE_MEM,
	129	+ .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
	130	+ .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
	131	+ }, {
	132	+ .flags = IORESOURCE_MEM,
	133	+ .start = cvmx_build_io_address(8, 0),
	134	+ .end = cvmx_build_io_address(8, 0) + 0x7
	135	+ }
	136	+ };
	137	+
	138	+ pd = platform_device_alloc("octeon_rng", -1);
	139	+ if (!pd) {
	140	+ ret = -ENOMEM;
	141	+ goto out;
	142	+ }
	143	+
	144	+ ret = platform_device_add_resources(pd, rng_resources,
	145	+ ARRAY_SIZE(rng_resources));
	146	+ if (ret)
	147	+ goto fail;
	148	+
	149	+ ret = platform_device_add(pd);
	150	+ if (ret)
	151	+ goto fail;
	152	+
	153	+ return ret;
	154	+fail:
	155	+ platform_device_put(pd);
	156	+
	157	+out:
	158	+ return ret;
	159	+}
	160	+device_initcall(octeon_rng_device_init);
	161	+
	162	+MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
	163	+MODULE_LICENSE("GPL");
	164	+MODULE_DESCRIPTION("Platform driver for Octeon SOC");
...	...	@@ -11,7 +11,6 @@
11	11	#include <linux/delay.h>
12	12	#include <linux/interrupt.h>
13	13	#include <linux/io.h>
14		-#include <linux/irq.h>
15	14	#include <linux/serial.h>
16	15	#include <linux/smp.h>
17	16	#include <linux/types.h>
...	...	@@ -33,7 +32,6 @@
33	32	#include <asm/time.h>
34	33
35	34	#include <asm/octeon/octeon.h>
36		-#include <asm/octeon/cvmx-rnm-defs.h>
37	35
38	36	#ifdef CONFIG_CAVIUM_DECODE_RSL
39	37	extern void cvmx_interrupt_rsl_decode(void);
...	...	@@ -825,148 +823,4 @@
825	823	CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
826	824	octeon_hal_setup_reserved32();
827	825	}
828		-
829		-static struct octeon_cf_data octeon_cf_data;
830		-
831		-static int __init octeon_cf_device_init(void)
832		-{
833		- union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
834		- unsigned long base_ptr, region_base, region_size;
835		- struct platform_device *pd;
836		- struct resource cf_resources[3];
837		- unsigned int num_resources;
838		- int i;
839		- int ret = 0;
840		-
841		- /* Setup octeon-cf platform device if present. */
842		- base_ptr = 0;
843		- if (octeon_bootinfo->major_version == 1
844		- && octeon_bootinfo->minor_version >= 1) {
845		- if (octeon_bootinfo->compact_flash_common_base_addr)
846		- base_ptr =
847		- octeon_bootinfo->compact_flash_common_base_addr;
848		- } else {
849		- base_ptr = 0x1d000800;
850		- }
851		-
852		- if (!base_ptr)
853		- return ret;
854		-
855		- /* Find CS0 region. */
856		- for (i = 0; i < 8; i++) {
857		- mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
858		- region_base = mio_boot_reg_cfg.s.base << 16;
859		- region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
860		- if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
861		- && base_ptr < region_base + region_size)
862		- break;
863		- }
864		- if (i >= 7) {
865		- /* i and i + 1 are CS0 and CS1, both must be less than 8. */
866		- goto out;
867		- }
868		- octeon_cf_data.base_region = i;
869		- octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
870		- octeon_cf_data.base_region_bias = base_ptr - region_base;
871		- memset(cf_resources, 0, sizeof(cf_resources));
872		- num_resources = 0;
873		- cf_resources[num_resources].flags = IORESOURCE_MEM;
874		- cf_resources[num_resources].start = region_base;
875		- cf_resources[num_resources].end = region_base + region_size - 1;
876		- num_resources++;
877		-
878		-
879		- if (!(base_ptr & 0xfffful)) {
880		- /*
881		- * Boot loader signals availability of DMA (true_ide
882		- * mode) by setting low order bits of base_ptr to
883		- * zero.
884		- */
885		-
886		- /* Asume that CS1 immediately follows. */
887		- mio_boot_reg_cfg.u64 =
888		- cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
889		- region_base = mio_boot_reg_cfg.s.base << 16;
890		- region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
891		- if (!mio_boot_reg_cfg.s.en)
892		- goto out;
893		-
894		- cf_resources[num_resources].flags = IORESOURCE_MEM;
895		- cf_resources[num_resources].start = region_base;
896		- cf_resources[num_resources].end = region_base + region_size - 1;
897		- num_resources++;
898		-
899		- octeon_cf_data.dma_engine = 0;
900		- cf_resources[num_resources].flags = IORESOURCE_IRQ;
901		- cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
902		- cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
903		- num_resources++;
904		- } else {
905		- octeon_cf_data.dma_engine = -1;
906		- }
907		-
908		- pd = platform_device_alloc("pata_octeon_cf", -1);
909		- if (!pd) {
910		- ret = -ENOMEM;
911		- goto out;
912		- }
913		- pd->dev.platform_data = &octeon_cf_data;
914		-
915		- ret = platform_device_add_resources(pd, cf_resources, num_resources);
916		- if (ret)
917		- goto fail;
918		-
919		- ret = platform_device_add(pd);
920		- if (ret)
921		- goto fail;
922		-
923		- return ret;
924		-fail:
925		- platform_device_put(pd);
926		-out:
927		- return ret;
928		-}
929		-device_initcall(octeon_cf_device_init);
930		-
931		-/* Octeon Random Number Generator. */
932		-static int __init octeon_rng_device_init(void)
933		-{
934		- struct platform_device *pd;
935		- int ret = 0;
936		-
937		- struct resource rng_resources[] = {
938		- {
939		- .flags = IORESOURCE_MEM,
940		- .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
941		- .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
942		- }, {
943		- .flags = IORESOURCE_MEM,
944		- .start = cvmx_build_io_address(8, 0),
945		- .end = cvmx_build_io_address(8, 0) + 0x7
946		- }
947		- };
948		-
949		- pd = platform_device_alloc("octeon_rng", -1);
950		- if (!pd) {
951		- ret = -ENOMEM;
952		- goto out;
953		- }
954		-
955		- ret = platform_device_add_resources(pd, rng_resources,
956		- ARRAY_SIZE(rng_resources));
957		- if (ret)
958		- goto fail;
959		-
960		- ret = platform_device_add(pd);
961		- if (ret)
962		- goto fail;
963		-
964		- return ret;
965		-fail:
966		- platform_device_put(pd);
967		-
968		-out:
969		- return ret;
970		-}
971		-device_initcall(octeon_rng_device_init);