Commit 539d3d8cbe5cf7597d4c4c4428aec242f9ea5185
Committed by
Mark Brown
1 parent
92e2a6f682
Exists in
master
and in
4 other branches
ASoC: DaVinci: Correct McASP FIFO initialization
McASP write FIFO registers should be modified for playback and read FIFO registers for capture. Check the PCM mode before manipulating the FIFO registers. Currently, irrespective of playback/capture both the FIFOs are enabled or disbaled. This resulted in errors in audio loopback mode. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Showing 1 changed file with 18 additions and 18 deletions Side-by-side Diff
sound/soc/davinci/davinci-mcasp.c
... | ... | @@ -378,17 +378,17 @@ |
378 | 378 | |
379 | 379 | static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream) |
380 | 380 | { |
381 | - if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
381 | + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
382 | + if (dev->txnumevt) /* enable FIFO */ | |
383 | + mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, | |
384 | + FIFO_ENABLE); | |
382 | 385 | mcasp_start_tx(dev); |
383 | - else | |
386 | + } else { | |
387 | + if (dev->rxnumevt) /* enable FIFO */ | |
388 | + mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, | |
389 | + FIFO_ENABLE); | |
384 | 390 | mcasp_start_rx(dev); |
385 | - | |
386 | - /* enable FIFO */ | |
387 | - if (dev->txnumevt) | |
388 | - mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); | |
389 | - | |
390 | - if (dev->rxnumevt) | |
391 | - mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); | |
391 | + } | |
392 | 392 | } |
393 | 393 | |
394 | 394 | static void mcasp_stop_rx(struct davinci_audio_dev *dev) |
395 | 395 | |
396 | 396 | |
... | ... | @@ -405,17 +405,17 @@ |
405 | 405 | |
406 | 406 | static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream) |
407 | 407 | { |
408 | - if (stream == SNDRV_PCM_STREAM_PLAYBACK) | |
408 | + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
409 | + if (dev->txnumevt) /* disable FIFO */ | |
410 | + mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, | |
411 | + FIFO_ENABLE); | |
409 | 412 | mcasp_stop_tx(dev); |
410 | - else | |
413 | + } else { | |
414 | + if (dev->rxnumevt) /* disable FIFO */ | |
415 | + mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, | |
416 | + FIFO_ENABLE); | |
411 | 417 | mcasp_stop_rx(dev); |
412 | - | |
413 | - /* disable FIFO */ | |
414 | - if (dev->txnumevt) | |
415 | - mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); | |
416 | - | |
417 | - if (dev->rxnumevt) | |
418 | - mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); | |
418 | + } | |
419 | 419 | } |
420 | 420 | |
421 | 421 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |