Eric Lee / linux-smarc-t335x-v3.2

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Commit 55d81aa5c11f9da510a72cc48fd59689b3e91e3a

Authored by Andy Walls
Committed by Mauro Carvalho Chehab
1 parent 57e24b629a
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

V4L/DVB (9937): cx18: Use a consistent crystal value for computing all PLL parameters 

Use a consistent crystal value of 28.636360 MHz for computing all PLL
parameters so clocks don't have relative error due to assumed crystal
value mismatches.  Also aimed to have all PLLs run their VOCs at close to
400 MHz to minimze the error of these PLLs as frequency synthesizers. Also
set the VDCLK and AIMCLK PLLs to sane values before the APU and CPU firmware
are loaded.  Also fixed I2S Master clock dividers.

Many thanks to Mike Bradley and Jeff Campbell for reporting this problem and
suggesting the solution, researching and experimenting, and performing
extensive testing to support their suggested solution.

Reported-by: Jeff Campbell <jac1dlists@gmail.com>
Reported-by: Mike Bradley <mike.bradley@incanetworks.com>
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

Showing 3 changed files with 191 additions and 45 deletions Side-by-side Diff

drivers/media/video/cx18/cx18-av-audio.c
Diff comments   View file @ 55d81aa
... ... @@ -31,27 +31,67 @@
31 31 if (freq != 32000 && freq != 44100 && freq != 48000)
32 32 return -EINVAL;
33 33  
34   - /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x10 */
35   - cx18_av_write(cx, 0x127, 0x50);
  34 + /*
  35 + * The PLL parameters are based on the external crystal frequency that
  36 + * would ideally be:
  37 + *
  38 + * NTSC Color subcarrier freq * 8 =
  39 + * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
  40 + *
  41 + * The accidents of history and rationale that explain from where this
  42 + * combination of magic numbers originate can be found in:
  43 + *
  44 + * [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
  45 + * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
  46 + *
  47 + * [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
  48 + * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
  49 + *
  50 + * As Mike Bradley has rightly pointed out, it's not the exact crystal
  51 + * frequency that matters, only that all parts of the driver and
  52 + * firmware are using the same value (close to the ideal value).
  53 + *
  54 + * Since I have a strong suspicion that, if the firmware ever assumes a
  55 + * crystal value at all, it will assume 28.636360 MHz, the crystal
  56 + * freq used in calculations in this driver will be:
  57 + *
  58 + * xtal_freq = 28.636360 MHz
  59 + *
  60 + * an error of less than 0.13 ppm which is way, way better than any off
  61 + * the shelf crystal will have for accuracy anyway.
  62 + *
  63 + * Below I aim to run the PLLs' VCOs near 400 MHz to minimze error.
  64 + *
  65 + * Many thanks to Jeff Campbell and Mike Bradley for their extensive
  66 + * investigation, experimentation, testing, and suggested solutions of
  67 + * of audio/video sync problems with SVideo and CVBS captures.
  68 + */
36 69  
37 70 if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
38 71 switch (freq) {
39 72 case 32000:
40   - /* VID_PLL and AUX_PLL */
41   - cx18_av_write4(cx, 0x108, 0x1408040f);
  73 + /*
  74 + * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  75 + * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
  76 + */
  77 + cx18_av_write4(cx, 0x108, 0x200d040f);
42 78  
43   - /* AUX_PLL_FRAC */
44   - /* 0x8.9504318a * 28,636,363.636 / 0x14 = 32000 * 384 */
45   - cx18_av_write4(cx, 0x110, 0x012a0863);
  79 + /* VID_PLL Fraction = 0x2be2fe */
  80 + /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  81 + cx18_av_write4(cx, 0x10c, 0x002be2fe);
46 82  
  83 + /* AUX_PLL Fraction = 0x176740c */
  84 + /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/
  85 + cx18_av_write4(cx, 0x110, 0x0176740c);
  86 +
47 87 /* src3/4/6_ctl */
48   - /* 0x1.f77f = (4 * 15734.26) / 32000 */
  88 + /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */
49 89 cx18_av_write4(cx, 0x900, 0x0801f77f);
50 90 cx18_av_write4(cx, 0x904, 0x0801f77f);
51 91 cx18_av_write4(cx, 0x90c, 0x0801f77f);
52 92  
53   - /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */
54   - cx18_av_write(cx, 0x127, 0x54);
  93 + /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
  94 + cx18_av_write(cx, 0x127, 0x60);
55 95  
56 96 /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */
57 97 cx18_av_write4(cx, 0x12c, 0x11202fff);
58 98  
59 99  
60 100  
61 101  
... ... @@ -65,19 +105,29 @@
65 105 break;
66 106  
67 107 case 44100:
68   - /* VID_PLL and AUX_PLL */
69   - cx18_av_write4(cx, 0x108, 0x1009040f);
  108 + /*
  109 + * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  110 + * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18
  111 + */
  112 + cx18_av_write4(cx, 0x108, 0x180e040f);
70 113  
71   - /* AUX_PLL_FRAC */
72   - /* 0x9.7635e7 * 28,636,363.63 / 0x10 = 44100 * 384 */
73   - cx18_av_write4(cx, 0x110, 0x00ec6bce);
  114 + /* VID_PLL Fraction = 0x2be2fe */
  115 + /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  116 + cx18_av_write4(cx, 0x10c, 0x002be2fe);
74 117  
  118 + /* AUX_PLL Fraction = 0x062a1f2 */
  119 + /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/
  120 + cx18_av_write4(cx, 0x110, 0x0062a1f2);
  121 +
75 122 /* src3/4/6_ctl */
76   - /* 0x1.6d59 = (4 * 15734.26) / 44100 */
  123 + /* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */
77 124 cx18_av_write4(cx, 0x900, 0x08016d59);
78 125 cx18_av_write4(cx, 0x904, 0x08016d59);
79 126 cx18_av_write4(cx, 0x90c, 0x08016d59);
80 127  
  128 + /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x18 */
  129 + cx18_av_write(cx, 0x127, 0x58);
  130 +
81 131 /* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */
82 132 cx18_av_write4(cx, 0x12c, 0x112092ff);
83 133  
84 134  
85 135  
86 136  
87 137  
... ... @@ -90,19 +140,29 @@
90 140 break;
91 141  
92 142 case 48000:
93   - /* VID_PLL and AUX_PLL */
94   - cx18_av_write4(cx, 0x108, 0x100a040f);
  143 + /*
  144 + * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  145 + * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16
  146 + */
  147 + cx18_av_write4(cx, 0x108, 0x160e040f);
95 148  
96   - /* AUX_PLL_FRAC */
97   - /* 0xa.4c6b6ea * 28,636,363.63 / 0x10 = 48000 * 384 */
98   - cx18_av_write4(cx, 0x110, 0x0098d6dd);
  149 + /* VID_PLL Fraction = 0x2be2fe */
  150 + /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  151 + cx18_av_write4(cx, 0x10c, 0x002be2fe);
99 152  
  153 + /* AUX_PLL Fraction = 0x05227ad */
  154 + /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/
  155 + cx18_av_write4(cx, 0x110, 0x005227ad);
  156 +
100 157 /* src3/4/6_ctl */
101   - /* 0x1.4faa = (4 * 15734.26) / 48000 */
  158 + /* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */
102 159 cx18_av_write4(cx, 0x900, 0x08014faa);
103 160 cx18_av_write4(cx, 0x904, 0x08014faa);
104 161 cx18_av_write4(cx, 0x90c, 0x08014faa);
105 162  
  163 + /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
  164 + cx18_av_write(cx, 0x127, 0x56);
  165 +
106 166 /* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */
107 167 cx18_av_write4(cx, 0x12c, 0x11205fff);
108 168  
109 169  
110 170  
... ... @@ -117,13 +177,20 @@
117 177 } else {
118 178 switch (freq) {
119 179 case 32000:
120   - /* VID_PLL and AUX_PLL */
121   - cx18_av_write4(cx, 0x108, 0x1e08040f);
  180 + /*
  181 + * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  182 + * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30
  183 + */
  184 + cx18_av_write4(cx, 0x108, 0x300d040f);
122 185  
123   - /* AUX_PLL_FRAC */
124   - /* 0x8.9504318 * 28,636,363.63 / 0x1e = 32000 * 256 */
125   - cx18_av_write4(cx, 0x110, 0x012a0863);
  186 + /* VID_PLL Fraction = 0x2be2fe */
  187 + /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  188 + cx18_av_write4(cx, 0x10c, 0x002be2fe);
126 189  
  190 + /* AUX_PLL Fraction = 0x176740c */
  191 + /* xtal * 0xd.bb3a060/0x30 = 32000 * 256: 393 MHz p-pd*/
  192 + cx18_av_write4(cx, 0x110, 0x0176740c);
  193 +
127 194 /* src1_ctl */
128 195 /* 0x1.0000 = 32000/32000 */
129 196 cx18_av_write4(cx, 0x8f8, 0x08010000);
... ... @@ -134,8 +201,8 @@
134 201 cx18_av_write4(cx, 0x904, 0x08020000);
135 202 cx18_av_write4(cx, 0x90c, 0x08020000);
136 203  
137   - /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x14 */
138   - cx18_av_write(cx, 0x127, 0x54);
  204 + /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x30 */
  205 + cx18_av_write(cx, 0x127, 0x70);
139 206  
140 207 /* AUD_COUNT = 0x1fff = 8 samples * 4 * 256 - 1 */
141 208 cx18_av_write4(cx, 0x12c, 0x11201fff);
142 209  
143 210  
... ... @@ -149,13 +216,20 @@
149 216 break;
150 217  
151 218 case 44100:
152   - /* VID_PLL and AUX_PLL */
153   - cx18_av_write4(cx, 0x108, 0x1809040f);
  219 + /*
  220 + * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  221 + * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24
  222 + */
  223 + cx18_av_write4(cx, 0x108, 0x240e040f);
154 224  
155   - /* AUX_PLL_FRAC */
156   - /* 0x9.7635e74 * 28,636,363.63 / 0x18 = 44100 * 256 */
157   - cx18_av_write4(cx, 0x110, 0x00ec6bce);
  225 + /* VID_PLL Fraction = 0x2be2fe */
  226 + /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  227 + cx18_av_write4(cx, 0x10c, 0x002be2fe);
158 228  
  229 + /* AUX_PLL Fraction = 0x062a1f2 */
  230 + /* xtal * 0xe.3150f90/0x24 = 44100 * 256: 406 MHz p-pd*/
  231 + cx18_av_write4(cx, 0x110, 0x0062a1f2);
  232 +
159 233 /* src1_ctl */
160 234 /* 0x1.60cd = 44100/32000 */
161 235 cx18_av_write4(cx, 0x8f8, 0x080160cd);
... ... @@ -166,6 +240,9 @@
166 240 cx18_av_write4(cx, 0x904, 0x08017385);
167 241 cx18_av_write4(cx, 0x90c, 0x08017385);
168 242  
  243 + /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x24 */
  244 + cx18_av_write(cx, 0x127, 0x64);
  245 +
169 246 /* AUD_COUNT = 0x61ff = 49 samples * 2 * 256 - 1 */
170 247 cx18_av_write4(cx, 0x12c, 0x112061ff);
171 248  
172 249  
173 250  
... ... @@ -178,13 +255,20 @@
178 255 break;
179 256  
180 257 case 48000:
181   - /* VID_PLL and AUX_PLL */
182   - cx18_av_write4(cx, 0x108, 0x180a040f);
  258 + /*
  259 + * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  260 + * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
  261 + */
  262 + cx18_av_write4(cx, 0x108, 0x200d040f);
183 263  
184   - /* AUX_PLL_FRAC */
185   - /* 0xa.4c6b6ea * 28,636,363.63 / 0x18 = 48000 * 256 */
186   - cx18_av_write4(cx, 0x110, 0x0098d6dd);
  264 + /* VID_PLL Fraction = 0x2be2fe */
  265 + /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  266 + cx18_av_write4(cx, 0x10c, 0x002be2fe);
187 267  
  268 + /* AUX_PLL Fraction = 0x176740c */
  269 + /* xtal * 0xd.bb3a060/0x20 = 48000 * 256: 393 MHz p-pd*/
  270 + cx18_av_write4(cx, 0x110, 0x0176740c);
  271 +
188 272 /* src1_ctl */
189 273 /* 0x1.8000 = 48000/32000 */
190 274 cx18_av_write4(cx, 0x8f8, 0x08018000);
... ... @@ -194,6 +278,9 @@
194 278 cx18_av_write4(cx, 0x900, 0x08015555);
195 279 cx18_av_write4(cx, 0x904, 0x08015555);
196 280 cx18_av_write4(cx, 0x90c, 0x08015555);
  281 +
  282 + /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
  283 + cx18_av_write(cx, 0x127, 0x60);
197 284  
198 285 /* AUD_COUNT = 0x3fff = 4 samples * 16 * 256 - 1 */
199 286 cx18_av_write4(cx, 0x12c, 0x11203fff);
drivers/media/video/cx18/cx18-av-core.c
Diff comments   View file @ 55d81aa
... ... @@ -271,7 +271,7 @@
271 271 if (pll_post) {
272 272 int fin, fsc, pll;
273 273  
274   - pll = (28636364L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
  274 + pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
275 275 pll /= pll_post;
276 276 CX18_DEBUG_INFO("PLL = %d.%06d MHz\n",
277 277 pll / 1000000, pll % 1000000);
drivers/media/video/cx18/cx18-firmware.c
Diff comments   View file @ 55d81aa
... ... @@ -26,6 +26,7 @@
26 26 #include "cx18-irq.h"
27 27 #include "cx18-firmware.h"
28 28 #include "cx18-cards.h"
  29 +#include "cx18-av-core.h"
29 30 #include <linux/firmware.h>
30 31  
31 32 #define CX18_PROC_SOFT_RESET 0xc70010
... ... @@ -224,7 +225,45 @@
224 225 cx18_write_reg_expect(cx, 0x00020000, CX18_ADEC_CONTROL,
225 226 0x00000000, 0x00020002);
226 227  
227   - /* The fast clock is at 200/245 MHz */
  228 + /*
  229 + * The PLL parameters are based on the external crystal frequency that
  230 + * would ideally be:
  231 + *
  232 + * NTSC Color subcarrier freq * 8 =
  233 + * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
  234 + *
  235 + * The accidents of history and rationale that explain from where this
  236 + * combination of magic numbers originate can be found in:
  237 + *
  238 + * [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
  239 + * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
  240 + *
  241 + * [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
  242 + * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
  243 + *
  244 + * As Mike Bradley has rightly pointed out, it's not the exact crystal
  245 + * frequency that matters, only that all parts of the driver and
  246 + * firmware are using the same value (close to the ideal value).
  247 + *
  248 + * Since I have a strong suspicion that, if the firmware ever assumes a
  249 + * crystal value at all, it will assume 28.636360 MHz, the crystal
  250 + * freq used in calculations in this driver will be:
  251 + *
  252 + * xtal_freq = 28.636360 MHz
  253 + *
  254 + * an error of less than 0.13 ppm which is way, way better than any off
  255 + * the shelf crystal will have for accuracy anyway.
  256 + *
  257 + * Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors.
  258 + *
  259 + * Many thanks to Jeff Campbell and Mike Bradley for their extensive
  260 + * investigation, experimentation, testing, and suggested solutions of
  261 + * of audio/video sync problems with SVideo and CVBS captures.
  262 + */
  263 +
  264 + /* the fast clock is at 200/245 MHz */
  265 + /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/
  266 + /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/
228 267 cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
229 268 cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
230 269 CX18_FAST_CLOCK_PLL_FRAC);
231 270  
232 271  
233 272  
234 273  
... ... @@ -234,15 +273,35 @@
234 273 cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
235 274  
236 275 /* set slow clock to 125/120 MHz */
237   - cx18_write_reg(cx, lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
238   - cx18_write_reg(cx, lowpwr ? 0xEBAF05 : 0x18618A8,
  276 + /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */
  277 + /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */
  278 + cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
  279 + cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
239 280 CX18_SLOW_CLOCK_PLL_FRAC);
240   - cx18_write_reg(cx, 4, CX18_SLOW_CLOCK_PLL_POST);
  281 + cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
241 282  
242 283 /* mpeg clock pll 54MHz */
  284 + /* xtal_freq * 0xf.15f17f0 / 8 = 54 MHz: 432 MHz before post-divide */
243 285 cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
244   - cx18_write_reg(cx, 0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
  286 + cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
245 287 cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
  288 +
  289 + /*
  290 + * VDCLK Integer = 0x0f, Post Divider = 0x04
  291 + * AIMCLK Integer = 0x0e, Post Divider = 0x16
  292 + */
  293 + cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
  294 +
  295 + /* VDCLK Fraction = 0x2be2fe */
  296 + /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
  297 + cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
  298 +
  299 + /* AIMCLK Fraction = 0x05227ad */
  300 + /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz before post-divide */
  301 + cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
  302 +
  303 + /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
  304 + cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
246 305  
247 306 /* Defaults */
248 307 /* APU = SC or SC/2 = 125/62.5 */