Commit 565a55c81567b5478d8d7a0f4fe23171ef2e9827
1 parent
12ad41c225
Exists in
master
ARM:omap:am33xx: CPSW removes dmtimer re enabling
This patch is added to remove unwanted dmtimer re enabling code after reseting timer status register. Also, some additional cleanup is done in this patch. Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Showing 2 changed files with 17 additions and 35 deletions Side-by-side Diff
drivers/net/cpsw.c
| ... | ... | @@ -97,8 +97,8 @@ |
| 97 | 97 | #define CPSW_RX_TIMER_REQ 5 |
| 98 | 98 | #define CPSW_TX_TIMER_REQ 6 |
| 99 | 99 | |
| 100 | -struct omap_dm_timer *stTimerRx; | |
| 101 | -struct omap_dm_timer *stTimerTx; | |
| 100 | +struct omap_dm_timer *dmtimer_rx; | |
| 101 | +struct omap_dm_timer *dmtimer_tx; | |
| 102 | 102 | |
| 103 | 103 | extern u32 omap_ctrl_readl(u16 offset); |
| 104 | 104 | extern void omap_ctrl_writel(u32 val, u16 offset); |
| ... | ... | @@ -273,8 +273,6 @@ |
| 273 | 273 | static int cpsw_set_coalesce(struct net_device *ndev, |
| 274 | 274 | struct ethtool_coalesce *coal); |
| 275 | 275 | |
| 276 | -static void __iomem *cpdma_base; | |
| 277 | - | |
| 278 | 276 | static void cpsw_intr_enable(struct cpsw_priv *priv) |
| 279 | 277 | { |
| 280 | 278 | __raw_writel(0xFF, &priv->ss_regs->tx_en); |
| 281 | 279 | |
| ... | ... | @@ -344,19 +342,9 @@ |
| 344 | 342 | |
| 345 | 343 | static void set_cpsw_dmtimer_clear(void) |
| 346 | 344 | { |
| 347 | - omap_dm_timer_write_status(stTimerRx, OMAP_TIMER_INT_CAPTURE); | |
| 348 | - omap_dm_timer_write_status(stTimerTx, OMAP_TIMER_INT_CAPTURE); | |
| 345 | + omap_dm_timer_write_status(dmtimer_rx, OMAP_TIMER_INT_CAPTURE); | |
| 346 | + omap_dm_timer_write_status(dmtimer_tx, OMAP_TIMER_INT_CAPTURE); | |
| 349 | 347 | |
| 350 | - omap_dm_timer_disable(stTimerRx); | |
| 351 | - omap_dm_timer_set_int_enable(stTimerRx, OMAP_TIMER_INT_CAPTURE); | |
| 352 | - omap_dm_timer_set_capture(stTimerRx, 1, 0, 0); | |
| 353 | - omap_dm_timer_enable(stTimerRx); | |
| 354 | - | |
| 355 | - omap_dm_timer_disable(stTimerTx); | |
| 356 | - omap_dm_timer_set_int_enable(stTimerTx, OMAP_TIMER_INT_CAPTURE); | |
| 357 | - omap_dm_timer_set_capture(stTimerTx, 1, 0, 0); | |
| 358 | - omap_dm_timer_enable(stTimerTx); | |
| 359 | - | |
| 360 | 348 | return; |
| 361 | 349 | } |
| 362 | 350 | |
| ... | ... | @@ -387,8 +375,6 @@ |
| 387 | 375 | if (num_rx < budget) { |
| 388 | 376 | napi_complete(napi); |
| 389 | 377 | cpdma_ctlr_eoi(priv->dma); |
| 390 | - __raw_writel(0x1, cpdma_base + CPSW_CPDMA_EOI_REG); | |
| 391 | - __raw_writel(0x2, cpdma_base + CPSW_CPDMA_EOI_REG); | |
| 392 | 378 | set_cpsw_dmtimer_clear(); |
| 393 | 379 | cpsw_intr_enable(priv); |
| 394 | 380 | cpsw_enable_irq(priv); |
| ... | ... | @@ -1036,12 +1022,6 @@ |
| 1036 | 1022 | struct resource *res; |
| 1037 | 1023 | int ret = 0, i, k = 0; |
| 1038 | 1024 | |
| 1039 | - cpdma_base = ioremap(AM33XX_CPSW_BASE, SZ_4K); | |
| 1040 | - if (WARN_ON(!cpdma_base)) { | |
| 1041 | - printk(KERN_ERR"errror: %s: ioremap", __func__); | |
| 1042 | - return -ENODEV; | |
| 1043 | - } | |
| 1044 | - | |
| 1045 | 1025 | if (!data) { |
| 1046 | 1026 | pr_err("cpsw: platform data missing\n"); |
| 1047 | 1027 | return -ENODEV; |
| 1048 | 1028 | |
| ... | ... | @@ -1147,17 +1127,17 @@ |
| 1147 | 1127 | |
| 1148 | 1128 | omap_ctrl_writel(CPSW_TIMER_MASK, CPSW_TIMER_CAP_REG); |
| 1149 | 1129 | |
| 1150 | - /* Enable Timer */ | |
| 1151 | - stTimerRx = omap_dm_timer_request_specific(CPSW_RX_TIMER_REQ); | |
| 1152 | - omap_dm_timer_set_int_enable(stTimerRx, OMAP_TIMER_INT_CAPTURE); | |
| 1153 | - omap_dm_timer_set_capture(stTimerRx, 1, 0, 0); | |
| 1154 | - omap_dm_timer_enable(stTimerRx); | |
| 1130 | + /* Enable Timer for capturing cpsw rx interrupts */ | |
| 1131 | + dmtimer_rx = omap_dm_timer_request_specific(CPSW_RX_TIMER_REQ); | |
| 1132 | + omap_dm_timer_set_int_enable(dmtimer_rx, OMAP_TIMER_INT_CAPTURE); | |
| 1133 | + omap_dm_timer_set_capture(dmtimer_rx, 1, 0, 0); | |
| 1134 | + omap_dm_timer_enable(dmtimer_rx); | |
| 1155 | 1135 | |
| 1156 | - /* Enable Timer */ | |
| 1157 | - stTimerTx = omap_dm_timer_request_specific(CPSW_TX_TIMER_REQ); | |
| 1158 | - omap_dm_timer_set_int_enable(stTimerTx, OMAP_TIMER_INT_CAPTURE); | |
| 1159 | - omap_dm_timer_set_capture(stTimerTx, 1, 0, 0); | |
| 1160 | - omap_dm_timer_enable(stTimerTx); | |
| 1136 | + /* Enable Timer for capturing cpsw tx interrupts */ | |
| 1137 | + dmtimer_tx = omap_dm_timer_request_specific(CPSW_TX_TIMER_REQ); | |
| 1138 | + omap_dm_timer_set_int_enable(dmtimer_tx, OMAP_TIMER_INT_CAPTURE); | |
| 1139 | + omap_dm_timer_set_capture(dmtimer_tx, 1, 0, 0); | |
| 1140 | + omap_dm_timer_enable(dmtimer_tx); | |
| 1161 | 1141 | |
| 1162 | 1142 | memset(&dma_params, 0, sizeof(dma_params)); |
| 1163 | 1143 | dma_params.dev = &pdev->dev; |
drivers/net/davinci_cpdma.c
| ... | ... | @@ -471,6 +471,8 @@ |
| 471 | 471 | void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr) |
| 472 | 472 | { |
| 473 | 473 | dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0); |
| 474 | + dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 1); | |
| 475 | + dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 2); | |
| 474 | 476 | } |
| 475 | 477 | |
| 476 | 478 | struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, |