Eric Lee / linux-smarc-t335x-v3.2

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Commit 58cda884ecc87dcce18d463b0c8bd928dae63ad8

Authored by Jean Pihet
Committed by paul
1 parent 4be3bd7849
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

OMAP3 SDRC: add support for 2 SDRAM chip selects 

Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2
SDRAM parts connected to the SDRC.

This patch adds the following:
- add a new argument of type omap_sdrc_params struct*
to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params
- adapted the OMAP boards files to the new prototype of
omap2_init_common_hw
- add the SDRC 2nd CS registers offsets defines
- adapt the sram sleep code to configure the SDRC for the 2nd CS

Note: If the 2nd param to omap2_init_common_hw is NULL, then the
parameters are not programmed into the SDRC CS1 registers

Tested on 3430 SDP and Beagleboard rev C2 and B5, with
suspend/resume and frequency changes (cpufreq).

Signed-off-by: Jean Pihet <jpihet@mvista.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Showing 21 changed files with 236 additions and 102 deletions Side-by-side Diff

arch/arm/mach-omap2/board-2430sdp.c
Diff comments   View file @ 58cda88
... ... @@ -141,7 +141,7 @@
141 141  
142 142 static void __init omap_2430sdp_init_irq(void)
143 143 {
144   - omap2_init_common_hw(NULL);
  144 + omap2_init_common_hw(NULL, NULL);
145 145 omap_init_irq();
146 146 omap_gpio_init();
147 147 }
arch/arm/mach-omap2/board-3430sdp.c
Diff comments   View file @ 58cda88
... ... @@ -169,7 +169,7 @@
169 169  
170 170 static void __init omap_3430sdp_init_irq(void)
171 171 {
172   - omap2_init_common_hw(hyb18m512160af6_sdrc_params);
  172 + omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
173 173 omap_init_irq();
174 174 omap_gpio_init();
175 175 }
arch/arm/mach-omap2/board-4430sdp.c
Diff comments   View file @ 58cda88
... ... @@ -59,7 +59,7 @@
59 59  
60 60 static void __init omap_4430sdp_init_irq(void)
61 61 {
62   - omap2_init_common_hw(NULL);
  62 + omap2_init_common_hw(NULL, NULL);
63 63 #ifdef CONFIG_OMAP_32K_TIMER
64 64 omap2_gp_clockevent_set_gptimer(1);
65 65 #endif
arch/arm/mach-omap2/board-apollon.c
Diff comments   View file @ 58cda88
... ... @@ -250,7 +250,7 @@
250 250  
251 251 static void __init omap_apollon_init_irq(void)
252 252 {
253   - omap2_init_common_hw(NULL);
  253 + omap2_init_common_hw(NULL, NULL);
254 254 omap_init_irq();
255 255 omap_gpio_init();
256 256 apollon_init_smc91x();
arch/arm/mach-omap2/board-generic.c
Diff comments   View file @ 58cda88
... ... @@ -33,7 +33,7 @@
33 33  
34 34 static void __init omap_generic_init_irq(void)
35 35 {
36   - omap2_init_common_hw(NULL);
  36 + omap2_init_common_hw(NULL, NULL);
37 37 omap_init_irq();
38 38 }
39 39  
arch/arm/mach-omap2/board-h4.c
Diff comments   View file @ 58cda88
... ... @@ -270,7 +270,7 @@
270 270  
271 271 static void __init omap_h4_init_irq(void)
272 272 {
273   - omap2_init_common_hw(NULL);
  273 + omap2_init_common_hw(NULL, NULL);
274 274 omap_init_irq();
275 275 omap_gpio_init();
276 276 h4_init_flash();
arch/arm/mach-omap2/board-ldp.c
Diff comments   View file @ 58cda88
... ... @@ -270,7 +270,7 @@
270 270  
271 271 static void __init omap_ldp_init_irq(void)
272 272 {
273   - omap2_init_common_hw(NULL);
  273 + omap2_init_common_hw(NULL, NULL);
274 274 omap_init_irq();
275 275 omap_gpio_init();
276 276 ldp_init_smsc911x();
arch/arm/mach-omap2/board-omap3beagle.c
Diff comments   View file @ 58cda88
... ... @@ -282,7 +282,8 @@
282 282  
283 283 static void __init omap3_beagle_init_irq(void)
284 284 {
285   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  285 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
  286 + mt46h32m32lf6_sdrc_params);
286 287 omap_init_irq();
287 288 #ifdef CONFIG_OMAP_32K_TIMER
288 289 omap2_gp_clockevent_set_gptimer(12);
arch/arm/mach-omap2/board-omap3evm.c
Diff comments   View file @ 58cda88
... ... @@ -279,7 +279,7 @@
279 279  
280 280 static void __init omap3_evm_init_irq(void)
281 281 {
282   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  282 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
283 283 omap_init_irq();
284 284 omap_gpio_init();
285 285 omap3evm_init_smc911x();
arch/arm/mach-omap2/board-omap3pandora.c
Diff comments   View file @ 58cda88
... ... @@ -310,7 +310,8 @@
310 310  
311 311 static void __init omap3pandora_init_irq(void)
312 312 {
313   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  313 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
  314 + mt46h32m32lf6_sdrc_params);
314 315 omap_init_irq();
315 316 omap_gpio_init();
316 317 }
arch/arm/mach-omap2/board-overo.c
Diff comments   View file @ 58cda88
... ... @@ -360,7 +360,8 @@
360 360  
361 361 static void __init overo_init_irq(void)
362 362 {
363   - omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
  363 + omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
  364 + mt46h32m32lf6_sdrc_params);
364 365 omap_init_irq();
365 366 omap_gpio_init();
366 367 }
arch/arm/mach-omap2/board-rx51.c
Diff comments   View file @ 58cda88
... ... @@ -61,7 +61,7 @@
61 61  
62 62 static void __init rx51_init_irq(void)
63 63 {
64   - omap2_init_common_hw(NULL);
  64 + omap2_init_common_hw(NULL, NULL);
65 65 omap_init_irq();
66 66 omap_gpio_init();
67 67 }
arch/arm/mach-omap2/board-zoom2.c
Diff comments   View file @ 58cda88
... ... @@ -25,7 +25,7 @@
25 25  
26 26 static void __init omap_zoom2_init_irq(void)
27 27 {
28   - omap2_init_common_hw(NULL);
  28 + omap2_init_common_hw(NULL, NULL);
29 29 omap_init_irq();
30 30 omap_gpio_init();
31 31 }
arch/arm/mach-omap2/clock34xx.c
Diff comments   View file @ 58cda88
... ... @@ -725,7 +725,9 @@
725 725 u32 unlock_dll = 0;
726 726 u32 c;
727 727 unsigned long validrate, sdrcrate, mpurate;
728   - struct omap_sdrc_params *sp;
  728 + struct omap_sdrc_params *sdrc_cs0;
  729 + struct omap_sdrc_params *sdrc_cs1;
  730 + int ret;
729 731  
730 732 if (!clk || !rate)
731 733 return -EINVAL;
... ... @@ -743,8 +745,8 @@
743 745 else
744 746 sdrcrate >>= ((clk->rate / rate) >> 1);
745 747  
746   - sp = omap2_sdrc_get_params(sdrcrate);
747   - if (!sp)
  748 + ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
  749 + if (ret)
748 750 return -EINVAL;
749 751  
750 752 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
751 753  
... ... @@ -765,12 +767,29 @@
765 767  
766 768 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
767 769 validrate);
768   - pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
769   - sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
  770 + pr_debug("clock: SDRC CS0 timing params used:"
  771 + " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  772 + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  773 + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
  774 + if (sdrc_cs1)
  775 + pr_debug("clock: SDRC CS1 timing params used: "
  776 + " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  777 + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
  778 + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
770 779  
771   - omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
772   - sp->actim_ctrlb, new_div, unlock_dll, c,
773   - sp->mr, rate > clk->rate);
  780 + if (sdrc_cs1)
  781 + omap3_configure_core_dpll(
  782 + new_div, unlock_dll, c, rate > clk->rate,
  783 + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  784 + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
  785 + sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
  786 + sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
  787 + else
  788 + omap3_configure_core_dpll(
  789 + new_div, unlock_dll, c, rate > clk->rate,
  790 + sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  791 + sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
  792 + 0, 0, 0, 0);
774 793  
775 794 return 0;
776 795 }
arch/arm/mach-omap2/io.c
Diff comments   View file @ 58cda88
... ... @@ -276,14 +276,15 @@
276 276 return v;
277 277 }
278 278  
279   -void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
  279 +void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
  280 + struct omap_sdrc_params *sdrc_cs1)
280 281 {
281 282 omap2_mux_init();
282 283 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
283 284 pwrdm_init(powerdomains_omap);
284 285 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
285 286 omap2_clk_init();
286   - omap2_sdrc_init(sp);
  287 + omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
287 288 _omap2_init_reprogram_sdrc();
288 289 #endif
289 290 gpmc_init();
arch/arm/mach-omap2/sdrc.c
Diff comments   View file @ 58cda88
... ... @@ -32,7 +32,7 @@
32 32 #include <mach/sdrc.h>
33 33 #include "sdrc.h"
34 34  
35   -static struct omap_sdrc_params *sdrc_init_params;
  35 +static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
36 36  
37 37 void __iomem *omap2_sdrc_base;
38 38 void __iomem *omap2_sms_base;
39 39  
40 40  
41 41  
42 42  
43 43  
44 44  
45 45  
46 46  
... ... @@ -45,33 +45,49 @@
45 45 /**
46 46 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
47 47 * @r: SDRC clock rate (in Hz)
  48 + * @sdrc_cs0: chip select 0 ram timings **
  49 + * @sdrc_cs1: chip select 1 ram timings **
48 50 *
49 51 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
50   - * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
51   - * SDRC clock rate 'r'. These parameters control various timing
52   - * delays in the SDRAM controller that are expressed in terms of the
53   - * number of SDRC clock cycles to wait; hence the clock rate
54   - * dependency. Note that sdrc_init_params must be sorted rate
55   - * descending. Also assumes that both chip-selects use the same
56   - * timing parameters. Returns a struct omap_sdrc_params * upon
57   - * success, or NULL upon failure.
  52 + * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
  53 + * structs,for a given SDRC clock rate 'r'.
  54 + * These parameters control various timing delays in the SDRAM controller
  55 + * that are expressed in terms of the number of SDRC clock cycles to
  56 + * wait; hence the clock rate dependency.
  57 + *
  58 + * Supports 2 different timing parameters for both chip selects.
  59 + *
  60 + * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
  61 + * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
  62 + * as sdrc_init_params_cs_0.
  63 + *
  64 + * Fills in the struct omap_sdrc_params * for each chip select.
  65 + * Returns 0 upon success or -1 upon failure.
58 66 */
59   -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
  67 +int omap2_sdrc_get_params(unsigned long r,
  68 + struct omap_sdrc_params **sdrc_cs0,
  69 + struct omap_sdrc_params **sdrc_cs1)
60 70 {
61   - struct omap_sdrc_params *sp;
  71 + struct omap_sdrc_params *sp0, *sp1;
62 72  
63   - if (!sdrc_init_params)
64   - return NULL;
  73 + if (!sdrc_init_params_cs0)
  74 + return -1;
65 75  
66   - sp = sdrc_init_params;
  76 + sp0 = sdrc_init_params_cs0;
  77 + sp1 = sdrc_init_params_cs1;
67 78  
68   - while (sp->rate && sp->rate != r)
69   - sp++;
  79 + while (sp0->rate && sp0->rate != r) {
  80 + sp0++;
  81 + if (sdrc_init_params_cs1)
  82 + sp1++;
  83 + }
70 84  
71   - if (!sp->rate)
72   - return NULL;
  85 + if (!sp0->rate)
  86 + return -1;
73 87  
74   - return sp;
  88 + *sdrc_cs0 = sp0;
  89 + *sdrc_cs1 = sp1;
  90 + return 0;
75 91 }
76 92  
77 93  
78 94  
... ... @@ -83,13 +99,15 @@
83 99  
84 100 /**
85 101 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
86   - * @sp: pointer to a null-terminated list of struct omap_sdrc_params
  102 + * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
  103 + * Support for 2 chip selects timings
87 104 *
88 105 * Turn on smart idle modes for SDRAM scheduler and controller.
89 106 * Program a known-good configuration for the SDRC to deal with buggy
90 107 * bootloaders.
91 108 */
92   -void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
  109 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  110 + struct omap_sdrc_params *sdrc_cs1)
93 111 {
94 112 u32 l;
95 113  
... ... @@ -103,7 +121,8 @@
103 121 l |= (0x2 << 3);
104 122 sdrc_write_reg(l, SDRC_SYSCONFIG);
105 123  
106   - sdrc_init_params = sp;
  124 + sdrc_init_params_cs0 = sdrc_cs0;
  125 + sdrc_init_params_cs1 = sdrc_cs1;
107 126  
108 127 /* XXX Enable SRFRONIDLEREQ here also? */
109 128 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
arch/arm/mach-omap2/sram34xx.S
Diff comments   View file @ 58cda88
... ... @@ -36,7 +36,7 @@
36 36  
37 37 .text
38 38  
39   -/* r4 parameters */
  39 +/* r1 parameters */
40 40 #define SDRC_NO_UNLOCK_DLL 0x0
41 41 #define SDRC_UNLOCK_DLL 0x1
42 42  
43 43  
44 44  
45 45  
46 46  
47 47  
48 48  
49 49  
50 50  
51 51  
... ... @@ -71,40 +71,71 @@
71 71  
72 72 /*
73 73 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
74   - * r0 = new SDRC_RFR_CTRL register contents
75   - * r1 = new SDRC_ACTIM_CTRLA register contents
76   - * r2 = new SDRC_ACTIM_CTRLB register contents
77   - * r3 = new M2 divider setting (only 1 and 2 supported right now)
78   - * r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
  74 + *
  75 + * Params passed in registers:
  76 + * r0 = new M2 divider setting (only 1 and 2 supported right now)
  77 + * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
79 78 * SDRC rates < 83MHz
80   - * r5 = number of MPU cycles to wait for SDRC to stabilize after
  79 + * r2 = number of MPU cycles to wait for SDRC to stabilize after
81 80 * reprogramming the SDRC when switching to a slower MPU speed
82   - * r6 = new SDRC_MR_0 register value
83   - * r7 = increasing SDRC rate? (1 = yes, 0 = no)
  81 + * r3 = increasing SDRC rate? (1 = yes, 0 = no)
84 82 *
  83 + * Params passed via the stack. The needed params will be copied in SRAM
  84 + * before use by the code in SRAM (SDRAM is not accessible during SDRC
  85 + * reconfiguration):
  86 + * new SDRC_RFR_CTRL_0 register contents
  87 + * new SDRC_ACTIM_CTRL_A_0 register contents
  88 + * new SDRC_ACTIM_CTRL_B_0 register contents
  89 + * new SDRC_MR_0 register value
  90 + * new SDRC_RFR_CTRL_1 register contents
  91 + * new SDRC_ACTIM_CTRL_A_1 register contents
  92 + * new SDRC_ACTIM_CTRL_B_1 register contents
  93 + * new SDRC_MR_1 register value
  94 + *
  95 + * If the param SDRC_RFR_CTRL_1 is 0, the parameters
  96 + * are not programmed into the SDRC CS1 registers
85 97 */
86 98 ENTRY(omap3_sram_configure_core_dpll)
87 99 stmfd sp!, {r1-r12, lr} @ store regs to stack
88   - ldr r4, [sp, #52] @ pull extra args off the stack
89   - ldr r5, [sp, #56] @ load extra args from the stack
90   - ldr r6, [sp, #60] @ load extra args from the stack
91   - ldr r7, [sp, #64] @ load extra args from the stack
  100 +
  101 + @ pull the extra args off the stack
  102 + @ and store them in SRAM
  103 + ldr r4, [sp, #52]
  104 + str r4, omap_sdrc_rfr_ctrl_0_val
  105 + ldr r4, [sp, #56]
  106 + str r4, omap_sdrc_actim_ctrl_a_0_val
  107 + ldr r4, [sp, #60]
  108 + str r4, omap_sdrc_actim_ctrl_b_0_val
  109 + ldr r4, [sp, #64]
  110 + str r4, omap_sdrc_mr_0_val
  111 + ldr r4, [sp, #68]
  112 + str r4, omap_sdrc_rfr_ctrl_1_val
  113 + cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
  114 + beq skip_cs1_params @ do not use cs1 params
  115 + ldr r4, [sp, #72]
  116 + str r4, omap_sdrc_actim_ctrl_a_1_val
  117 + ldr r4, [sp, #76]
  118 + str r4, omap_sdrc_actim_ctrl_b_1_val
  119 + ldr r4, [sp, #80]
  120 + str r4, omap_sdrc_mr_1_val
  121 +skip_cs1_params:
92 122 dsb @ flush buffered writes to interconnect
93   - cmp r7, #1 @ if increasing SDRC clk rate,
  123 +
  124 + cmp r3, #1 @ if increasing SDRC clk rate,
94 125 bleq configure_sdrc @ program the SDRC regs early (for RFR)
95   - cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
  126 + cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
96 127 bleq unlock_dll
97 128 blne lock_dll
98 129 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
99 130 bl configure_core_dpll @ change the DPLL3 M2 divider
100 131 bl enable_sdrc @ take SDRC out of idle
101   - cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
  132 + cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
102 133 bleq wait_dll_unlock
103 134 blne wait_dll_lock
104   - cmp r7, #1 @ if increasing SDRC clk rate,
  135 + cmp r3, #1 @ if increasing SDRC clk rate,
105 136 beq return_to_sdram @ return to SDRAM code, otherwise,
106 137 bl configure_sdrc @ reprogram SDRC regs now
107   - mov r12, r5
  138 + mov r12, r2
108 139 bl wait_clk_stable @ wait for SDRC to stabilize
109 140 return_to_sdram:
110 141 isb @ prevent speculative exec past here
... ... @@ -149,7 +180,7 @@
149 180 ldr r12, [r11]
150 181 ldr r10, core_m2_mask_val @ modify m2 for core dpll
151 182 and r12, r12, r10
152   - orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
  183 + orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
153 184 str r12, [r11]
154 185 ldr r12, [r11] @ posted-write barrier for CM
155 186 bx lr
156 187  
... ... @@ -187,15 +218,34 @@
187 218 bne wait_dll_unlock
188 219 bx lr
189 220 configure_sdrc:
190   - ldr r11, omap3_sdrc_rfr_ctrl
191   - str r0, [r11]
192   - ldr r11, omap3_sdrc_actim_ctrla
193   - str r1, [r11]
194   - ldr r11, omap3_sdrc_actim_ctrlb
195   - str r2, [r11]
  221 + ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
  222 + ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
  223 + str r12, [r11] @ store
  224 + ldr r12, omap_sdrc_actim_ctrl_a_0_val
  225 + ldr r11, omap3_sdrc_actim_ctrl_a_0
  226 + str r12, [r11]
  227 + ldr r12, omap_sdrc_actim_ctrl_b_0_val
  228 + ldr r11, omap3_sdrc_actim_ctrl_b_0
  229 + str r12, [r11]
  230 + ldr r12, omap_sdrc_mr_0_val
196 231 ldr r11, omap3_sdrc_mr_0
197   - str r6, [r11]
198   - ldr r6, [r11] @ posted-write barrier for SDRC
  232 + str r12, [r11]
  233 + ldr r12, omap_sdrc_rfr_ctrl_1_val
  234 + cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
  235 + beq skip_cs1_prog @ do not program cs1 params
  236 + ldr r11, omap3_sdrc_rfr_ctrl_1
  237 + str r12, [r11]
  238 + ldr r12, omap_sdrc_actim_ctrl_a_1_val
  239 + ldr r11, omap3_sdrc_actim_ctrl_a_1
  240 + str r12, [r11]
  241 + ldr r12, omap_sdrc_actim_ctrl_b_1_val
  242 + ldr r11, omap3_sdrc_actim_ctrl_b_1
  243 + str r12, [r11]
  244 + ldr r12, omap_sdrc_mr_1_val
  245 + ldr r11, omap3_sdrc_mr_1
  246 + str r12, [r11]
  247 +skip_cs1_prog:
  248 + ldr r12, [r11] @ posted-write barrier for SDRC
199 249 bx lr
200 250  
201 251 omap3_sdrc_power:
202 252  
203 253  
204 254  
205 255  
... ... @@ -206,14 +256,40 @@
206 256 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
207 257 omap3_cm_iclken1_core:
208 258 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
209   -omap3_sdrc_rfr_ctrl:
  259 +
  260 +omap3_sdrc_rfr_ctrl_0:
210 261 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
211   -omap3_sdrc_actim_ctrla:
  262 +omap3_sdrc_rfr_ctrl_1:
  263 + .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
  264 +omap3_sdrc_actim_ctrl_a_0:
212 265 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
213   -omap3_sdrc_actim_ctrlb:
  266 +omap3_sdrc_actim_ctrl_a_1:
  267 + .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
  268 +omap3_sdrc_actim_ctrl_b_0:
214 269 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
  270 +omap3_sdrc_actim_ctrl_b_1:
  271 + .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
215 272 omap3_sdrc_mr_0:
216 273 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
  274 +omap3_sdrc_mr_1:
  275 + .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
  276 +omap_sdrc_rfr_ctrl_0_val:
  277 + .word 0xDEADBEEF
  278 +omap_sdrc_rfr_ctrl_1_val:
  279 + .word 0xDEADBEEF
  280 +omap_sdrc_actim_ctrl_a_0_val:
  281 + .word 0xDEADBEEF
  282 +omap_sdrc_actim_ctrl_a_1_val:
  283 + .word 0xDEADBEEF
  284 +omap_sdrc_actim_ctrl_b_0_val:
  285 + .word 0xDEADBEEF
  286 +omap_sdrc_actim_ctrl_b_1_val:
  287 + .word 0xDEADBEEF
  288 +omap_sdrc_mr_0_val:
  289 + .word 0xDEADBEEF
  290 +omap_sdrc_mr_1_val:
  291 + .word 0xDEADBEEF
  292 +
217 293 omap3_sdrc_dlla_status:
218 294 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
219 295 omap3_sdrc_dlla_ctrl:
arch/arm/plat-omap/include/mach/io.h
Diff comments   View file @ 58cda88
... ... @@ -228,7 +228,8 @@
228 228 extern void omap1_init_common_hw(void);
229 229  
230 230 extern void omap2_map_common_io(void);
231   -extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
  231 +extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
  232 + struct omap_sdrc_params *sdrc_cs1);
232 233  
233 234 #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
234 235 #define __arch_iounmap(v) omap_iounmap(v)
arch/arm/plat-omap/include/mach/sdrc.h
Diff comments   View file @ 58cda88
... ... @@ -30,6 +30,10 @@
30 30 #define SDRC_ACTIM_CTRL_A_0 0x09c
31 31 #define SDRC_ACTIM_CTRL_B_0 0x0a0
32 32 #define SDRC_RFR_CTRL_0 0x0a4
  33 +#define SDRC_MR_1 0x0B4
  34 +#define SDRC_ACTIM_CTRL_A_1 0x0C4
  35 +#define SDRC_ACTIM_CTRL_B_1 0x0C8
  36 +#define SDRC_RFR_CTRL_1 0x0D4
33 37  
34 38 /*
35 39 * These values represent the number of memory clock cycles between
... ... @@ -102,8 +106,11 @@
102 106 u32 mr;
103 107 };
104 108  
105   -void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
106   -struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
  109 +void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  110 + struct omap_sdrc_params *sdrc_cs1);
  111 +int omap2_sdrc_get_params(unsigned long r,
  112 + struct omap_sdrc_params **sdrc_cs0,
  113 + struct omap_sdrc_params **sdrc_cs1);
107 114  
108 115 #ifdef CONFIG_ARCH_OMAP2
109 116  
arch/arm/plat-omap/include/mach/sram.h
Diff comments   View file @ 58cda88
... ... @@ -21,11 +21,12 @@
21 21 u32 mem_type);
22 22 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
23 23  
24   -extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
25   - u32 sdrc_actim_ctrla,
26   - u32 sdrc_actim_ctrlb, u32 m2,
27   - u32 unlock_dll, u32 f, u32 sdrc_mr,
28   - u32 inc);
  24 +extern u32 omap3_configure_core_dpll(
  25 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
  26 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  27 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  28 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  29 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
29 30  
30 31 /* Do not use these */
31 32 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
... ... @@ -59,12 +60,12 @@
59 60 u32 mem_type);
60 61 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
61 62  
62   -
63   -extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
64   - u32 sdrc_actim_ctrla,
65   - u32 sdrc_actim_ctrlb, u32 m2,
66   - u32 unlock_dll, u32 f, u32 sdrc_mr,
67   - u32 inc);
  63 +extern u32 omap3_sram_configure_core_dpll(
  64 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
  65 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  66 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  67 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  68 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
68 69 extern unsigned long omap3_sram_configure_core_dpll_sz;
69 70  
70 71 #endif
arch/arm/plat-omap/sram.c
Diff comments   View file @ 58cda88
... ... @@ -373,20 +373,26 @@
373 373  
374 374 #ifdef CONFIG_ARCH_OMAP3
375 375  
376   -static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
377   - u32 sdrc_actim_ctrla,
378   - u32 sdrc_actim_ctrlb,
379   - u32 m2, u32 unlock_dll,
380   - u32 f, u32 sdrc_mr, u32 inc);
381   -u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
382   - u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
383   - u32 f, u32 sdrc_mr, u32 inc)
  376 +static u32 (*_omap3_sram_configure_core_dpll)(
  377 + u32 m2, u32 unlock_dll, u32 f, u32 inc,
  378 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  379 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  380 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  381 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
  382 +
  383 +u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
  384 + u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  385 + u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  386 + u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  387 + u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
384 388 {
385 389 BUG_ON(!_omap3_sram_configure_core_dpll);
386   - return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
387   - sdrc_actim_ctrla,
388   - sdrc_actim_ctrlb, m2,
389   - unlock_dll, f, sdrc_mr, inc);
  390 + return _omap3_sram_configure_core_dpll(
  391 + m2, unlock_dll, f, inc,
  392 + sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
  393 + sdrc_actim_ctrl_b_0, sdrc_mr_0,
  394 + sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
  395 + sdrc_actim_ctrl_b_1, sdrc_mr_1);
390 396 }
391 397  
392 398 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */