Commit 6322cdd0eb22e016aeced886c2046d115139c962
Committed by
Chris Ball
Chris Ball
1 parent
a8e6df7343
Exists in
master
and in
4 other branches
mmc: sdhci: add hooks for setting UHS in platform specific code
Allow platform specific code to set UHS registers if implementation requires speciial platform specific handling Signed-off-by: Philip Rakity <prakity@marvell.com> Reviewed-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Showing 2 changed files with 20 additions and 15 deletions Side-by-side Diff
drivers/mmc/host/sdhci.c
| ... | ... | @@ -1346,27 +1346,30 @@ |
| 1346 | 1346 | sdhci_set_clock(host, clock); |
| 1347 | 1347 | } |
| 1348 | 1348 | |
| 1349 | - ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
| 1350 | 1349 | |
| 1351 | - /* Select Bus Speed Mode for host */ | |
| 1352 | - ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
| 1353 | - if (ios->timing == MMC_TIMING_UHS_SDR12) | |
| 1354 | - ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
| 1355 | - else if (ios->timing == MMC_TIMING_UHS_SDR25) | |
| 1356 | - ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
| 1357 | - else if (ios->timing == MMC_TIMING_UHS_SDR50) | |
| 1358 | - ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
| 1359 | - else if (ios->timing == MMC_TIMING_UHS_SDR104) | |
| 1360 | - ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
| 1361 | - else if (ios->timing == MMC_TIMING_UHS_DDR50) | |
| 1362 | - ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
| 1363 | - | |
| 1364 | 1350 | /* Reset SD Clock Enable */ |
| 1365 | 1351 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1366 | 1352 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1367 | 1353 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1368 | 1354 | |
| 1369 | - sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
| 1355 | + if (host->ops->set_uhs_signaling) | |
| 1356 | + host->ops->set_uhs_signaling(host, ios->timing); | |
| 1357 | + else { | |
| 1358 | + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
| 1359 | + /* Select Bus Speed Mode for host */ | |
| 1360 | + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
| 1361 | + if (ios->timing == MMC_TIMING_UHS_SDR12) | |
| 1362 | + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
| 1363 | + else if (ios->timing == MMC_TIMING_UHS_SDR25) | |
| 1364 | + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
| 1365 | + else if (ios->timing == MMC_TIMING_UHS_SDR50) | |
| 1366 | + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
| 1367 | + else if (ios->timing == MMC_TIMING_UHS_SDR104) | |
| 1368 | + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
| 1369 | + else if (ios->timing == MMC_TIMING_UHS_DDR50) | |
| 1370 | + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
| 1371 | + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
| 1372 | + } | |
| 1370 | 1373 | |
| 1371 | 1374 | /* Re-enable SD Clock */ |
| 1372 | 1375 | clock = host->clock; |
drivers/mmc/host/sdhci.h
| ... | ... | @@ -270,6 +270,8 @@ |
| 270 | 270 | unsigned int (*get_ro)(struct sdhci_host *host); |
| 271 | 271 | void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); |
| 272 | 272 | void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); |
| 273 | + int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); | |
| 274 | + | |
| 273 | 275 | }; |
| 274 | 276 | |
| 275 | 277 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |