Commit 67ce04bf2746f8a1f8c2a104b313d20c63f68378
Committed by
David Woodhouse
1 parent
4938c88c92
Exists in
master
and in
4 other branches
mtd: nand: add OMAP2/OMAP3 NAND driver
This driver is present in the OMAP tree, now pushing it to MTD. Original author(s): Jian Zhang <jzhang@ti.com> Signed-off-by: Vimal Singh <vimalsingh@ti.com> Cc: Jian Zhang <jzhang@ti.com> Cc: Artem Bityutskiy <dedekind@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Showing 3 changed files with 783 additions and 0 deletions Side-by-side Diff
drivers/mtd/nand/Kconfig
... | ... | @@ -74,6 +74,12 @@ |
74 | 74 | help |
75 | 75 | Support for NAND flash on Amstrad E3 (Delta). |
76 | 76 | |
77 | +config MTD_NAND_OMAP2 | |
78 | + tristate "NAND Flash device on OMAP2 and OMAP3" | |
79 | + depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3) | |
80 | + help | |
81 | + Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms. | |
82 | + | |
77 | 83 | config MTD_NAND_TS7250 |
78 | 84 | tristate "NAND Flash device on TS-7250 board" |
79 | 85 | depends on MACH_TS72XX |
drivers/mtd/nand/Makefile
... | ... | @@ -25,6 +25,7 @@ |
25 | 25 | obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o |
26 | 26 | obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o |
27 | 27 | obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o |
28 | +obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o | |
28 | 29 | obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o |
29 | 30 | obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o |
30 | 31 | obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o |
drivers/mtd/nand/omap2.c
1 | +/* | |
2 | + * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com> | |
3 | + * Copyright © 2004 Micron Technology Inc. | |
4 | + * Copyright © 2004 David Brownell | |
5 | + * | |
6 | + * This program is free software; you can redistribute it and/or modify | |
7 | + * it under the terms of the GNU General Public License version 2 as | |
8 | + * published by the Free Software Foundation. | |
9 | + */ | |
10 | + | |
11 | +#include <linux/platform_device.h> | |
12 | +#include <linux/dma-mapping.h> | |
13 | +#include <linux/delay.h> | |
14 | +#include <linux/mtd/mtd.h> | |
15 | +#include <linux/mtd/nand.h> | |
16 | +#include <linux/mtd/partitions.h> | |
17 | +#include <linux/io.h> | |
18 | + | |
19 | +#include <asm/dma.h> | |
20 | + | |
21 | +#include <mach/gpmc.h> | |
22 | +#include <mach/nand.h> | |
23 | + | |
24 | +#define GPMC_IRQ_STATUS 0x18 | |
25 | +#define GPMC_ECC_CONFIG 0x1F4 | |
26 | +#define GPMC_ECC_CONTROL 0x1F8 | |
27 | +#define GPMC_ECC_SIZE_CONFIG 0x1FC | |
28 | +#define GPMC_ECC1_RESULT 0x200 | |
29 | + | |
30 | +#define DRIVER_NAME "omap2-nand" | |
31 | + | |
32 | +/* size (4 KiB) for IO mapping */ | |
33 | +#define NAND_IO_SIZE SZ_4K | |
34 | + | |
35 | +#define NAND_WP_OFF 0 | |
36 | +#define NAND_WP_BIT 0x00000010 | |
37 | +#define WR_RD_PIN_MONITORING 0x00600000 | |
38 | + | |
39 | +#define GPMC_BUF_FULL 0x00000001 | |
40 | +#define GPMC_BUF_EMPTY 0x00000000 | |
41 | + | |
42 | +#define NAND_Ecc_P1e (1 << 0) | |
43 | +#define NAND_Ecc_P2e (1 << 1) | |
44 | +#define NAND_Ecc_P4e (1 << 2) | |
45 | +#define NAND_Ecc_P8e (1 << 3) | |
46 | +#define NAND_Ecc_P16e (1 << 4) | |
47 | +#define NAND_Ecc_P32e (1 << 5) | |
48 | +#define NAND_Ecc_P64e (1 << 6) | |
49 | +#define NAND_Ecc_P128e (1 << 7) | |
50 | +#define NAND_Ecc_P256e (1 << 8) | |
51 | +#define NAND_Ecc_P512e (1 << 9) | |
52 | +#define NAND_Ecc_P1024e (1 << 10) | |
53 | +#define NAND_Ecc_P2048e (1 << 11) | |
54 | + | |
55 | +#define NAND_Ecc_P1o (1 << 16) | |
56 | +#define NAND_Ecc_P2o (1 << 17) | |
57 | +#define NAND_Ecc_P4o (1 << 18) | |
58 | +#define NAND_Ecc_P8o (1 << 19) | |
59 | +#define NAND_Ecc_P16o (1 << 20) | |
60 | +#define NAND_Ecc_P32o (1 << 21) | |
61 | +#define NAND_Ecc_P64o (1 << 22) | |
62 | +#define NAND_Ecc_P128o (1 << 23) | |
63 | +#define NAND_Ecc_P256o (1 << 24) | |
64 | +#define NAND_Ecc_P512o (1 << 25) | |
65 | +#define NAND_Ecc_P1024o (1 << 26) | |
66 | +#define NAND_Ecc_P2048o (1 << 27) | |
67 | + | |
68 | +#define TF(value) (value ? 1 : 0) | |
69 | + | |
70 | +#define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0) | |
71 | +#define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1) | |
72 | +#define P1e(a) (TF(a & NAND_Ecc_P1e) << 2) | |
73 | +#define P1o(a) (TF(a & NAND_Ecc_P1o) << 3) | |
74 | +#define P2e(a) (TF(a & NAND_Ecc_P2e) << 4) | |
75 | +#define P2o(a) (TF(a & NAND_Ecc_P2o) << 5) | |
76 | +#define P4e(a) (TF(a & NAND_Ecc_P4e) << 6) | |
77 | +#define P4o(a) (TF(a & NAND_Ecc_P4o) << 7) | |
78 | + | |
79 | +#define P8e(a) (TF(a & NAND_Ecc_P8e) << 0) | |
80 | +#define P8o(a) (TF(a & NAND_Ecc_P8o) << 1) | |
81 | +#define P16e(a) (TF(a & NAND_Ecc_P16e) << 2) | |
82 | +#define P16o(a) (TF(a & NAND_Ecc_P16o) << 3) | |
83 | +#define P32e(a) (TF(a & NAND_Ecc_P32e) << 4) | |
84 | +#define P32o(a) (TF(a & NAND_Ecc_P32o) << 5) | |
85 | +#define P64e(a) (TF(a & NAND_Ecc_P64e) << 6) | |
86 | +#define P64o(a) (TF(a & NAND_Ecc_P64o) << 7) | |
87 | + | |
88 | +#define P128e(a) (TF(a & NAND_Ecc_P128e) << 0) | |
89 | +#define P128o(a) (TF(a & NAND_Ecc_P128o) << 1) | |
90 | +#define P256e(a) (TF(a & NAND_Ecc_P256e) << 2) | |
91 | +#define P256o(a) (TF(a & NAND_Ecc_P256o) << 3) | |
92 | +#define P512e(a) (TF(a & NAND_Ecc_P512e) << 4) | |
93 | +#define P512o(a) (TF(a & NAND_Ecc_P512o) << 5) | |
94 | +#define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6) | |
95 | +#define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7) | |
96 | + | |
97 | +#define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0) | |
98 | +#define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1) | |
99 | +#define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2) | |
100 | +#define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3) | |
101 | +#define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4) | |
102 | +#define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5) | |
103 | +#define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6) | |
104 | +#define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7) | |
105 | + | |
106 | +#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) | |
107 | +#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) | |
108 | + | |
109 | +#ifdef CONFIG_MTD_PARTITIONS | |
110 | +static const char *part_probes[] = { "cmdlinepart", NULL }; | |
111 | +#endif | |
112 | + | |
113 | +struct omap_nand_info { | |
114 | + struct nand_hw_control controller; | |
115 | + struct omap_nand_platform_data *pdata; | |
116 | + struct mtd_info mtd; | |
117 | + struct mtd_partition *parts; | |
118 | + struct nand_chip nand; | |
119 | + struct platform_device *pdev; | |
120 | + | |
121 | + int gpmc_cs; | |
122 | + unsigned long phys_base; | |
123 | + void __iomem *gpmc_cs_baseaddr; | |
124 | + void __iomem *gpmc_baseaddr; | |
125 | +}; | |
126 | + | |
127 | +/** | |
128 | + * omap_nand_wp - This function enable or disable the Write Protect feature | |
129 | + * @mtd: MTD device structure | |
130 | + * @mode: WP ON/OFF | |
131 | + */ | |
132 | +static void omap_nand_wp(struct mtd_info *mtd, int mode) | |
133 | +{ | |
134 | + struct omap_nand_info *info = container_of(mtd, | |
135 | + struct omap_nand_info, mtd); | |
136 | + | |
137 | + unsigned long config = __raw_readl(info->gpmc_baseaddr + GPMC_CONFIG); | |
138 | + | |
139 | + if (mode) | |
140 | + config &= ~(NAND_WP_BIT); /* WP is ON */ | |
141 | + else | |
142 | + config |= (NAND_WP_BIT); /* WP is OFF */ | |
143 | + | |
144 | + __raw_writel(config, (info->gpmc_baseaddr + GPMC_CONFIG)); | |
145 | +} | |
146 | + | |
147 | +/** | |
148 | + * omap_hwcontrol - hardware specific access to control-lines | |
149 | + * @mtd: MTD device structure | |
150 | + * @cmd: command to device | |
151 | + * @ctrl: | |
152 | + * NAND_NCE: bit 0 -> don't care | |
153 | + * NAND_CLE: bit 1 -> Command Latch | |
154 | + * NAND_ALE: bit 2 -> Address Latch | |
155 | + * | |
156 | + * NOTE: boards may use different bits for these!! | |
157 | + */ | |
158 | +static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) | |
159 | +{ | |
160 | + struct omap_nand_info *info = container_of(mtd, | |
161 | + struct omap_nand_info, mtd); | |
162 | + switch (ctrl) { | |
163 | + case NAND_CTRL_CHANGE | NAND_CTRL_CLE: | |
164 | + info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | |
165 | + GPMC_CS_NAND_COMMAND; | |
166 | + info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | |
167 | + GPMC_CS_NAND_DATA; | |
168 | + break; | |
169 | + | |
170 | + case NAND_CTRL_CHANGE | NAND_CTRL_ALE: | |
171 | + info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | |
172 | + GPMC_CS_NAND_ADDRESS; | |
173 | + info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | |
174 | + GPMC_CS_NAND_DATA; | |
175 | + break; | |
176 | + | |
177 | + case NAND_CTRL_CHANGE | NAND_NCE: | |
178 | + info->nand.IO_ADDR_W = info->gpmc_cs_baseaddr + | |
179 | + GPMC_CS_NAND_DATA; | |
180 | + info->nand.IO_ADDR_R = info->gpmc_cs_baseaddr + | |
181 | + GPMC_CS_NAND_DATA; | |
182 | + break; | |
183 | + } | |
184 | + | |
185 | + if (cmd != NAND_CMD_NONE) | |
186 | + __raw_writeb(cmd, info->nand.IO_ADDR_W); | |
187 | +} | |
188 | + | |
189 | +/** | |
190 | + * omap_read_buf16 - read data from NAND controller into buffer | |
191 | + * @mtd: MTD device structure | |
192 | + * @buf: buffer to store date | |
193 | + * @len: number of bytes to read | |
194 | + */ | |
195 | +static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len) | |
196 | +{ | |
197 | + struct nand_chip *nand = mtd->priv; | |
198 | + | |
199 | + __raw_readsw(nand->IO_ADDR_R, buf, len / 2); | |
200 | +} | |
201 | + | |
202 | +/** | |
203 | + * omap_write_buf16 - write buffer to NAND controller | |
204 | + * @mtd: MTD device structure | |
205 | + * @buf: data buffer | |
206 | + * @len: number of bytes to write | |
207 | + */ | |
208 | +static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len) | |
209 | +{ | |
210 | + struct omap_nand_info *info = container_of(mtd, | |
211 | + struct omap_nand_info, mtd); | |
212 | + u16 *p = (u16 *) buf; | |
213 | + | |
214 | + /* FIXME try bursts of writesw() or DMA ... */ | |
215 | + len >>= 1; | |
216 | + | |
217 | + while (len--) { | |
218 | + writew(*p++, info->nand.IO_ADDR_W); | |
219 | + | |
220 | + while (GPMC_BUF_EMPTY == (readl(info->gpmc_baseaddr + | |
221 | + GPMC_STATUS) & GPMC_BUF_FULL)) | |
222 | + ; | |
223 | + } | |
224 | +} | |
225 | +/** | |
226 | + * omap_verify_buf - Verify chip data against buffer | |
227 | + * @mtd: MTD device structure | |
228 | + * @buf: buffer containing the data to compare | |
229 | + * @len: number of bytes to compare | |
230 | + */ | |
231 | +static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len) | |
232 | +{ | |
233 | + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
234 | + mtd); | |
235 | + u16 *p = (u16 *) buf; | |
236 | + | |
237 | + len >>= 1; | |
238 | + while (len--) { | |
239 | + if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R))) | |
240 | + return -EFAULT; | |
241 | + } | |
242 | + | |
243 | + return 0; | |
244 | +} | |
245 | + | |
246 | +#ifdef CONFIG_MTD_NAND_OMAP_HWECC | |
247 | +/** | |
248 | + * omap_hwecc_init - Initialize the HW ECC for NAND flash in GPMC controller | |
249 | + * @mtd: MTD device structure | |
250 | + */ | |
251 | +static void omap_hwecc_init(struct mtd_info *mtd) | |
252 | +{ | |
253 | + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
254 | + mtd); | |
255 | + struct nand_chip *chip = mtd->priv; | |
256 | + unsigned long val = 0x0; | |
257 | + | |
258 | + /* Read from ECC Control Register */ | |
259 | + val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
260 | + /* Clear all ECC | Enable Reg1 */ | |
261 | + val = ((0x00000001<<8) | 0x00000001); | |
262 | + __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
263 | + | |
264 | + /* Read from ECC Size Config Register */ | |
265 | + val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); | |
266 | + /* ECCSIZE1=512 | Select eccResultsize[0-3] */ | |
267 | + val = ((((chip->ecc.size >> 1) - 1) << 22) | (0x0000000F)); | |
268 | + __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_SIZE_CONFIG); | |
269 | +} | |
270 | + | |
271 | +/** | |
272 | + * gen_true_ecc - This function will generate true ECC value | |
273 | + * @ecc_buf: buffer to store ecc code | |
274 | + * | |
275 | + * This generated true ECC value can be used when correcting | |
276 | + * data read from NAND flash memory core | |
277 | + */ | |
278 | +static void gen_true_ecc(u8 *ecc_buf) | |
279 | +{ | |
280 | + u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) | | |
281 | + ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8); | |
282 | + | |
283 | + ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | | |
284 | + P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp)); | |
285 | + ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | | |
286 | + P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp)); | |
287 | + ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | | |
288 | + P1e(tmp) | P2048o(tmp) | P2048e(tmp)); | |
289 | +} | |
290 | + | |
291 | +/** | |
292 | + * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data | |
293 | + * @ecc_data1: ecc code from nand spare area | |
294 | + * @ecc_data2: ecc code from hardware register obtained from hardware ecc | |
295 | + * @page_data: page data | |
296 | + * | |
297 | + * This function compares two ECC's and indicates if there is an error. | |
298 | + * If the error can be corrected it will be corrected to the buffer. | |
299 | + */ | |
300 | +static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */ | |
301 | + u8 *ecc_data2, /* read from register */ | |
302 | + u8 *page_data) | |
303 | +{ | |
304 | + uint i; | |
305 | + u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8]; | |
306 | + u8 comp0_bit[8], comp1_bit[8], comp2_bit[8]; | |
307 | + u8 ecc_bit[24]; | |
308 | + u8 ecc_sum = 0; | |
309 | + u8 find_bit = 0; | |
310 | + uint find_byte = 0; | |
311 | + int isEccFF; | |
312 | + | |
313 | + isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF); | |
314 | + | |
315 | + gen_true_ecc(ecc_data1); | |
316 | + gen_true_ecc(ecc_data2); | |
317 | + | |
318 | + for (i = 0; i <= 2; i++) { | |
319 | + *(ecc_data1 + i) = ~(*(ecc_data1 + i)); | |
320 | + *(ecc_data2 + i) = ~(*(ecc_data2 + i)); | |
321 | + } | |
322 | + | |
323 | + for (i = 0; i < 8; i++) { | |
324 | + tmp0_bit[i] = *ecc_data1 % 2; | |
325 | + *ecc_data1 = *ecc_data1 / 2; | |
326 | + } | |
327 | + | |
328 | + for (i = 0; i < 8; i++) { | |
329 | + tmp1_bit[i] = *(ecc_data1 + 1) % 2; | |
330 | + *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2; | |
331 | + } | |
332 | + | |
333 | + for (i = 0; i < 8; i++) { | |
334 | + tmp2_bit[i] = *(ecc_data1 + 2) % 2; | |
335 | + *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2; | |
336 | + } | |
337 | + | |
338 | + for (i = 0; i < 8; i++) { | |
339 | + comp0_bit[i] = *ecc_data2 % 2; | |
340 | + *ecc_data2 = *ecc_data2 / 2; | |
341 | + } | |
342 | + | |
343 | + for (i = 0; i < 8; i++) { | |
344 | + comp1_bit[i] = *(ecc_data2 + 1) % 2; | |
345 | + *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2; | |
346 | + } | |
347 | + | |
348 | + for (i = 0; i < 8; i++) { | |
349 | + comp2_bit[i] = *(ecc_data2 + 2) % 2; | |
350 | + *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2; | |
351 | + } | |
352 | + | |
353 | + for (i = 0; i < 6; i++) | |
354 | + ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2]; | |
355 | + | |
356 | + for (i = 0; i < 8; i++) | |
357 | + ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i]; | |
358 | + | |
359 | + for (i = 0; i < 8; i++) | |
360 | + ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i]; | |
361 | + | |
362 | + ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0]; | |
363 | + ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1]; | |
364 | + | |
365 | + for (i = 0; i < 24; i++) | |
366 | + ecc_sum += ecc_bit[i]; | |
367 | + | |
368 | + switch (ecc_sum) { | |
369 | + case 0: | |
370 | + /* Not reached because this function is not called if | |
371 | + * ECC values are equal | |
372 | + */ | |
373 | + return 0; | |
374 | + | |
375 | + case 1: | |
376 | + /* Uncorrectable error */ | |
377 | + DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n"); | |
378 | + return -1; | |
379 | + | |
380 | + case 11: | |
381 | + /* UN-Correctable error */ | |
382 | + DEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR B\n"); | |
383 | + return -1; | |
384 | + | |
385 | + case 12: | |
386 | + /* Correctable error */ | |
387 | + find_byte = (ecc_bit[23] << 8) + | |
388 | + (ecc_bit[21] << 7) + | |
389 | + (ecc_bit[19] << 6) + | |
390 | + (ecc_bit[17] << 5) + | |
391 | + (ecc_bit[15] << 4) + | |
392 | + (ecc_bit[13] << 3) + | |
393 | + (ecc_bit[11] << 2) + | |
394 | + (ecc_bit[9] << 1) + | |
395 | + ecc_bit[7]; | |
396 | + | |
397 | + find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1]; | |
398 | + | |
399 | + DEBUG(MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at " | |
400 | + "offset: %d, bit: %d\n", find_byte, find_bit); | |
401 | + | |
402 | + page_data[find_byte] ^= (1 << find_bit); | |
403 | + | |
404 | + return 0; | |
405 | + default: | |
406 | + if (isEccFF) { | |
407 | + if (ecc_data2[0] == 0 && | |
408 | + ecc_data2[1] == 0 && | |
409 | + ecc_data2[2] == 0) | |
410 | + return 0; | |
411 | + } | |
412 | + DEBUG(MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n"); | |
413 | + return -1; | |
414 | + } | |
415 | +} | |
416 | + | |
417 | +/** | |
418 | + * omap_correct_data - Compares the ECC read with HW generated ECC | |
419 | + * @mtd: MTD device structure | |
420 | + * @dat: page data | |
421 | + * @read_ecc: ecc read from nand flash | |
422 | + * @calc_ecc: ecc read from HW ECC registers | |
423 | + * | |
424 | + * Compares the ecc read from nand spare area with ECC registers values | |
425 | + * and if ECC's mismached, it will call 'omap_compare_ecc' for error detection | |
426 | + * and correction. | |
427 | + */ | |
428 | +static int omap_correct_data(struct mtd_info *mtd, u_char *dat, | |
429 | + u_char *read_ecc, u_char *calc_ecc) | |
430 | +{ | |
431 | + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
432 | + mtd); | |
433 | + int blockCnt = 0, i = 0, ret = 0; | |
434 | + | |
435 | + /* Ex NAND_ECC_HW12_2048 */ | |
436 | + if ((info->nand.ecc.mode == NAND_ECC_HW) && | |
437 | + (info->nand.ecc.size == 2048)) | |
438 | + blockCnt = 4; | |
439 | + else | |
440 | + blockCnt = 1; | |
441 | + | |
442 | + for (i = 0; i < blockCnt; i++) { | |
443 | + if (memcmp(read_ecc, calc_ecc, 3) != 0) { | |
444 | + ret = omap_compare_ecc(read_ecc, calc_ecc, dat); | |
445 | + if (ret < 0) | |
446 | + return ret; | |
447 | + } | |
448 | + read_ecc += 3; | |
449 | + calc_ecc += 3; | |
450 | + dat += 512; | |
451 | + } | |
452 | + return 0; | |
453 | +} | |
454 | + | |
455 | +/** | |
456 | + * omap_calcuate_ecc - Generate non-inverted ECC bytes. | |
457 | + * @mtd: MTD device structure | |
458 | + * @dat: The pointer to data on which ecc is computed | |
459 | + * @ecc_code: The ecc_code buffer | |
460 | + * | |
461 | + * Using noninverted ECC can be considered ugly since writing a blank | |
462 | + * page ie. padding will clear the ECC bytes. This is no problem as long | |
463 | + * nobody is trying to write data on the seemingly unused page. Reading | |
464 | + * an erased page will produce an ECC mismatch between generated and read | |
465 | + * ECC bytes that has to be dealt with separately. | |
466 | + */ | |
467 | +static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat, | |
468 | + u_char *ecc_code) | |
469 | +{ | |
470 | + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
471 | + mtd); | |
472 | + unsigned long val = 0x0; | |
473 | + unsigned long reg; | |
474 | + | |
475 | + /* Start Reading from HW ECC1_Result = 0x200 */ | |
476 | + reg = (unsigned long)(info->gpmc_baseaddr + GPMC_ECC1_RESULT); | |
477 | + val = __raw_readl(reg); | |
478 | + *ecc_code++ = val; /* P128e, ..., P1e */ | |
479 | + *ecc_code++ = val >> 16; /* P128o, ..., P1o */ | |
480 | + /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */ | |
481 | + *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0); | |
482 | + reg += 4; | |
483 | + | |
484 | + return 0; | |
485 | +} | |
486 | + | |
487 | +/** | |
488 | + * omap_enable_hwecc - This function enables the hardware ecc functionality | |
489 | + * @mtd: MTD device structure | |
490 | + * @mode: Read/Write mode | |
491 | + */ | |
492 | +static void omap_enable_hwecc(struct mtd_info *mtd, int mode) | |
493 | +{ | |
494 | + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
495 | + mtd); | |
496 | + struct nand_chip *chip = mtd->priv; | |
497 | + unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
498 | + unsigned long val = __raw_readl(info->gpmc_baseaddr + GPMC_ECC_CONFIG); | |
499 | + | |
500 | + switch (mode) { | |
501 | + case NAND_ECC_READ: | |
502 | + __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
503 | + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
504 | + val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
505 | + break; | |
506 | + case NAND_ECC_READSYN: | |
507 | + __raw_writel(0x100, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
508 | + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
509 | + val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
510 | + break; | |
511 | + case NAND_ECC_WRITE: | |
512 | + __raw_writel(0x101, info->gpmc_baseaddr + GPMC_ECC_CONTROL); | |
513 | + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
514 | + val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1); | |
515 | + break; | |
516 | + default: | |
517 | + DEBUG(MTD_DEBUG_LEVEL0, "Error: Unrecognized Mode[%d]!\n", | |
518 | + mode); | |
519 | + break; | |
520 | + } | |
521 | + | |
522 | + __raw_writel(val, info->gpmc_baseaddr + GPMC_ECC_CONFIG); | |
523 | +} | |
524 | +#endif | |
525 | + | |
526 | +/** | |
527 | + * omap_wait - wait until the command is done | |
528 | + * @mtd: MTD device structure | |
529 | + * @chip: NAND Chip structure | |
530 | + * | |
531 | + * Wait function is called during Program and erase operations and | |
532 | + * the way it is called from MTD layer, we should wait till the NAND | |
533 | + * chip is ready after the programming/erase operation has completed. | |
534 | + * | |
535 | + * Erase can take up to 400ms and program up to 20ms according to | |
536 | + * general NAND and SmartMedia specs | |
537 | + */ | |
538 | +static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip) | |
539 | +{ | |
540 | + struct nand_chip *this = mtd->priv; | |
541 | + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
542 | + mtd); | |
543 | + unsigned long timeo = jiffies; | |
544 | + int status, state = this->state; | |
545 | + | |
546 | + if (state == FL_ERASING) | |
547 | + timeo += (HZ * 400) / 1000; | |
548 | + else | |
549 | + timeo += (HZ * 20) / 1000; | |
550 | + | |
551 | + this->IO_ADDR_W = (void *) info->gpmc_cs_baseaddr + | |
552 | + GPMC_CS_NAND_COMMAND; | |
553 | + this->IO_ADDR_R = (void *) info->gpmc_cs_baseaddr + GPMC_CS_NAND_DATA; | |
554 | + | |
555 | + __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W); | |
556 | + | |
557 | + while (time_before(jiffies, timeo)) { | |
558 | + status = __raw_readb(this->IO_ADDR_R); | |
559 | + if (!(status & 0x40)) | |
560 | + break; | |
561 | + } | |
562 | + return status; | |
563 | +} | |
564 | + | |
565 | +/** | |
566 | + * omap_dev_ready - calls the platform specific dev_ready function | |
567 | + * @mtd: MTD device structure | |
568 | + */ | |
569 | +static int omap_dev_ready(struct mtd_info *mtd) | |
570 | +{ | |
571 | + struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, | |
572 | + mtd); | |
573 | + unsigned int val = __raw_readl(info->gpmc_baseaddr + GPMC_IRQ_STATUS); | |
574 | + | |
575 | + if ((val & 0x100) == 0x100) { | |
576 | + /* Clear IRQ Interrupt */ | |
577 | + val |= 0x100; | |
578 | + val &= ~(0x0); | |
579 | + __raw_writel(val, info->gpmc_baseaddr + GPMC_IRQ_STATUS); | |
580 | + } else { | |
581 | + unsigned int cnt = 0; | |
582 | + while (cnt++ < 0x1FF) { | |
583 | + if ((val & 0x100) == 0x100) | |
584 | + return 0; | |
585 | + val = __raw_readl(info->gpmc_baseaddr + | |
586 | + GPMC_IRQ_STATUS); | |
587 | + } | |
588 | + } | |
589 | + | |
590 | + return 1; | |
591 | +} | |
592 | + | |
593 | +static int __devinit omap_nand_probe(struct platform_device *pdev) | |
594 | +{ | |
595 | + struct omap_nand_info *info; | |
596 | + struct omap_nand_platform_data *pdata; | |
597 | + int err; | |
598 | + unsigned long val; | |
599 | + | |
600 | + | |
601 | + pdata = pdev->dev.platform_data; | |
602 | + if (pdata == NULL) { | |
603 | + dev_err(&pdev->dev, "platform data missing\n"); | |
604 | + return -ENODEV; | |
605 | + } | |
606 | + | |
607 | + info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL); | |
608 | + if (!info) | |
609 | + return -ENOMEM; | |
610 | + | |
611 | + platform_set_drvdata(pdev, info); | |
612 | + | |
613 | + spin_lock_init(&info->controller.lock); | |
614 | + init_waitqueue_head(&info->controller.wq); | |
615 | + | |
616 | + info->pdev = pdev; | |
617 | + | |
618 | + info->gpmc_cs = pdata->cs; | |
619 | + info->gpmc_baseaddr = pdata->gpmc_baseaddr; | |
620 | + info->gpmc_cs_baseaddr = pdata->gpmc_cs_baseaddr; | |
621 | + | |
622 | + info->mtd.priv = &info->nand; | |
623 | + info->mtd.name = dev_name(&pdev->dev); | |
624 | + info->mtd.owner = THIS_MODULE; | |
625 | + | |
626 | + err = gpmc_cs_request(info->gpmc_cs, NAND_IO_SIZE, &info->phys_base); | |
627 | + if (err < 0) { | |
628 | + dev_err(&pdev->dev, "Cannot request GPMC CS\n"); | |
629 | + goto out_free_info; | |
630 | + } | |
631 | + | |
632 | + /* Enable RD PIN Monitoring Reg */ | |
633 | + if (pdata->dev_ready) { | |
634 | + val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1); | |
635 | + val |= WR_RD_PIN_MONITORING; | |
636 | + gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG1, val); | |
637 | + } | |
638 | + | |
639 | + val = gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG7); | |
640 | + val &= ~(0xf << 8); | |
641 | + val |= (0xc & 0xf) << 8; | |
642 | + gpmc_cs_write_reg(info->gpmc_cs, GPMC_CS_CONFIG7, val); | |
643 | + | |
644 | + /* NAND write protect off */ | |
645 | + omap_nand_wp(&info->mtd, NAND_WP_OFF); | |
646 | + | |
647 | + if (!request_mem_region(info->phys_base, NAND_IO_SIZE, | |
648 | + pdev->dev.driver->name)) { | |
649 | + err = -EBUSY; | |
650 | + goto out_free_cs; | |
651 | + } | |
652 | + | |
653 | + info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); | |
654 | + if (!info->nand.IO_ADDR_R) { | |
655 | + err = -ENOMEM; | |
656 | + goto out_release_mem_region; | |
657 | + } | |
658 | + info->nand.controller = &info->controller; | |
659 | + | |
660 | + info->nand.IO_ADDR_W = info->nand.IO_ADDR_R; | |
661 | + info->nand.cmd_ctrl = omap_hwcontrol; | |
662 | + | |
663 | + /* REVISIT: only supports 16-bit NAND flash */ | |
664 | + | |
665 | + info->nand.read_buf = omap_read_buf16; | |
666 | + info->nand.write_buf = omap_write_buf16; | |
667 | + info->nand.verify_buf = omap_verify_buf; | |
668 | + | |
669 | + /* | |
670 | + * If RDY/BSY line is connected to OMAP then use the omap ready | |
671 | + * funcrtion and the generic nand_wait function which reads the status | |
672 | + * register after monitoring the RDY/BSY line.Otherwise use a standard | |
673 | + * chip delay which is slightly more than tR (AC Timing) of the NAND | |
674 | + * device and read status register until you get a failure or success | |
675 | + */ | |
676 | + if (pdata->dev_ready) { | |
677 | + info->nand.dev_ready = omap_dev_ready; | |
678 | + info->nand.chip_delay = 0; | |
679 | + } else { | |
680 | + info->nand.waitfunc = omap_wait; | |
681 | + info->nand.chip_delay = 50; | |
682 | + } | |
683 | + | |
684 | + info->nand.options |= NAND_SKIP_BBTSCAN; | |
685 | + if ((gpmc_cs_read_reg(info->gpmc_cs, GPMC_CS_CONFIG1) & 0x3000) | |
686 | + == 0x1000) | |
687 | + info->nand.options |= NAND_BUSWIDTH_16; | |
688 | + | |
689 | +#ifdef CONFIG_MTD_NAND_OMAP_HWECC | |
690 | + info->nand.ecc.bytes = 3; | |
691 | + info->nand.ecc.size = 512; | |
692 | + info->nand.ecc.calculate = omap_calculate_ecc; | |
693 | + info->nand.ecc.hwctl = omap_enable_hwecc; | |
694 | + info->nand.ecc.correct = omap_correct_data; | |
695 | + info->nand.ecc.mode = NAND_ECC_HW; | |
696 | + | |
697 | + /* init HW ECC */ | |
698 | + omap_hwecc_init(&info->mtd); | |
699 | +#else | |
700 | + info->nand.ecc.mode = NAND_ECC_SOFT; | |
701 | +#endif | |
702 | + | |
703 | + /* DIP switches on some boards change between 8 and 16 bit | |
704 | + * bus widths for flash. Try the other width if the first try fails. | |
705 | + */ | |
706 | + if (nand_scan(&info->mtd, 1)) { | |
707 | + info->nand.options ^= NAND_BUSWIDTH_16; | |
708 | + if (nand_scan(&info->mtd, 1)) { | |
709 | + err = -ENXIO; | |
710 | + goto out_release_mem_region; | |
711 | + } | |
712 | + } | |
713 | + | |
714 | +#ifdef CONFIG_MTD_PARTITIONS | |
715 | + err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); | |
716 | + if (err > 0) | |
717 | + add_mtd_partitions(&info->mtd, info->parts, err); | |
718 | + else if (pdata->parts) | |
719 | + add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts); | |
720 | + else | |
721 | +#endif | |
722 | + add_mtd_device(&info->mtd); | |
723 | + | |
724 | + platform_set_drvdata(pdev, &info->mtd); | |
725 | + | |
726 | + return 0; | |
727 | + | |
728 | +out_release_mem_region: | |
729 | + release_mem_region(info->phys_base, NAND_IO_SIZE); | |
730 | +out_free_cs: | |
731 | + gpmc_cs_free(info->gpmc_cs); | |
732 | +out_free_info: | |
733 | + kfree(info); | |
734 | + | |
735 | + return err; | |
736 | +} | |
737 | + | |
738 | +static int omap_nand_remove(struct platform_device *pdev) | |
739 | +{ | |
740 | + struct mtd_info *mtd = platform_get_drvdata(pdev); | |
741 | + struct omap_nand_info *info = mtd->priv; | |
742 | + | |
743 | + platform_set_drvdata(pdev, NULL); | |
744 | + /* Release NAND device, its internal structures and partitions */ | |
745 | + nand_release(&info->mtd); | |
746 | + iounmap(info->nand.IO_ADDR_R); | |
747 | + kfree(&info->mtd); | |
748 | + return 0; | |
749 | +} | |
750 | + | |
751 | +static struct platform_driver omap_nand_driver = { | |
752 | + .probe = omap_nand_probe, | |
753 | + .remove = omap_nand_remove, | |
754 | + .driver = { | |
755 | + .name = DRIVER_NAME, | |
756 | + .owner = THIS_MODULE, | |
757 | + }, | |
758 | +}; | |
759 | + | |
760 | +static int __init omap_nand_init(void) | |
761 | +{ | |
762 | + printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME); | |
763 | + return platform_driver_register(&omap_nand_driver); | |
764 | +} | |
765 | + | |
766 | +static void __exit omap_nand_exit(void) | |
767 | +{ | |
768 | + platform_driver_unregister(&omap_nand_driver); | |
769 | +} | |
770 | + | |
771 | +module_init(omap_nand_init); | |
772 | +module_exit(omap_nand_exit); | |
773 | + | |
774 | +MODULE_ALIAS(DRIVER_NAME); | |
775 | +MODULE_LICENSE("GPL"); | |
776 | +MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards"); |