Eric Lee / linux-smarc-t335x-v3.2

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Commit 717aec7087b8bd4dc15a1d8a2f5cd6473ea51cd1

Authored by Vaibhav Bedia
Committed by Vaibhav Hiremath
1 parent 8dc4be8e6a
Exists in master

arm:omap:am33xx: hwmod cleanup 

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>

Showing 1 changed file with 84 additions and 68 deletions Inline Diff

arch/arm/mach-omap2/omap_hwmod_33xx_data.c
Diff comments   View file @ 717aec7
1 /* 1 /*
2 * Hardware modules present on the AM33XX chips 2 * Hardware modules present on the AM33XX chips
3 * 3 *
4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) {2011} Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This file is automatically generated from the AM33XX hardware databases. 6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2. 9 * published by the Free Software Foundation version 2.
10 * 10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty 12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17 #include <linux/io.h> 17 #include <linux/io.h>
18 18
19 #include <plat/omap_hwmod.h> 19 #include <plat/omap_hwmod.h>
20 #include <plat/cpu.h> 20 #include <plat/cpu.h>
21 #include <plat/gpio.h> 21 #include <plat/gpio.h>
22 #include <plat/dma.h> 22 #include <plat/dma.h>
23 #include <plat/mmc.h> 23 #include <plat/mmc.h>
24 #include <plat/mcspi.h> 24 #include <plat/mcspi.h>
25 25
26 #include "omap_hwmod_common_data.h" 26 #include "omap_hwmod_common_data.h"
27 #include "control.h" 27 #include "control.h"
28 #include "cm33xx.h" 28 #include "cm33xx.h"
29 29
30 /* Backward references (IPs with Bus Master capability) */ 30 /* Backward references (IPs with Bus Master capability) */
31 static struct omap_hwmod am33xx_mpu_hwmod; 31 static struct omap_hwmod am33xx_mpu_hwmod;
32 static struct omap_hwmod am33xx_l3slow_hwmod; 32 static struct omap_hwmod am33xx_l3slow_hwmod;
33 static struct omap_hwmod am33xx_l4wkup_hwmod; 33 static struct omap_hwmod am33xx_l4wkup_hwmod;
34 static struct omap_hwmod am33xx_l4per_hwmod; 34 static struct omap_hwmod am33xx_l4per_hwmod;
35 static struct omap_hwmod am33xx_uart1_hwmod; 35 static struct omap_hwmod am33xx_uart1_hwmod;
36 static struct omap_hwmod am33xx_uart2_hwmod; 36 static struct omap_hwmod am33xx_uart2_hwmod;
37 static struct omap_hwmod am33xx_uart3_hwmod; 37 static struct omap_hwmod am33xx_uart3_hwmod;
38 static struct omap_hwmod am33xx_uart4_hwmod; 38 static struct omap_hwmod am33xx_uart4_hwmod;
39 static struct omap_hwmod am33xx_uart5_hwmod; 39 static struct omap_hwmod am33xx_uart5_hwmod;
40 static struct omap_hwmod am33xx_uart6_hwmod; 40 static struct omap_hwmod am33xx_uart6_hwmod;
41 static struct omap_hwmod am33xx_timer0_hwmod; 41 static struct omap_hwmod am33xx_timer0_hwmod;
42 static struct omap_hwmod am33xx_timer1_hwmod; 42 static struct omap_hwmod am33xx_timer1_hwmod;
43 static struct omap_hwmod am33xx_timer2_hwmod; 43 static struct omap_hwmod am33xx_timer2_hwmod;
44 static struct omap_hwmod am33xx_timer3_hwmod; 44 static struct omap_hwmod am33xx_timer3_hwmod;
45 static struct omap_hwmod am33xx_timer4_hwmod; 45 static struct omap_hwmod am33xx_timer4_hwmod;
46 static struct omap_hwmod am33xx_timer5_hwmod; 46 static struct omap_hwmod am33xx_timer5_hwmod;
47 static struct omap_hwmod am33xx_timer6_hwmod; 47 static struct omap_hwmod am33xx_timer6_hwmod;
48 static struct omap_hwmod am33xx_timer7_hwmod; 48 static struct omap_hwmod am33xx_timer7_hwmod;
49 static struct omap_hwmod am33xx_wd_timer1_hwmod; 49 static struct omap_hwmod am33xx_wd_timer1_hwmod;
50 static struct omap_hwmod am33xx_cpgmac0_hwmod; 50 static struct omap_hwmod am33xx_cpgmac0_hwmod;
51 static struct omap_hwmod am33xx_icss_hwmod; 51 static struct omap_hwmod am33xx_icss_hwmod;
52 static struct omap_hwmod am33xx_ieee5000_hwmod; 52 static struct omap_hwmod am33xx_ieee5000_hwmod;
53 static struct omap_hwmod am33xx_tptc0_hwmod; 53 static struct omap_hwmod am33xx_tptc0_hwmod;
54 static struct omap_hwmod am33xx_tptc1_hwmod; 54 static struct omap_hwmod am33xx_tptc1_hwmod;
55 static struct omap_hwmod am33xx_tptc2_hwmod; 55 static struct omap_hwmod am33xx_tptc2_hwmod;
56 static struct omap_hwmod am33xx_gpio0_hwmod; 56 static struct omap_hwmod am33xx_gpio0_hwmod;
57 static struct omap_hwmod am33xx_gpio1_hwmod; 57 static struct omap_hwmod am33xx_gpio1_hwmod;
58 static struct omap_hwmod am33xx_gpio2_hwmod; 58 static struct omap_hwmod am33xx_gpio2_hwmod;
59 static struct omap_hwmod am33xx_gpio3_hwmod; 59 static struct omap_hwmod am33xx_gpio3_hwmod;
60 static struct omap_hwmod am33xx_i2c1_hwmod; 60 static struct omap_hwmod am33xx_i2c1_hwmod;
61 static struct omap_hwmod am33xx_i2c2_hwmod; 61 static struct omap_hwmod am33xx_i2c2_hwmod;
62 static struct omap_hwmod am33xx_usbss_hwmod; 62 static struct omap_hwmod am33xx_usbss_hwmod;
63 static struct omap_hwmod am33xx_mmc0_hwmod; 63 static struct omap_hwmod am33xx_mmc0_hwmod;
64 static struct omap_hwmod am33xx_mmc1_hwmod; 64 static struct omap_hwmod am33xx_mmc1_hwmod;
65 static struct omap_hwmod am33xx_mmc2_hwmod; 65 static struct omap_hwmod am33xx_mmc2_hwmod;
66 static struct omap_hwmod am33xx_spi0_hwmod; 66 static struct omap_hwmod am33xx_spi0_hwmod;
67 static struct omap_hwmod am33xx_spi1_hwmod; 67 static struct omap_hwmod am33xx_spi1_hwmod;
68 static struct omap_hwmod am33xx_elm_hwmod; 68 static struct omap_hwmod am33xx_elm_hwmod;
69 69
70 /* 70 /*
71 * Interconnects hwmod structures 71 * Interconnects hwmod structures
72 * hwmods that compose the global AM33XX OCP interconnect 72 * hwmods that compose the global AM33XX OCP interconnect
73 */ 73 */
74 74
75 /* MPU -> L3_SLOW Peripheral interface */ 75 /* MPU -> L3_SLOW Peripheral interface */
76 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = { 76 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
77 .master = &am33xx_mpu_hwmod, 77 .master = &am33xx_mpu_hwmod,
78 .slave = &am33xx_l3slow_hwmod, 78 .slave = &am33xx_l3slow_hwmod,
79 .user = OCP_USER_MPU, 79 .user = OCP_USER_MPU,
80 }; 80 };
81 81
82 /* L3 SLOW -> L4_PER Peripheral interface */ 82 /* L3 SLOW -> L4_PER Peripheral interface */
83 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = { 83 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
84 .master = &am33xx_l3slow_hwmod, 84 .master = &am33xx_l3slow_hwmod,
85 .slave = &am33xx_l4per_hwmod, 85 .slave = &am33xx_l4per_hwmod,
86 .user = OCP_USER_MPU, 86 .user = OCP_USER_MPU,
87 }; 87 };
88 88
89 /* L3 SLOW -> L4_WKUP Peripheral interface */ 89 /* L3 SLOW -> L4_WKUP Peripheral interface */
90 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = { 90 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
91 .master = &am33xx_l3slow_hwmod, 91 .master = &am33xx_l3slow_hwmod,
92 .slave = &am33xx_l4wkup_hwmod, 92 .slave = &am33xx_l4wkup_hwmod,
93 .user = OCP_USER_MPU, 93 .user = OCP_USER_MPU,
94 }; 94 };
95 95
96 /* Master interfaces on the L4_WKUP interconnect */ 96 /* Master interfaces on the L4_WKUP interconnect */
97 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = { 97 static struct omap_hwmod_ocp_if *am33xx_l3_slow_masters[] = {
98 &am33xx_l3_slow__l4_per, 98 &am33xx_l3_slow__l4_per,
99 &am33xx_l3_slow__l4_wkup, 99 &am33xx_l3_slow__l4_wkup,
100 }; 100 };
101 101
102 /* Slave interfaces on the L3_SLOW interconnect */ 102 /* Slave interfaces on the L3_SLOW interconnect */
103 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = { 103 static struct omap_hwmod_ocp_if *am33xx_l3_slow_slaves[] = {
104 &am33xx_mpu__l3_slow, 104 &am33xx_mpu__l3_slow,
105 }; 105 };
106 106
107 static struct omap_hwmod am33xx_l3slow_hwmod = { 107 static struct omap_hwmod am33xx_l3slow_hwmod = {
108 .name = "l3_slow", 108 .name = "l3_slow",
109 .class = &l3_hwmod_class, 109 .class = &l3_hwmod_class,
110 .clkdm_name = "l3s_clkdm", 110 .clkdm_name = "l3s_clkdm",
111 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 111 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
112 .masters = am33xx_l3_slow_masters, 112 .masters = am33xx_l3_slow_masters,
113 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters), 113 .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
114 .slaves = am33xx_l3_slow_slaves, 114 .slaves = am33xx_l3_slow_slaves,
115 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves), 115 .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
116 }; 116 };
117 117
118 /* L4 PER -> GPIO2 */ 118 /* L4 PER -> GPIO2 */
119 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = { 119 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
120 { 120 {
121 .pa_start = AM33XX_GPIO1_BASE, 121 .pa_start = AM33XX_GPIO1_BASE,
122 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1, 122 .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
123 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 123 .flags = ADDR_TYPE_RT
124 }, 124 },
125 { }
125 }; 126 };
126 127
127 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { 128 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
128 .master = &am33xx_l4per_hwmod, 129 .master = &am33xx_l4per_hwmod,
129 .slave = &am33xx_gpio1_hwmod, 130 .slave = &am33xx_gpio1_hwmod,
130 .clk = "l4ls_gclk", 131 .clk = "l4ls_gclk",
131 .addr = am33xx_gpio1_addrs, 132 .addr = am33xx_gpio1_addrs,
132 .user = OCP_USER_MPU | OCP_USER_SDMA, 133 .user = OCP_USER_MPU | OCP_USER_SDMA,
133 }; 134 };
134 135
135 /* L4 PER -> GPIO3 */ 136 /* L4 PER -> GPIO3 */
136 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = { 137 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
137 { 138 {
138 .pa_start = AM33XX_GPIO2_BASE, 139 .pa_start = AM33XX_GPIO2_BASE,
139 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1, 140 .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
140 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 141 .flags = ADDR_TYPE_RT
141 }, 142 },
143 { }
142 }; 144 };
143 145
144 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { 146 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
145 .master = &am33xx_l4per_hwmod, 147 .master = &am33xx_l4per_hwmod,
146 .slave = &am33xx_gpio2_hwmod, 148 .slave = &am33xx_gpio2_hwmod,
147 .clk = "l4ls_gclk", 149 .clk = "l4ls_gclk",
148 .addr = am33xx_gpio2_addrs, 150 .addr = am33xx_gpio2_addrs,
149 .user = OCP_USER_MPU | OCP_USER_SDMA, 151 .user = OCP_USER_MPU | OCP_USER_SDMA,
150 }; 152 };
151 153
152 /* L4 PER -> GPIO4 */ 154 /* L4 PER -> GPIO4 */
153 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = { 155 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
154 { 156 {
155 .pa_start = AM33XX_GPIO3_BASE, 157 .pa_start = AM33XX_GPIO3_BASE,
156 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1, 158 .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
157 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 159 .flags = ADDR_TYPE_RT
158 }, 160 },
161 { }
159 }; 162 };
160 163
161 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { 164 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
162 .master = &am33xx_l4per_hwmod, 165 .master = &am33xx_l4per_hwmod,
163 .slave = &am33xx_gpio3_hwmod, 166 .slave = &am33xx_gpio3_hwmod,
164 .clk = "l4ls_gclk", 167 .clk = "l4ls_gclk",
165 .addr = am33xx_gpio3_addrs, 168 .addr = am33xx_gpio3_addrs,
166 .user = OCP_USER_MPU | OCP_USER_SDMA, 169 .user = OCP_USER_MPU | OCP_USER_SDMA,
167 }; 170 };
168 171
169 /* Master interfaces on the L4_PER interconnect */ 172 /* Master interfaces on the L4_PER interconnect */
170 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = { 173 static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
171 &am33xx_l4_per__gpio1, 174 &am33xx_l4_per__gpio1,
172 &am33xx_l4_per__gpio2, 175 &am33xx_l4_per__gpio2,
173 &am33xx_l4_per__gpio3, 176 &am33xx_l4_per__gpio3,
174 }; 177 };
175 /* Slave interfaces on the L4_PER interconnect */ 178 /* Slave interfaces on the L4_PER interconnect */
176 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = { 179 static struct omap_hwmod_ocp_if *am33xx_l4_per_slaves[] = {
177 &am33xx_l3_slow__l4_per, 180 &am33xx_l3_slow__l4_per,
178 }; 181 };
179 182
180 static struct omap_hwmod am33xx_l4per_hwmod = { 183 static struct omap_hwmod am33xx_l4per_hwmod = {
181 .name = "l4_per", 184 .name = "l4_per",
182 .class = &l4_hwmod_class, 185 .class = &l4_hwmod_class,
183 .clkdm_name = "l4ls_clkdm", 186 .clkdm_name = "l4ls_clkdm",
184 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 187 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
185 .masters = am33xx_l4_per_masters, 188 .masters = am33xx_l4_per_masters,
186 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters), 189 .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
187 .slaves = am33xx_l4_per_slaves, 190 .slaves = am33xx_l4_per_slaves,
188 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves), 191 .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
189 }; 192 };
190 193
191 /* L4 WKUP -> I2C1 */ 194 /* L4 WKUP -> I2C1 */
192 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = { 195 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
193 { 196 {
194 .pa_start = AM33XX_I2C0_BASE, 197 .pa_start = AM33XX_I2C0_BASE,
195 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1, 198 .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
196 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 199 .flags = ADDR_TYPE_RT
197 }, 200 },
201 { }
198 }; 202 };
199 203
200 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = { 204 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
201 .master = &am33xx_l4wkup_hwmod, 205 .master = &am33xx_l4wkup_hwmod,
202 .slave = &am33xx_i2c1_hwmod, 206 .slave = &am33xx_i2c1_hwmod,
203 .addr = am33xx_i2c1_addr_space, 207 .addr = am33xx_i2c1_addr_space,
204 .user = OCP_USER_MPU, 208 .user = OCP_USER_MPU,
205 }; 209 };
206 210
207 /* L4 WKUP -> GPIO1 */ 211 /* L4 WKUP -> GPIO1 */
208 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = { 212 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
209 { 213 {
210 .pa_start = AM33XX_GPIO0_BASE, 214 .pa_start = AM33XX_GPIO0_BASE,
211 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1, 215 .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
212 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 216 .flags = ADDR_TYPE_RT
213 }, 217 },
218 { }
214 }; 219 };
215 220
216 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { 221 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
217 .master = &am33xx_l4wkup_hwmod, 222 .master = &am33xx_l4wkup_hwmod,
218 .slave = &am33xx_gpio0_hwmod, 223 .slave = &am33xx_gpio0_hwmod,
219 .clk = "l4ls_gclk", 224 .clk = "l4ls_gclk",
220 .addr = am33xx_gpio0_addrs, 225 .addr = am33xx_gpio0_addrs,
221 .user = OCP_USER_MPU | OCP_USER_SDMA, 226 .user = OCP_USER_MPU | OCP_USER_SDMA,
222 }; 227 };
223 228
224 /* Master interfaces on the L4_WKUP interconnect */ 229 /* Master interfaces on the L4_WKUP interconnect */
225 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = { 230 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
226 &am33xx_l4_wkup__gpio0, 231 &am33xx_l4_wkup__gpio0,
227 }; 232 };
228 /* Slave interfaces on the L4_WKUP interconnect */ 233 /* Slave interfaces on the L4_WKUP interconnect */
229 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = { 234 static struct omap_hwmod_ocp_if *am33xx_l4_wkup_slaves[] = {
230 &am33xx_l3_slow__l4_wkup, 235 &am33xx_l3_slow__l4_wkup,
231 }; 236 };
232 237
233 static struct omap_hwmod am33xx_l4wkup_hwmod = { 238 static struct omap_hwmod am33xx_l4wkup_hwmod = {
234 .name = "l4_wkup", 239 .name = "l4_wkup",
235 .class = &l4_hwmod_class, 240 .class = &l4_hwmod_class,
236 .clkdm_name = "l4_wkup_clkdm", 241 .clkdm_name = "l4_wkup_clkdm",
237 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 242 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
238 .masters = am33xx_l4_wkup_masters, 243 .masters = am33xx_l4_wkup_masters,
239 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters), 244 .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
240 .slaves = am33xx_l4_wkup_slaves, 245 .slaves = am33xx_l4_wkup_slaves,
241 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves), 246 .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
242 }; 247 };
243 248
244 /* 'adc_tsc' class */ 249 /* 'adc_tsc' class */
245 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { 250 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
246 .name = "adc_tsc", 251 .name = "adc_tsc",
247 }; 252 };
248 253
249 /* adc_tsc */ 254 /* adc_tsc */
250 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = { 255 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
251 { .irq = AM33XX_IRQ_TSC }, 256 { .irq = AM33XX_IRQ_TSC },
252 { .irq = -1 } 257 { .irq = -1 }
253 }; 258 };
254 259
255 static struct omap_hwmod am33xx_adc_tsc_hwmod = { 260 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
256 .name = "adc_tsc", 261 .name = "adc_tsc",
257 .class = &am33xx_adc_tsc_hwmod_class, 262 .class = &am33xx_adc_tsc_hwmod_class,
258 .mpu_irqs = am33xx_adc_tsc_irqs, 263 .mpu_irqs = am33xx_adc_tsc_irqs,
259 .main_clk = "adc_tsc_fck", 264 .main_clk = "adc_tsc_fck",
260 .clkdm_name = "l4_wkup_clkdm", 265 .clkdm_name = "l4_wkup_clkdm",
261 .prcm = { 266 .prcm = {
262 .omap4 = { 267 .omap4 = {
263 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, 268 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
264 .modulemode = MODULEMODE_SWCTRL, 269 .modulemode = MODULEMODE_SWCTRL,
265 }, 270 },
266 }, 271 },
267 }; 272 };
268 273
269 /* 'aes' class */ 274 /* 'aes' class */
270 static struct omap_hwmod_class am33xx_aes_hwmod_class = { 275 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
271 .name = "aes", 276 .name = "aes",
272 }; 277 };
273 278
274 /* aes0 */ 279 /* aes0 */
275 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = { 280 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
276 { .irq = AM33XX_IRQ_AESEIP36t0_S }, 281 { .irq = AM33XX_IRQ_AESEIP36t0_S },
277 { .irq = -1 }, 282 { .irq = -1 }
278 }; 283 };
279 284
280 static struct omap_hwmod am33xx_aes0_hwmod = { 285 static struct omap_hwmod am33xx_aes0_hwmod = {
281 .name = "aes0", 286 .name = "aes0",
282 .class = &am33xx_aes_hwmod_class, 287 .class = &am33xx_aes_hwmod_class,
283 .mpu_irqs = am33xx_aes0_irqs, 288 .mpu_irqs = am33xx_aes0_irqs,
284 .main_clk = "aes0_fck", 289 .main_clk = "aes0_fck",
285 .clkdm_name = "l3_clkdm", 290 .clkdm_name = "l3_clkdm",
286 .prcm = { 291 .prcm = {
287 .omap4 = { 292 .omap4 = {
288 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, 293 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
289 .modulemode = MODULEMODE_SWCTRL, 294 .modulemode = MODULEMODE_SWCTRL,
290 }, 295 },
291 }, 296 },
292 }; 297 };
293 298
294 /* 'cefuse' class */ 299 /* 'cefuse' class */
295 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { 300 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
296 .name = "cefuse", 301 .name = "cefuse",
297 }; 302 };
298 303
299 /* cefuse */ 304 /* cefuse */
300 static struct omap_hwmod am33xx_cefuse_hwmod = { 305 static struct omap_hwmod am33xx_cefuse_hwmod = {
301 .name = "cefuse", 306 .name = "cefuse",
302 .class = &am33xx_cefuse_hwmod_class, 307 .class = &am33xx_cefuse_hwmod_class,
303 .main_clk = "cefuse_fck", 308 .main_clk = "cefuse_fck",
304 .clkdm_name = "l4_cefuse_clkdm", 309 .clkdm_name = "l4_cefuse_clkdm",
305 .prcm = { 310 .prcm = {
306 .omap4 = { 311 .omap4 = {
307 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, 312 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
308 .modulemode = MODULEMODE_SWCTRL, 313 .modulemode = MODULEMODE_SWCTRL,
309 }, 314 },
310 }, 315 },
311 }; 316 };
312 317
313 /* 'clkdiv32k' class */ 318 /* 'clkdiv32k' class */
314 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { 319 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
315 .name = "clkdiv32k", 320 .name = "clkdiv32k",
316 }; 321 };
317 322
318 /* clkdiv32k */ 323 /* clkdiv32k */
319 static struct omap_hwmod am33xx_clkdiv32k_hwmod = { 324 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
320 .name = "clkdiv32k", 325 .name = "clkdiv32k",
321 .class = &am33xx_clkdiv32k_hwmod_class, 326 .class = &am33xx_clkdiv32k_hwmod_class,
322 .main_clk = "clkdiv32k_ick", 327 .main_clk = "clkdiv32k_ick",
323 .clkdm_name = "clk_24mhz_clkdm", 328 .clkdm_name = "clk_24mhz_clkdm",
324 .prcm = { 329 .prcm = {
325 .omap4 = { 330 .omap4 = {
326 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, 331 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
327 .modulemode = MODULEMODE_SWCTRL, 332 .modulemode = MODULEMODE_SWCTRL,
328 }, 333 },
329 }, 334 },
330 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 335 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
331 }; 336 };
332 337
333 /* 'control' class */ 338 /* 'control' class */
334 static struct omap_hwmod_class am33xx_control_hwmod_class = { 339 static struct omap_hwmod_class am33xx_control_hwmod_class = {
335 .name = "control", 340 .name = "control",
336 }; 341 };
337 342
338 /* control */ 343 /* control */
339 static struct omap_hwmod_irq_info am33xx_control_irqs[] = { 344 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
340 { .irq = AM33XX_IRQ_CONTROL_PLATFORM }, 345 { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
341 { .irq = -1 }, 346 { .irq = -1 }
342 }; 347 };
343 348
344 static struct omap_hwmod am33xx_control_hwmod = { 349 static struct omap_hwmod am33xx_control_hwmod = {
345 .name = "control", 350 .name = "control",
346 .class = &am33xx_control_hwmod_class, 351 .class = &am33xx_control_hwmod_class,
347 .mpu_irqs = am33xx_control_irqs, 352 .mpu_irqs = am33xx_control_irqs,
348 .main_clk = "control_fck", 353 .main_clk = "control_fck",
349 .clkdm_name = "l4_wkup_clkdm", 354 .clkdm_name = "l4_wkup_clkdm",
350 .prcm = { 355 .prcm = {
351 .omap4 = { 356 .omap4 = {
352 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, 357 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
353 .modulemode = MODULEMODE_SWCTRL, 358 .modulemode = MODULEMODE_SWCTRL,
354 }, 359 },
355 }, 360 },
356 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 361 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
357 }; 362 };
358 363
359 /* 'cpgmac0' class */ 364 /* 'cpgmac0' class */
360 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { 365 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
361 .name = "cpgmac0", 366 .name = "cpgmac0",
362 }; 367 };
363 368
364 /* cpgmac0 */ 369 /* cpgmac0 */
365 static struct omap_hwmod am33xx_cpgmac0_hwmod = { 370 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
366 .name = "cpgmac0", 371 .name = "cpgmac0",
367 .class = &am33xx_cpgmac0_hwmod_class, 372 .class = &am33xx_cpgmac0_hwmod_class,
368 .main_clk = "cpgmac0_ick", 373 .main_clk = "cpgmac0_ick",
369 .clkdm_name = "cpsw_125mhz_clkdm", 374 .clkdm_name = "cpsw_125mhz_clkdm",
370 .prcm = { 375 .prcm = {
371 .omap4 = { 376 .omap4 = {
372 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, 377 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
373 .modulemode = MODULEMODE_SWCTRL, 378 .modulemode = MODULEMODE_SWCTRL,
374 }, 379 },
375 }, 380 },
376 }; 381 };
377 382
378 /* 'dcan' class */ 383 /* 'dcan' class */
379 static struct omap_hwmod_class am33xx_dcan_hwmod_class = { 384 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
380 .name = "dcan", 385 .name = "dcan",
381 }; 386 };
382 387
383 /* dcan0 */ 388 /* dcan0 */
384 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = { 389 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
385 { .irq = AM33XX_IRQ_DCAN0_0 }, 390 { .irq = AM33XX_IRQ_DCAN0_0 },
386 { .irq = -1 }, 391 { .irq = -1 }
387 }; 392 };
388 393
389 static struct omap_hwmod am33xx_dcan0_hwmod = { 394 static struct omap_hwmod am33xx_dcan0_hwmod = {
390 .name = "dcan0", 395 .name = "dcan0",
391 .class = &am33xx_dcan_hwmod_class, 396 .class = &am33xx_dcan_hwmod_class,
392 .mpu_irqs = am33xx_dcan0_irqs, 397 .mpu_irqs = am33xx_dcan0_irqs,
393 .main_clk = "dcan0_fck", 398 .main_clk = "dcan0_fck",
394 .clkdm_name = "l4ls_clkdm", 399 .clkdm_name = "l4ls_clkdm",
395 .prcm = { 400 .prcm = {
396 .omap4 = { 401 .omap4 = {
397 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, 402 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
398 .modulemode = MODULEMODE_SWCTRL, 403 .modulemode = MODULEMODE_SWCTRL,
399 }, 404 },
400 }, 405 },
401 }; 406 };
402 407
403 /* dcan1 */ 408 /* dcan1 */
404 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = { 409 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
405 { .irq = AM33XX_IRQ_DCAN1_0 }, 410 { .irq = AM33XX_IRQ_DCAN1_0 },
406 { .irq = -1 }, 411 { .irq = -1 }
407 }; 412 };
408 static struct omap_hwmod am33xx_dcan1_hwmod = { 413 static struct omap_hwmod am33xx_dcan1_hwmod = {
409 .name = "dcan1", 414 .name = "dcan1",
410 .class = &am33xx_dcan_hwmod_class, 415 .class = &am33xx_dcan_hwmod_class,
411 .mpu_irqs = am33xx_dcan1_irqs, 416 .mpu_irqs = am33xx_dcan1_irqs,
412 .main_clk = "dcan1_fck", 417 .main_clk = "dcan1_fck",
413 .clkdm_name = "l4ls_clkdm", 418 .clkdm_name = "l4ls_clkdm",
414 .prcm = { 419 .prcm = {
415 .omap4 = { 420 .omap4 = {
416 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, 421 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
417 .modulemode = MODULEMODE_SWCTRL, 422 .modulemode = MODULEMODE_SWCTRL,
418 }, 423 },
419 }, 424 },
420 }; 425 };
421 426
422 /* 'debugss' class */ 427 /* 'debugss' class */
423 static struct omap_hwmod_class am33xx_debugss_hwmod_class = { 428 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
424 .name = "debugss", 429 .name = "debugss",
425 }; 430 };
426 431
427 /* debugss */ 432 /* debugss */
428 static struct omap_hwmod am33xx_debugss_hwmod = { 433 static struct omap_hwmod am33xx_debugss_hwmod = {
429 .name = "debugss", 434 .name = "debugss",
430 .class = &am33xx_debugss_hwmod_class, 435 .class = &am33xx_debugss_hwmod_class,
431 .main_clk = "debugss_ick", 436 .main_clk = "debugss_ick",
432 .clkdm_name = "l3_aon_clkdm", 437 .clkdm_name = "l3_aon_clkdm",
433 .prcm = { 438 .prcm = {
434 .omap4 = { 439 .omap4 = {
435 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, 440 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
436 .modulemode = MODULEMODE_SWCTRL, 441 .modulemode = MODULEMODE_SWCTRL,
437 }, 442 },
438 }, 443 },
439 #ifdef CONFIG_DEBUG_JTAG_ENABLE 444 #ifdef CONFIG_DEBUG_JTAG_ENABLE
440 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 445 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
441 #endif 446 #endif
442 }; 447 };
443 448
444 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { 449 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
445 .rev_offs = 0x0000, 450 .rev_offs = 0x0000,
446 .sysc_offs = 0x0010, 451 .sysc_offs = 0x0010,
447 .syss_offs = 0x0014, 452 .syss_offs = 0x0014,
448 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 453 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
449 SYSC_HAS_SOFTRESET | 454 SYSC_HAS_SOFTRESET |
450 SYSS_HAS_RESET_STATUS), 455 SYSS_HAS_RESET_STATUS),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
452 .sysc_fields = &omap_hwmod_sysc_type1, 457 .sysc_fields = &omap_hwmod_sysc_type1,
453 }; 458 };
454 /* 'elm' class */ 459 /* 'elm' class */
455 static struct omap_hwmod_class am33xx_elm_hwmod_class = { 460 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
456 .name = "elm", 461 .name = "elm",
457 .sysc = &am33xx_elm_sysc, 462 .sysc = &am33xx_elm_sysc,
458 }; 463 };
459 464
460 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = { 465 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
461 { .irq = AM33XX_IRQ_ELM }, 466 { .irq = AM33XX_IRQ_ELM },
462 { .irq = -1 } 467 { .irq = -1 }
463 }; 468 };
464 469
465 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { 470 struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
466 { 471 {
467 .pa_start = AM33XX_ELM_BASE, 472 .pa_start = AM33XX_ELM_BASE,
468 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1, 473 .pa_end = AM33XX_ELM_BASE + SZ_8K - 1,
469 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 474 .flags = ADDR_TYPE_RT
470 }, 475 },
471 { } 476 { }
472 }; 477 };
473 478
474 struct omap_hwmod_ocp_if am33xx_l4_core__elm = { 479 struct omap_hwmod_ocp_if am33xx_l4_core__elm = {
475 .master = &am33xx_l4per_hwmod, 480 .master = &am33xx_l4per_hwmod,
476 .slave = &am33xx_elm_hwmod, 481 .slave = &am33xx_elm_hwmod,
477 .addr = am33xx_elm_addr_space, 482 .addr = am33xx_elm_addr_space,
478 .user = OCP_USER_MPU, 483 .user = OCP_USER_MPU,
479 }; 484 };
480 485
481 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = { 486 static struct omap_hwmod_ocp_if *am33xx_elm_slaves[] = {
482 &am33xx_l4_core__elm, 487 &am33xx_l4_core__elm,
483 }; 488 };
484 489
485 /* elm */ 490 /* elm */
486 static struct omap_hwmod am33xx_elm_hwmod = { 491 static struct omap_hwmod am33xx_elm_hwmod = {
487 .name = "elm", 492 .name = "elm",
488 .class = &am33xx_elm_hwmod_class, 493 .class = &am33xx_elm_hwmod_class,
489 .mpu_irqs = am33xx_elm_irqs, 494 .mpu_irqs = am33xx_elm_irqs,
490 .main_clk = "elm_fck", 495 .main_clk = "elm_fck",
491 .clkdm_name = "l4ls_clkdm", 496 .clkdm_name = "l4ls_clkdm",
492 .slaves = am33xx_elm_slaves, 497 .slaves = am33xx_elm_slaves,
493 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves), 498 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
494 .prcm = { 499 .prcm = {
495 .omap4 = { 500 .omap4 = {
496 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, 501 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
497 .modulemode = MODULEMODE_SWCTRL, 502 .modulemode = MODULEMODE_SWCTRL,
498 }, 503 },
499 }, 504 },
500 }; 505 };
501 506
502 /* 'emif_fw' class */ 507 /* 'emif_fw' class */
503 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = { 508 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
504 .name = "emif_fw", 509 .name = "emif_fw",
505 }; 510 };
506 511
507 /* emif_fw */ 512 /* emif_fw */
508 static struct omap_hwmod am33xx_emif_fw_hwmod = { 513 static struct omap_hwmod am33xx_emif_fw_hwmod = {
509 .name = "emif_fw", 514 .name = "emif_fw",
510 .class = &am33xx_emif_fw_hwmod_class, 515 .class = &am33xx_emif_fw_hwmod_class,
511 .main_clk = "emif_fw_fck", 516 .main_clk = "emif_fw_fck",
512 .clkdm_name = "l4fw_clkdm", 517 .clkdm_name = "l4fw_clkdm",
513 .prcm = { 518 .prcm = {
514 .omap4 = { 519 .omap4 = {
515 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET, 520 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
516 .modulemode = MODULEMODE_SWCTRL, 521 .modulemode = MODULEMODE_SWCTRL,
517 }, 522 },
518 }, 523 },
519 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE, 524 .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
520 }; 525 };
521 526
522 /* 'epwmss' class */ 527 /* 'epwmss' class */
523 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { 528 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
524 .name = "epwmss", 529 .name = "epwmss",
525 }; 530 };
526 531
527 /* epwmss0 */ 532 /* epwmss0 */
528 static struct omap_hwmod am33xx_epwmss0_hwmod = { 533 static struct omap_hwmod am33xx_epwmss0_hwmod = {
529 .name = "epwmss0", 534 .name = "epwmss0",
530 .class = &am33xx_epwmss_hwmod_class, 535 .class = &am33xx_epwmss_hwmod_class,
531 .main_clk = "epwmss0_fck", 536 .main_clk = "epwmss0_fck",
532 .clkdm_name = "l4ls_clkdm", 537 .clkdm_name = "l4ls_clkdm",
533 .prcm = { 538 .prcm = {
534 .omap4 = { 539 .omap4 = {
535 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, 540 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
536 .modulemode = MODULEMODE_SWCTRL, 541 .modulemode = MODULEMODE_SWCTRL,
537 }, 542 },
538 }, 543 },
539 }; 544 };
540 545
541 /* epwmss1 */ 546 /* epwmss1 */
542 static struct omap_hwmod am33xx_epwmss1_hwmod = { 547 static struct omap_hwmod am33xx_epwmss1_hwmod = {
543 .name = "epwmss1", 548 .name = "epwmss1",
544 .class = &am33xx_epwmss_hwmod_class, 549 .class = &am33xx_epwmss_hwmod_class,
545 .main_clk = "epwmss1_fck", 550 .main_clk = "epwmss1_fck",
546 .clkdm_name = "l4ls_clkdm", 551 .clkdm_name = "l4ls_clkdm",
547 .prcm = { 552 .prcm = {
548 .omap4 = { 553 .omap4 = {
549 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, 554 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
550 .modulemode = MODULEMODE_SWCTRL, 555 .modulemode = MODULEMODE_SWCTRL,
551 }, 556 },
552 }, 557 },
553 }; 558 };
554 559
555 /* epwmss2 */ 560 /* epwmss2 */
556 static struct omap_hwmod am33xx_epwmss2_hwmod = { 561 static struct omap_hwmod am33xx_epwmss2_hwmod = {
557 .name = "epwmss2", 562 .name = "epwmss2",
558 .class = &am33xx_epwmss_hwmod_class, 563 .class = &am33xx_epwmss_hwmod_class,
559 .main_clk = "epwmss2_fck", 564 .main_clk = "epwmss2_fck",
560 .clkdm_name = "l4ls_clkdm", 565 .clkdm_name = "l4ls_clkdm",
561 .prcm = { 566 .prcm = {
562 .omap4 = { 567 .omap4 = {
563 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, 568 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
564 .modulemode = MODULEMODE_SWCTRL, 569 .modulemode = MODULEMODE_SWCTRL,
565 }, 570 },
566 }, 571 },
567 }; 572 };
568 573
569 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { 574 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
570 .rev_offs = 0x0000, 575 .rev_offs = 0x0000,
571 .sysc_offs = 0x0010, 576 .sysc_offs = 0x0010,
572 .syss_offs = 0x0114, 577 .syss_offs = 0x0114,
573 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 578 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
574 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 579 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
575 SYSS_HAS_RESET_STATUS), 580 SYSS_HAS_RESET_STATUS),
576 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 581 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
577 SIDLE_SMART_WKUP), 582 SIDLE_SMART_WKUP),
578 .sysc_fields = &omap_hwmod_sysc_type1, 583 .sysc_fields = &omap_hwmod_sysc_type1,
579 }; 584 };
580 585
581 /* 'gpio' class */ 586 /* 'gpio' class */
582 static struct omap_hwmod_class am33xx_gpio_hwmod_class = { 587 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
583 .name = "gpio", 588 .name = "gpio",
584 .sysc = &am33xx_gpio_sysc, 589 .sysc = &am33xx_gpio_sysc,
585 .rev = 2, 590 .rev = 2,
586 }; 591 };
587 592
588 /* gpio dev_attr */ 593 /* gpio dev_attr */
589 static struct omap_gpio_dev_attr gpio_dev_attr = { 594 static struct omap_gpio_dev_attr gpio_dev_attr = {
590 .bank_width = 32, 595 .bank_width = 32,
591 .dbck_flag = true, 596 .dbck_flag = true,
592 }; 597 };
593 598
594 /* gpio0 */ 599 /* gpio0 */
595 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = { 600 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
596 { .irq = AM33XX_IRQ_GPIO0_1 }, 601 { .irq = AM33XX_IRQ_GPIO0_1 },
597 { .irq = -1 }, 602 { .irq = -1 }
598 }; 603 };
599 604
600 /* gpio0 slave ports */ 605 /* gpio0 slave ports */
601 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = { 606 static struct omap_hwmod_ocp_if *am33xx_gpio0_slaves[] = {
602 &am33xx_l4_wkup__gpio0, 607 &am33xx_l4_wkup__gpio0,
603 }; 608 };
604 609
605 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { 610 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
606 { .role = "dbclk", .clk = "gpio0_dbclk" }, 611 { .role = "dbclk", .clk = "gpio0_dbclk" },
607 }; 612 };
608 613
609 /* gpio0 */ 614 /* gpio0 */
610 static struct omap_hwmod am33xx_gpio0_hwmod = { 615 static struct omap_hwmod am33xx_gpio0_hwmod = {
611 .name = "gpio1", 616 .name = "gpio1",
612 .class = &am33xx_gpio_hwmod_class, 617 .class = &am33xx_gpio_hwmod_class,
613 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
614 .mpu_irqs = am33xx_gpio0_irqs, 619 .mpu_irqs = am33xx_gpio0_irqs,
615 .main_clk = "gpio0_ick", 620 .main_clk = "gpio0_ick",
616 .clkdm_name = "l4_wkup_clkdm", 621 .clkdm_name = "l4_wkup_clkdm",
617 .prcm = { 622 .prcm = {
618 .omap4 = { 623 .omap4 = {
619 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, 624 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
620 .modulemode = MODULEMODE_SWCTRL, 625 .modulemode = MODULEMODE_SWCTRL,
621 }, 626 },
622 }, 627 },
623 .opt_clks = gpio0_opt_clks, 628 .opt_clks = gpio0_opt_clks,
624 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), 629 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
625 .dev_attr = &gpio_dev_attr, 630 .dev_attr = &gpio_dev_attr,
626 .slaves = am33xx_gpio0_slaves, 631 .slaves = am33xx_gpio0_slaves,
627 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves), 632 .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
628 }; 633 };
629 634
630 /* gpio1 */ 635 /* gpio1 */
631 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = { 636 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
632 { .irq = AM33XX_IRQ_GPIO1_1 }, 637 { .irq = AM33XX_IRQ_GPIO1_1 },
633 { .irq = -1 }, 638 { .irq = -1 }
634 }; 639 };
635 640
636 /* gpio1 slave ports */ 641 /* gpio1 slave ports */
637 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = { 642 static struct omap_hwmod_ocp_if *am33xx_gpio1_slaves[] = {
638 &am33xx_l4_per__gpio1, 643 &am33xx_l4_per__gpio1,
639 }; 644 };
640 645
641 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 646 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
642 { .role = "dbclk", .clk = "gpio1_dbclk" }, 647 { .role = "dbclk", .clk = "gpio1_dbclk" },
643 }; 648 };
644 649
645 static struct omap_hwmod am33xx_gpio1_hwmod = { 650 static struct omap_hwmod am33xx_gpio1_hwmod = {
646 .name = "gpio2", 651 .name = "gpio2",
647 .class = &am33xx_gpio_hwmod_class, 652 .class = &am33xx_gpio_hwmod_class,
648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 653 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
649 .mpu_irqs = am33xx_gpio1_irqs, 654 .mpu_irqs = am33xx_gpio1_irqs,
650 .main_clk = "gpio1_ick", 655 .main_clk = "gpio1_ick",
651 .clkdm_name = "l4ls_clkdm", 656 .clkdm_name = "l4ls_clkdm",
652 .prcm = { 657 .prcm = {
653 .omap4 = { 658 .omap4 = {
654 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, 659 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
655 .modulemode = MODULEMODE_SWCTRL, 660 .modulemode = MODULEMODE_SWCTRL,
656 }, 661 },
657 }, 662 },
658 .opt_clks = gpio1_opt_clks, 663 .opt_clks = gpio1_opt_clks,
659 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 664 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
660 .dev_attr = &gpio_dev_attr, 665 .dev_attr = &gpio_dev_attr,
661 .slaves = am33xx_gpio1_slaves, 666 .slaves = am33xx_gpio1_slaves,
662 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves), 667 .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
663 }; 668 };
664 669
665 /* gpio2 */ 670 /* gpio2 */
666 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = { 671 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
667 { .irq = AM33XX_IRQ_GPIO2_1 }, 672 { .irq = AM33XX_IRQ_GPIO2_1 },
668 { .irq = -1 }, 673 { .irq = -1 }
669 }; 674 };
670 675
671 /* gpio2 slave ports */ 676 /* gpio2 slave ports */
672 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = { 677 static struct omap_hwmod_ocp_if *am33xx_gpio2_slaves[] = {
673 &am33xx_l4_per__gpio2, 678 &am33xx_l4_per__gpio2,
674 }; 679 };
675 680
676 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 681 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
677 { .role = "dbclk", .clk = "gpio2_dbclk" }, 682 { .role = "dbclk", .clk = "gpio2_dbclk" },
678 }; 683 };
679 684
680 /* gpio2 */ 685 /* gpio2 */
681 static struct omap_hwmod am33xx_gpio2_hwmod = { 686 static struct omap_hwmod am33xx_gpio2_hwmod = {
682 .name = "gpio3", 687 .name = "gpio3",
683 .class = &am33xx_gpio_hwmod_class, 688 .class = &am33xx_gpio_hwmod_class,
684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 689 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
685 .mpu_irqs = am33xx_gpio2_irqs, 690 .mpu_irqs = am33xx_gpio2_irqs,
686 .main_clk = "gpio2_ick", 691 .main_clk = "gpio2_ick",
687 .clkdm_name = "l4ls_clkdm", 692 .clkdm_name = "l4ls_clkdm",
688 .prcm = { 693 .prcm = {
689 .omap4 = { 694 .omap4 = {
690 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, 695 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
691 .modulemode = MODULEMODE_SWCTRL, 696 .modulemode = MODULEMODE_SWCTRL,
692 }, 697 },
693 }, 698 },
694 .opt_clks = gpio2_opt_clks, 699 .opt_clks = gpio2_opt_clks,
695 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 700 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
696 .dev_attr = &gpio_dev_attr, 701 .dev_attr = &gpio_dev_attr,
697 .slaves = am33xx_gpio2_slaves, 702 .slaves = am33xx_gpio2_slaves,
698 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves), 703 .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
699 }; 704 };
700 705
701 /* gpio3 */ 706 /* gpio3 */
702 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = { 707 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
703 { .irq = AM33XX_IRQ_GPIO3_1 }, 708 { .irq = AM33XX_IRQ_GPIO3_1 },
704 { .irq = -1 }, 709 { .irq = -1 }
705 }; 710 };
706 711
707 /* gpio3 slave ports */ 712 /* gpio3 slave ports */
708 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = { 713 static struct omap_hwmod_ocp_if *am33xx_gpio3_slaves[] = {
709 &am33xx_l4_per__gpio3, 714 &am33xx_l4_per__gpio3,
710 }; 715 };
711 716
712 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 717 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
713 { .role = "dbclk", .clk = "gpio3_dbclk" }, 718 { .role = "dbclk", .clk = "gpio3_dbclk" },
714 }; 719 };
715 720
716 /* gpio3 */ 721 /* gpio3 */
717 static struct omap_hwmod am33xx_gpio3_hwmod = { 722 static struct omap_hwmod am33xx_gpio3_hwmod = {
718 .name = "gpio4", 723 .name = "gpio4",
719 .class = &am33xx_gpio_hwmod_class, 724 .class = &am33xx_gpio_hwmod_class,
720 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 725 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
721 .mpu_irqs = am33xx_gpio3_irqs, 726 .mpu_irqs = am33xx_gpio3_irqs,
722 .main_clk = "gpio3_ick", 727 .main_clk = "gpio3_ick",
723 .clkdm_name = "l4ls_clkdm", 728 .clkdm_name = "l4ls_clkdm",
724 .prcm = { 729 .prcm = {
725 .omap4 = { 730 .omap4 = {
726 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, 731 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
727 .modulemode = MODULEMODE_SWCTRL, 732 .modulemode = MODULEMODE_SWCTRL,
728 }, 733 },
729 }, 734 },
730 .opt_clks = gpio3_opt_clks, 735 .opt_clks = gpio3_opt_clks,
731 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 736 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
732 .dev_attr = &gpio_dev_attr, 737 .dev_attr = &gpio_dev_attr,
733 .slaves = am33xx_gpio3_slaves, 738 .slaves = am33xx_gpio3_slaves,
734 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves), 739 .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
735 }; 740 };
736 741
737 /* 'gpmc' class */ 742 /* 'gpmc' class */
738 743
739 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { 744 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
740 .name = "gpmc", 745 .name = "gpmc",
741 }; 746 };
742 747
743 /* gpmc */ 748 /* gpmc */
744 static struct omap_hwmod am33xx_gpmc_hwmod = { 749 static struct omap_hwmod am33xx_gpmc_hwmod = {
745 .name = "gpmc", 750 .name = "gpmc",
746 .class = &am33xx_gpmc_hwmod_class, 751 .class = &am33xx_gpmc_hwmod_class,
747 .main_clk = "gpmc_fck", 752 .main_clk = "gpmc_fck",
748 .clkdm_name = "l3s_clkdm", 753 .clkdm_name = "l3s_clkdm",
749 .prcm = { 754 .prcm = {
750 .omap4 = { 755 .omap4 = {
751 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, 756 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
752 .modulemode = MODULEMODE_SWCTRL, 757 .modulemode = MODULEMODE_SWCTRL,
753 }, 758 },
754 }, 759 },
755 }; 760 };
756 761
757 /* 'i2c' class */ 762 /* 'i2c' class */
758 763
759 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { 764 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
760 .sysc_offs = 0x0010, 765 .sysc_offs = 0x0010,
761 .syss_offs = 0x0090, 766 .syss_offs = 0x0090,
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 767 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
763 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 768 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
764 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 769 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
765 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 770 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
766 SIDLE_SMART_WKUP), 771 SIDLE_SMART_WKUP),
767 .sysc_fields = &omap_hwmod_sysc_type1, 772 .sysc_fields = &omap_hwmod_sysc_type1,
768 }; 773 };
769 774
770 static struct omap_i2c_dev_attr i2c_dev_attr = { 775 static struct omap_i2c_dev_attr i2c_dev_attr = {
771 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, 776 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
772 }; 777 };
773 778
774 static struct omap_hwmod_class i2c_class = { 779 static struct omap_hwmod_class i2c_class = {
775 .name = "i2c", 780 .name = "i2c",
776 .sysc = &am33xx_i2c_sysc, 781 .sysc = &am33xx_i2c_sysc,
777 .rev = OMAP_I2C_IP_VERSION_2, 782 .rev = OMAP_I2C_IP_VERSION_2,
778 .reset = &omap_i2c_reset, 783 .reset = &omap_i2c_reset,
779 }; 784 };
780 785
781 /* I2C1 */ 786 /* I2C1 */
782 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { 787 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
783 { .irq = AM33XX_IRQ_MSHSI2COCP0 }, 788 { .irq = AM33XX_IRQ_MSHSI2COCP0 },
784 { .irq = -1 }, 789 { .irq = -1 }
785 }; 790 };
786 791
787 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = { 792 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
788 { .name = "tx", .dma_req = 0, }, 793 { .name = "tx", .dma_req = 0, },
789 { .name = "rx", .dma_req = 0, }, 794 { .name = "rx", .dma_req = 0, },
795 { .dma_req = -1 }
790 }; 796 };
791 797
792 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = { 798 static struct omap_hwmod_ocp_if *am33xx_i2c1_slaves[] = {
793 &am33xx_l4_wkup_i2c1, 799 &am33xx_l4_wkup_i2c1,
794 }; 800 };
795 801
796 static struct omap_hwmod am33xx_i2c1_hwmod = { 802 static struct omap_hwmod am33xx_i2c1_hwmod = {
797 .name = "i2c1", 803 .name = "i2c1",
798 .mpu_irqs = i2c1_mpu_irqs, 804 .mpu_irqs = i2c1_mpu_irqs,
799 .sdma_reqs = i2c1_edma_reqs, 805 .sdma_reqs = i2c1_edma_reqs,
800 .main_clk = "i2c1_fck", 806 .main_clk = "i2c1_fck",
801 .clkdm_name = "l4_wkup_clkdm", 807 .clkdm_name = "l4_wkup_clkdm",
802 .prcm = { 808 .prcm = {
803 .omap4 = { 809 .omap4 = {
804 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, 810 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
805 .modulemode = MODULEMODE_SWCTRL, 811 .modulemode = MODULEMODE_SWCTRL,
806 }, 812 },
807 }, 813 },
808 .flags = HWMOD_16BIT_REG, 814 .flags = HWMOD_16BIT_REG,
809 .dev_attr = &i2c_dev_attr, 815 .dev_attr = &i2c_dev_attr,
810 .slaves = am33xx_i2c1_slaves, 816 .slaves = am33xx_i2c1_slaves,
811 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves), 817 .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
812 .class = &i2c_class, 818 .class = &i2c_class,
813 }; 819 };
814 820
815 /* i2c2 */ 821 /* i2c2 */
816 /* l4 per -> i2c2 */ 822 /* l4 per -> i2c2 */
817 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = { 823 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
818 { 824 {
819 .pa_start = AM33XX_I2C1_BASE, 825 .pa_start = AM33XX_I2C1_BASE,
820 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1, 826 .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
821 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 827 .flags = ADDR_TYPE_RT
822 }, 828 },
829 { }
823 }; 830 };
824 831
825 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = { 832 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
826 .master = &am33xx_l4per_hwmod, 833 .master = &am33xx_l4per_hwmod,
827 .slave = &am33xx_i2c2_hwmod, 834 .slave = &am33xx_i2c2_hwmod,
828 .addr = am33xx_i2c2_addr_space, 835 .addr = am33xx_i2c2_addr_space,
829 .user = OCP_USER_MPU, 836 .user = OCP_USER_MPU,
830 }; 837 };
831 838
832 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { 839 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
833 { .irq = AM33XX_IRQ_MSHSI2COCP1 }, 840 { .irq = AM33XX_IRQ_MSHSI2COCP1 },
834 { .irq = -1 }, 841 { .irq = -1 }
835 }; 842 };
836 843
837 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = { 844 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
838 { .name = "tx", .dma_req = 0, }, 845 { .name = "tx", .dma_req = 0, },
839 { .name = "rx", .dma_req = 0, }, 846 { .name = "rx", .dma_req = 0, },
847 { .dma_req = -1 }
840 }; 848 };
841 849
842 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = { 850 static struct omap_hwmod_ocp_if *am33xx_i2c2_slaves[] = {
843 &am335_l4_per_i2c2, 851 &am335_l4_per_i2c2,
844 }; 852 };
845 853
846 static struct omap_hwmod am33xx_i2c2_hwmod = { 854 static struct omap_hwmod am33xx_i2c2_hwmod = {
847 .name = "i2c2", 855 .name = "i2c2",
848 .mpu_irqs = i2c2_mpu_irqs, 856 .mpu_irqs = i2c2_mpu_irqs,
849 .sdma_reqs = i2c2_edma_reqs, 857 .sdma_reqs = i2c2_edma_reqs,
850 .main_clk = "i2c2_fck", 858 .main_clk = "i2c2_fck",
851 .clkdm_name = "l4ls_clkdm", 859 .clkdm_name = "l4ls_clkdm",
852 .prcm = { 860 .prcm = {
853 .omap4 = { 861 .omap4 = {
854 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, 862 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
855 .modulemode = MODULEMODE_SWCTRL, 863 .modulemode = MODULEMODE_SWCTRL,
856 }, 864 },
857 }, 865 },
858 .flags = HWMOD_16BIT_REG, 866 .flags = HWMOD_16BIT_REG,
859 .dev_attr = &i2c_dev_attr, 867 .dev_attr = &i2c_dev_attr,
860 .slaves = am33xx_i2c2_slaves, 868 .slaves = am33xx_i2c2_slaves,
861 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves), 869 .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
862 .class = &i2c_class, 870 .class = &i2c_class,
863 }; 871 };
864 872
865 /* 'icss' class */ 873 /* 'icss' class */
866 static struct omap_hwmod_class am33xx_icss_hwmod_class = { 874 static struct omap_hwmod_class am33xx_icss_hwmod_class = {
867 .name = "icss", 875 .name = "icss",
868 }; 876 };
869 877
870 /* icss */ 878 /* icss */
871 static struct omap_hwmod am33xx_icss_hwmod = { 879 static struct omap_hwmod am33xx_icss_hwmod = {
872 .name = "icss", 880 .name = "icss",
873 .class = &am33xx_icss_hwmod_class, 881 .class = &am33xx_icss_hwmod_class,
874 .main_clk = "icss_uart_gclk", 882 .main_clk = "icss_uart_gclk",
875 .clkdm_name = "icss_ocp_clkdm", 883 .clkdm_name = "icss_ocp_clkdm",
876 .prcm = { 884 .prcm = {
877 .omap4 = { 885 .omap4 = {
878 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET, 886 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
879 .modulemode = MODULEMODE_SWCTRL, 887 .modulemode = MODULEMODE_SWCTRL,
880 }, 888 },
881 }, 889 },
882 }; 890 };
883 891
884 /* 'ieee5000' class */ 892 /* 'ieee5000' class */
885 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = { 893 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
886 .name = "ieee5000", 894 .name = "ieee5000",
887 }; 895 };
888 896
889 /* ieee5000 */ 897 /* ieee5000 */
890 static struct omap_hwmod am33xx_ieee5000_hwmod = { 898 static struct omap_hwmod am33xx_ieee5000_hwmod = {
891 .name = "ieee5000", 899 .name = "ieee5000",
892 .class = &am33xx_ieee5000_hwmod_class, 900 .class = &am33xx_ieee5000_hwmod_class,
893 .main_clk = "ieee5000_fck", 901 .main_clk = "ieee5000_fck",
894 .clkdm_name = "l3s_clkdm", 902 .clkdm_name = "l3s_clkdm",
895 .prcm = { 903 .prcm = {
896 .omap4 = { 904 .omap4 = {
897 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET, 905 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
898 .modulemode = MODULEMODE_SWCTRL, 906 .modulemode = MODULEMODE_SWCTRL,
899 }, 907 },
900 }, 908 },
901 }; 909 };
902 910
903 911
904 /* 'l3' class */ 912 /* 'l3' class */
905 static struct omap_hwmod_class am33xx_l3_hwmod_class = { 913 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
906 .name = "l3", 914 .name = "l3",
907 }; 915 };
908 916
909 /* l4_hs */ 917 /* l4_hs */
910 static struct omap_hwmod am33xx_l4_hs_hwmod = { 918 static struct omap_hwmod am33xx_l4_hs_hwmod = {
911 .name = "l4_hs", 919 .name = "l4_hs",
912 .class = &am33xx_l3_hwmod_class, 920 .class = &am33xx_l3_hwmod_class,
913 .clkdm_name = "l4hs_clkdm", 921 .clkdm_name = "l4hs_clkdm",
914 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 922 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
915 .prcm = { 923 .prcm = {
916 .omap4 = { 924 .omap4 = {
917 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, 925 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL, 926 .modulemode = MODULEMODE_SWCTRL,
919 }, 927 },
920 }, 928 },
921 }; 929 };
922 930
923 /* l3_instr */ 931 /* l3_instr */
924 static struct omap_hwmod am33xx_l3_instr_hwmod = { 932 static struct omap_hwmod am33xx_l3_instr_hwmod = {
925 .name = "l3_instr", 933 .name = "l3_instr",
926 .class = &am33xx_l3_hwmod_class, 934 .class = &am33xx_l3_hwmod_class,
927 .clkdm_name = "l3_clkdm", 935 .clkdm_name = "l3_clkdm",
928 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 936 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
929 .prcm = { 937 .prcm = {
930 .omap4 = { 938 .omap4 = {
931 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, 939 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
932 .modulemode = MODULEMODE_SWCTRL, 940 .modulemode = MODULEMODE_SWCTRL,
933 }, 941 },
934 }, 942 },
935 }; 943 };
936 944
937 /* l3_main */ 945 /* l3_main */
938 static struct omap_hwmod am33xx_l3_main_hwmod = { 946 static struct omap_hwmod am33xx_l3_main_hwmod = {
939 .name = "l3_main", 947 .name = "l3_main",
940 .class = &am33xx_l3_hwmod_class, 948 .class = &am33xx_l3_hwmod_class,
941 .clkdm_name = "l3_clkdm", 949 .clkdm_name = "l3_clkdm",
942 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 950 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
943 .prcm = { 951 .prcm = {
944 .omap4 = { 952 .omap4 = {
945 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, 953 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
946 .modulemode = MODULEMODE_SWCTRL, 954 .modulemode = MODULEMODE_SWCTRL,
947 }, 955 },
948 }, 956 },
949 }; 957 };
950 958
951 /* 'l4fw' class */ 959 /* 'l4fw' class */
952 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = { 960 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
953 .name = "l4fw", 961 .name = "l4fw",
954 }; 962 };
955 963
956 /* l4fw */ 964 /* l4fw */
957 static struct omap_hwmod am33xx_l4fw_hwmod = { 965 static struct omap_hwmod am33xx_l4fw_hwmod = {
958 .name = "l4fw", 966 .name = "l4fw",
959 .class = &am33xx_l4fw_hwmod_class, 967 .class = &am33xx_l4fw_hwmod_class,
960 .clkdm_name = "l4fw_clkdm", 968 .clkdm_name = "l4fw_clkdm",
961 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 969 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
962 .prcm = { 970 .prcm = {
963 .omap4 = { 971 .omap4 = {
964 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET, 972 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
965 .modulemode = MODULEMODE_SWCTRL, 973 .modulemode = MODULEMODE_SWCTRL,
966 }, 974 },
967 }, 975 },
968 }; 976 };
969 977
970 /* 'l4ls' class */ 978 /* 'l4ls' class */
971 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = { 979 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
972 .name = "l4ls", 980 .name = "l4ls",
973 }; 981 };
974 982
975 /* l4ls */ 983 /* l4ls */
976 static struct omap_hwmod am33xx_l4ls_hwmod = { 984 static struct omap_hwmod am33xx_l4ls_hwmod = {
977 .name = "l4ls", 985 .name = "l4ls",
978 .class = &am33xx_l4ls_hwmod_class, 986 .class = &am33xx_l4ls_hwmod_class,
979 .main_clk = "l4ls_gclk", 987 .main_clk = "l4ls_gclk",
980 .clkdm_name = "l4ls_clkdm", 988 .clkdm_name = "l4ls_clkdm",
981 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 989 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
982 .prcm = { 990 .prcm = {
983 .omap4 = { 991 .omap4 = {
984 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, 992 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
985 .modulemode = MODULEMODE_SWCTRL, 993 .modulemode = MODULEMODE_SWCTRL,
986 }, 994 },
987 }, 995 },
988 }; 996 };
989 997
990 /* 'lcdc' class */ 998 /* 'lcdc' class */
991 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { 999 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
992 .name = "lcdc", 1000 .name = "lcdc",
993 }; 1001 };
994 1002
995 /* lcdc */ 1003 /* lcdc */
996 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = { 1004 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
997 { .irq = AM33XX_IRQ_LCD }, 1005 { .irq = AM33XX_IRQ_LCD },
998 { .irq = -1 }, 1006 { .irq = -1 }
999 }; 1007 };
1000 1008
1001 static struct omap_hwmod am33xx_lcdc_hwmod = { 1009 static struct omap_hwmod am33xx_lcdc_hwmod = {
1002 .name = "lcdc", 1010 .name = "lcdc",
1003 .class = &am33xx_lcdc_hwmod_class, 1011 .class = &am33xx_lcdc_hwmod_class,
1004 .mpu_irqs = am33xx_lcdc_irqs, 1012 .mpu_irqs = am33xx_lcdc_irqs,
1005 .main_clk = "lcdc_fck", 1013 .main_clk = "lcdc_fck",
1006 .clkdm_name = "lcdc_clkdm", 1014 .clkdm_name = "lcdc_clkdm",
1007 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 1015 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1008 .prcm = { 1016 .prcm = {
1009 .omap4 = { 1017 .omap4 = {
1010 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, 1018 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1011 .modulemode = MODULEMODE_SWCTRL, 1019 .modulemode = MODULEMODE_SWCTRL,
1012 }, 1020 },
1013 }, 1021 },
1014 }; 1022 };
1015 1023
1016 /* 'mcasp' class */ 1024 /* 'mcasp' class */
1017 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { 1025 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1018 .name = "mcasp", 1026 .name = "mcasp",
1019 }; 1027 };
1020 1028
1021 /* mcasp0 */ 1029 /* mcasp0 */
1022 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = { 1030 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1023 { .irq = 80 }, 1031 { .irq = 80 },
1024 { .irq = -1 }, 1032 { .irq = -1 }
1025 }; 1033 };
1026 1034
1027 static struct omap_hwmod am33xx_mcasp0_hwmod = { 1035 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1028 .name = "mcasp0", 1036 .name = "mcasp0",
1029 .class = &am33xx_mcasp_hwmod_class, 1037 .class = &am33xx_mcasp_hwmod_class,
1030 .mpu_irqs = am33xx_mcasp0_irqs, 1038 .mpu_irqs = am33xx_mcasp0_irqs,
1031 .main_clk = "mcasp0_fck", 1039 .main_clk = "mcasp0_fck",
1032 .clkdm_name = "l3s_clkdm", 1040 .clkdm_name = "l3s_clkdm",
1033 .prcm = { 1041 .prcm = {
1034 .omap4 = { 1042 .omap4 = {
1035 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, 1043 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1036 .modulemode = MODULEMODE_SWCTRL, 1044 .modulemode = MODULEMODE_SWCTRL,
1037 }, 1045 },
1038 }, 1046 },
1039 }; 1047 };
1040 1048
1041 /* 'mmc' class */ 1049 /* 'mmc' class */
1042 1050
1043 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { 1051 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1044 .rev_offs = 0x1fc, 1052 .rev_offs = 0x1fc,
1045 .sysc_offs = 0x10, 1053 .sysc_offs = 0x10,
1046 .syss_offs = 0x14, 1054 .syss_offs = 0x14,
1047 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1055 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1048 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1056 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1049 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1057 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1050 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1058 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1051 .sysc_fields = &omap_hwmod_sysc_type1, 1059 .sysc_fields = &omap_hwmod_sysc_type1,
1052 }; 1060 };
1053 1061
1054 static struct omap_hwmod_class am33xx_mmc_hwmod_class = { 1062 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1055 .name = "mmc", 1063 .name = "mmc",
1056 .sysc = &am33xx_mmc_sysc, 1064 .sysc = &am33xx_mmc_sysc,
1057 }; 1065 };
1058 1066
1059 /* mmc0 */ 1067 /* mmc0 */
1060 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = { 1068 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1061 { .irq = AM33XX_IRQ_MMCHS0 }, 1069 { .irq = AM33XX_IRQ_MMCHS0 },
1062 { .irq = -1 }, 1070 { .irq = -1 }
1063 }; 1071 };
1064 1072
1065 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = { 1073 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1066 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, }, 1074 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS0_W, },
1067 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, }, 1075 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS0_R, },
1068 { .dma_req = -1 } 1076 { .dma_req = -1 }
1069 }; 1077 };
1070 1078
1071 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { 1079 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
1072 { 1080 {
1073 .pa_start = AM33XX_MMC0_BASE, 1081 .pa_start = AM33XX_MMC0_BASE,
1074 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1, 1082 .pa_end = AM33XX_MMC0_BASE + SZ_4K - 1,
1075 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 1083 .flags = ADDR_TYPE_RT
1076 }, 1084 },
1085 { }
1077 }; 1086 };
1078 1087
1079 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = { 1088 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc0 = {
1080 .master = &am33xx_l4ls_hwmod, 1089 .master = &am33xx_l4ls_hwmod,
1081 .slave = &am33xx_mmc0_hwmod, 1090 .slave = &am33xx_mmc0_hwmod,
1082 .clk = "mmc0_ick", 1091 .clk = "mmc0_ick",
1083 .addr = am33xx_mmc0_addr_space, 1092 .addr = am33xx_mmc0_addr_space,
1084 .user = OCP_USER_MPU, 1093 .user = OCP_USER_MPU,
1085 }; 1094 };
1086 1095
1087 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = { 1096 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1088 &am33xx_l4ls__mmc0, 1097 &am33xx_l4ls__mmc0,
1089 }; 1098 };
1090 1099
1091 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { 1100 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1092 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1101 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1093 }; 1102 };
1094 1103
1095 static struct omap_hwmod am33xx_mmc0_hwmod = { 1104 static struct omap_hwmod am33xx_mmc0_hwmod = {
1096 .name = "mmc1", 1105 .name = "mmc1",
1097 .class = &am33xx_mmc_hwmod_class, 1106 .class = &am33xx_mmc_hwmod_class,
1098 .mpu_irqs = am33xx_mmc0_irqs, 1107 .mpu_irqs = am33xx_mmc0_irqs,
1099 .sdma_reqs = am33xx_mmc0_edma_reqs, 1108 .sdma_reqs = am33xx_mmc0_edma_reqs,
1100 .main_clk = "mmc0_fck", 1109 .main_clk = "mmc0_fck",
1101 .clkdm_name = "l4ls_clkdm", 1110 .clkdm_name = "l4ls_clkdm",
1102 .prcm = { 1111 .prcm = {
1103 .omap4 = { 1112 .omap4 = {
1104 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, 1113 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1105 .modulemode = MODULEMODE_SWCTRL, 1114 .modulemode = MODULEMODE_SWCTRL,
1106 }, 1115 },
1107 }, 1116 },
1108 .dev_attr = &am33xx_mmc0_dev_attr, 1117 .dev_attr = &am33xx_mmc0_dev_attr,
1109 .slaves = am33xx_mmc0_slaves, 1118 .slaves = am33xx_mmc0_slaves,
1110 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves), 1119 .slaves_cnt = ARRAY_SIZE(am33xx_mmc0_slaves),
1111 }; 1120 };
1112 1121
1113 /* mmc1 */ 1122 /* mmc1 */
1114 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = { 1123 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1115 { .irq = AM33XX_IRQ_MMCHS1 }, 1124 { .irq = AM33XX_IRQ_MMCHS1 },
1116 { .irq = -1 }, 1125 { .irq = -1 }
1117 }; 1126 };
1118 1127
1119 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = { 1128 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1120 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, }, 1129 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS1_W, },
1121 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, }, 1130 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS1_R, },
1122 { .dma_req = -1 } 1131 { .dma_req = -1 }
1123 }; 1132 };
1124 1133
1125 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { 1134 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
1126 { 1135 {
1127 .pa_start = AM33XX_MMC1_BASE, 1136 .pa_start = AM33XX_MMC1_BASE,
1128 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1, 1137 .pa_end = AM33XX_MMC1_BASE + SZ_4K - 1,
1129 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 1138 .flags = ADDR_TYPE_RT
1130 }, 1139 },
1140 { }
1131 }; 1141 };
1132 1142
1133 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = { 1143 static struct omap_hwmod_ocp_if am33xx_l4ls__mmc1 = {
1134 .master = &am33xx_l4ls_hwmod, 1144 .master = &am33xx_l4ls_hwmod,
1135 .slave = &am33xx_mmc1_hwmod, 1145 .slave = &am33xx_mmc1_hwmod,
1136 .clk = "mmc1_ick", 1146 .clk = "mmc1_ick",
1137 .addr = am33xx_mmc1_addr_space, 1147 .addr = am33xx_mmc1_addr_space,
1138 .user = OCP_USER_MPU, 1148 .user = OCP_USER_MPU,
1139 }; 1149 };
1140 1150
1141 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = { 1151 static struct omap_hwmod_ocp_if *am33xx_mmc1_slaves[] = {
1142 &am33xx_l4ls__mmc1, 1152 &am33xx_l4ls__mmc1,
1143 }; 1153 };
1144 1154
1145 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { 1155 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1146 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1156 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1147 }; 1157 };
1148 1158
1149 static struct omap_hwmod am33xx_mmc1_hwmod = { 1159 static struct omap_hwmod am33xx_mmc1_hwmod = {
1150 .name = "mmc2", 1160 .name = "mmc2",
1151 .class = &am33xx_mmc_hwmod_class, 1161 .class = &am33xx_mmc_hwmod_class,
1152 .mpu_irqs = am33xx_mmc1_irqs, 1162 .mpu_irqs = am33xx_mmc1_irqs,
1153 .sdma_reqs = am33xx_mmc1_edma_reqs, 1163 .sdma_reqs = am33xx_mmc1_edma_reqs,
1154 .main_clk = "mmc1_fck", 1164 .main_clk = "mmc1_fck",
1155 .clkdm_name = "l4ls_clkdm", 1165 .clkdm_name = "l4ls_clkdm",
1156 .prcm = { 1166 .prcm = {
1157 .omap4 = { 1167 .omap4 = {
1158 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, 1168 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1159 .modulemode = MODULEMODE_SWCTRL, 1169 .modulemode = MODULEMODE_SWCTRL,
1160 }, 1170 },
1161 }, 1171 },
1162 .dev_attr = &am33xx_mmc1_dev_attr, 1172 .dev_attr = &am33xx_mmc1_dev_attr,
1163 .slaves = am33xx_mmc1_slaves, 1173 .slaves = am33xx_mmc1_slaves,
1164 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves), 1174 .slaves_cnt = ARRAY_SIZE(am33xx_mmc1_slaves),
1165 }; 1175 };
1166 1176
1167 /* mmc2 */ 1177 /* mmc2 */
1168 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = { 1178 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1169 { .irq = AM33XX_IRQ_MMCHS2 }, 1179 { .irq = AM33XX_IRQ_MMCHS2 },
1170 { .irq = -1 }, 1180 { .irq = -1 }
1171 }; 1181 };
1172 1182
1173 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = { 1183 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1174 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, }, 1184 { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
1175 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, }, 1185 { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
1176 { .dma_req = -1 } 1186 { .dma_req = -1 }
1177 }; 1187 };
1178 1188
1179 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { 1189 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
1180 { 1190 {
1181 .pa_start = AM33XX_MMC2_BASE, 1191 .pa_start = AM33XX_MMC2_BASE,
1182 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1, 1192 .pa_end = AM33XX_MMC2_BASE + SZ_64K - 1,
1183 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 1193 .flags = ADDR_TYPE_RT
1184 }, 1194 },
1195 { }
1185 }; 1196 };
1186 1197
1187 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = { 1198 static struct omap_hwmod_ocp_if am33xx_l3_main__mmc2 = {
1188 .master = &am33xx_l3_main_hwmod, 1199 .master = &am33xx_l3_main_hwmod,
1189 .slave = &am33xx_mmc2_hwmod, 1200 .slave = &am33xx_mmc2_hwmod,
1190 .clk = "mmc2_ick", 1201 .clk = "mmc2_ick",
1191 .addr = am33xx_mmc2_addr_space, 1202 .addr = am33xx_mmc2_addr_space,
1192 .user = OCP_USER_MPU, 1203 .user = OCP_USER_MPU,
1193 }; 1204 };
1194 1205
1195 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = { 1206 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1196 &am33xx_l3_main__mmc2, 1207 &am33xx_l3_main__mmc2,
1197 }; 1208 };
1198 1209
1199 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { 1210 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1200 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1211 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1201 }; 1212 };
1202 static struct omap_hwmod am33xx_mmc2_hwmod = { 1213 static struct omap_hwmod am33xx_mmc2_hwmod = {
1203 .name = "mmc3", 1214 .name = "mmc3",
1204 .class = &am33xx_mmc_hwmod_class, 1215 .class = &am33xx_mmc_hwmod_class,
1205 .mpu_irqs = am33xx_mmc2_irqs, 1216 .mpu_irqs = am33xx_mmc2_irqs,
1206 .sdma_reqs = am33xx_mmc2_edma_reqs, 1217 .sdma_reqs = am33xx_mmc2_edma_reqs,
1207 .main_clk = "mmc2_fck", 1218 .main_clk = "mmc2_fck",
1208 .clkdm_name = "l3s_clkdm", 1219 .clkdm_name = "l3s_clkdm",
1209 .prcm = { 1220 .prcm = {
1210 .omap4 = { 1221 .omap4 = {
1211 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, 1222 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1212 .modulemode = MODULEMODE_SWCTRL, 1223 .modulemode = MODULEMODE_SWCTRL,
1213 }, 1224 },
1214 }, 1225 },
1215 .dev_attr = &am33xx_mmc2_dev_attr, 1226 .dev_attr = &am33xx_mmc2_dev_attr,
1216 .slaves = am33xx_mmc2_slaves, 1227 .slaves = am33xx_mmc2_slaves,
1217 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves), 1228 .slaves_cnt = ARRAY_SIZE(am33xx_mmc2_slaves),
1218 }; 1229 };
1219 1230
1220 /* Master interfaces on the MPU interconnect */ 1231 /* Master interfaces on the MPU interconnect */
1221 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = { 1232 static struct omap_hwmod_ocp_if *am33xx_l3_mpu_masters[] = {
1222 &am33xx_mpu__l3_slow, 1233 &am33xx_mpu__l3_slow,
1223 }; 1234 };
1224 1235
1225 /* mpu */ 1236 /* mpu */
1226 static struct omap_hwmod am33xx_mpu_hwmod = { 1237 static struct omap_hwmod am33xx_mpu_hwmod = {
1227 .name = "mpu", 1238 .name = "mpu",
1228 .class = &mpu_hwmod_class, 1239 .class = &mpu_hwmod_class,
1229 .masters = am33xx_l3_mpu_masters, 1240 .masters = am33xx_l3_mpu_masters,
1230 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters), 1241 .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1231 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 1242 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1232 .main_clk = "mpu_fck", 1243 .main_clk = "mpu_fck",
1233 .clkdm_name = "mpu_clkdm", 1244 .clkdm_name = "mpu_clkdm",
1234 .prcm = { 1245 .prcm = {
1235 .omap4 = { 1246 .omap4 = {
1236 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, 1247 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1237 .modulemode = MODULEMODE_SWCTRL, 1248 .modulemode = MODULEMODE_SWCTRL,
1238 }, 1249 },
1239 }, 1250 },
1240 }; 1251 };
1241 1252
1242 /* 'ocmcram' class */ 1253 /* 'ocmcram' class */
1243 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { 1254 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
1244 .name = "ocmcram", 1255 .name = "ocmcram",
1245 }; 1256 };
1246 1257
1247 /* ocmcram */ 1258 /* ocmcram */
1248 static struct omap_hwmod am33xx_ocmcram_hwmod = { 1259 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1249 .name = "ocmcram", 1260 .name = "ocmcram",
1250 .class = &am33xx_ocmcram_hwmod_class, 1261 .class = &am33xx_ocmcram_hwmod_class,
1251 .main_clk = "ocmcram_ick", 1262 .main_clk = "ocmcram_ick",
1252 .clkdm_name = "l3_clkdm", 1263 .clkdm_name = "l3_clkdm",
1253 .prcm = { 1264 .prcm = {
1254 .omap4 = { 1265 .omap4 = {
1255 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, 1266 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1256 .modulemode = MODULEMODE_SWCTRL, 1267 .modulemode = MODULEMODE_SWCTRL,
1257 }, 1268 },
1258 }, 1269 },
1259 }; 1270 };
1260 1271
1261 /* 'ocpwp' class */ 1272 /* 'ocpwp' class */
1262 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { 1273 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1263 .name = "ocpwp", 1274 .name = "ocpwp",
1264 }; 1275 };
1265 1276
1266 /* ocpwp */ 1277 /* ocpwp */
1267 static struct omap_hwmod am33xx_ocpwp_hwmod = { 1278 static struct omap_hwmod am33xx_ocpwp_hwmod = {
1268 .name = "ocpwp", 1279 .name = "ocpwp",
1269 .class = &am33xx_ocpwp_hwmod_class, 1280 .class = &am33xx_ocpwp_hwmod_class,
1270 .main_clk = "ocpwp_fck", 1281 .main_clk = "ocpwp_fck",
1271 .clkdm_name = "l4ls_clkdm", 1282 .clkdm_name = "l4ls_clkdm",
1272 .prcm = { 1283 .prcm = {
1273 .omap4 = { 1284 .omap4 = {
1274 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, 1285 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1275 .modulemode = MODULEMODE_SWCTRL, 1286 .modulemode = MODULEMODE_SWCTRL,
1276 }, 1287 },
1277 }, 1288 },
1278 }; 1289 };
1279 1290
1280 /* 'rtc' class */ 1291 /* 'rtc' class */
1281 static struct omap_hwmod_class am33xx_rtc_hwmod_class = { 1292 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1282 .name = "rtc", 1293 .name = "rtc",
1283 }; 1294 };
1284 1295
1285 /* rtc */ 1296 /* rtc */
1286 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = { 1297 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1287 { .irq = AM33XX_IRQ_RTC_TIMER }, 1298 { .irq = AM33XX_IRQ_RTC_TIMER },
1288 { .irq = -1 }, 1299 { .irq = -1 }
1289 }; 1300 };
1290 1301
1291 static struct omap_hwmod am33xx_rtc_hwmod = { 1302 static struct omap_hwmod am33xx_rtc_hwmod = {
1292 .name = "rtc", 1303 .name = "rtc",
1293 .class = &am33xx_rtc_hwmod_class, 1304 .class = &am33xx_rtc_hwmod_class,
1294 .mpu_irqs = am33xx_rtc_irqs, 1305 .mpu_irqs = am33xx_rtc_irqs,
1295 .main_clk = "rtc_fck", 1306 .main_clk = "rtc_fck",
1296 .clkdm_name = "l4_rtc_clkdm", 1307 .clkdm_name = "l4_rtc_clkdm",
1297 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 1308 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1298 .prcm = { 1309 .prcm = {
1299 .omap4 = { 1310 .omap4 = {
1300 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, 1311 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1301 .modulemode = MODULEMODE_SWCTRL, 1312 .modulemode = MODULEMODE_SWCTRL,
1302 }, 1313 },
1303 }, 1314 },
1304 }; 1315 };
1305 1316
1306 /* 'sha0' class */ 1317 /* 'sha0' class */
1307 static struct omap_hwmod_class am33xx_sha0_hwmod_class = { 1318 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1308 .name = "sha0", 1319 .name = "sha0",
1309 }; 1320 };
1310 1321
1311 /* sha0 */ 1322 /* sha0 */
1312 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = { 1323 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1313 { .irq = AM33XX_IRQ_SHAEIP57t0_S }, 1324 { .irq = AM33XX_IRQ_SHAEIP57t0_S },
1314 { .irq = -1 }, 1325 { .irq = -1 }
1315 }; 1326 };
1316 1327
1317 static struct omap_hwmod am33xx_sha0_hwmod = { 1328 static struct omap_hwmod am33xx_sha0_hwmod = {
1318 .name = "sha0", 1329 .name = "sha0",
1319 .class = &am33xx_sha0_hwmod_class, 1330 .class = &am33xx_sha0_hwmod_class,
1320 .mpu_irqs = am33xx_sha0_irqs, 1331 .mpu_irqs = am33xx_sha0_irqs,
1321 .main_clk = "sha0_fck", 1332 .main_clk = "sha0_fck",
1322 .clkdm_name = "l3_clkdm", 1333 .clkdm_name = "l3_clkdm",
1323 .prcm = { 1334 .prcm = {
1324 .omap4 = { 1335 .omap4 = {
1325 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, 1336 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1326 .modulemode = MODULEMODE_SWCTRL, 1337 .modulemode = MODULEMODE_SWCTRL,
1327 }, 1338 },
1328 }, 1339 },
1329 }; 1340 };
1330 1341
1331 /* 'smartreflex' class */ 1342 /* 'smartreflex' class */
1332 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { 1343 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1333 .name = "smartreflex", 1344 .name = "smartreflex",
1334 }; 1345 };
1335 1346
1336 /* smartreflex0 */ 1347 /* smartreflex0 */
1337 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = { 1348 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1338 { .irq = AM33XX_IRQ_SMARTREFLEX0 }, 1349 { .irq = AM33XX_IRQ_SMARTREFLEX0 },
1339 { .irq = -1 }, 1350 { .irq = -1 }
1340 }; 1351 };
1341 1352
1342 static struct omap_hwmod am33xx_smartreflex0_hwmod = { 1353 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1343 .name = "smartreflex0", 1354 .name = "smartreflex0",
1344 .class = &am33xx_smartreflex_hwmod_class, 1355 .class = &am33xx_smartreflex_hwmod_class,
1345 .mpu_irqs = am33xx_smartreflex0_irqs, 1356 .mpu_irqs = am33xx_smartreflex0_irqs,
1346 .main_clk = "smartreflex0_fck", 1357 .main_clk = "smartreflex0_fck",
1347 .clkdm_name = "l4_wkup_clkdm", 1358 .clkdm_name = "l4_wkup_clkdm",
1348 .prcm = { 1359 .prcm = {
1349 .omap4 = { 1360 .omap4 = {
1350 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, 1361 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1351 .modulemode = MODULEMODE_SWCTRL, 1362 .modulemode = MODULEMODE_SWCTRL,
1352 }, 1363 },
1353 }, 1364 },
1354 }; 1365 };
1355 1366
1356 /* smartreflex1 */ 1367 /* smartreflex1 */
1357 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = { 1368 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1358 { .irq = AM33XX_IRQ_SMARTREFLEX1 }, 1369 { .irq = AM33XX_IRQ_SMARTREFLEX1 },
1359 { .irq = -1 }, 1370 { .irq = -1 }
1360 }; 1371 };
1361 1372
1362 static struct omap_hwmod am33xx_smartreflex1_hwmod = { 1373 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1363 .name = "smartreflex1", 1374 .name = "smartreflex1",
1364 .class = &am33xx_smartreflex_hwmod_class, 1375 .class = &am33xx_smartreflex_hwmod_class,
1365 .mpu_irqs = am33xx_smartreflex1_irqs, 1376 .mpu_irqs = am33xx_smartreflex1_irqs,
1366 .main_clk = "smartreflex1_fck", 1377 .main_clk = "smartreflex1_fck",
1367 .clkdm_name = "l4_wkup_clkdm", 1378 .clkdm_name = "l4_wkup_clkdm",
1368 .prcm = { 1379 .prcm = {
1369 .omap4 = { 1380 .omap4 = {
1370 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, 1381 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1371 .modulemode = MODULEMODE_SWCTRL, 1382 .modulemode = MODULEMODE_SWCTRL,
1372 }, 1383 },
1373 }, 1384 },
1374 }; 1385 };
1375 1386
1376 /* 'spi' class */ 1387 /* 'spi' class */
1377 1388
1378 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { 1389 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1379 .rev_offs = 0x0000, 1390 .rev_offs = 0x0000,
1380 .sysc_offs = 0x0110, 1391 .sysc_offs = 0x0110,
1381 .syss_offs = 0x0114, 1392 .syss_offs = 0x0114,
1382 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1393 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1383 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1394 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1384 SYSS_HAS_RESET_STATUS), 1395 SYSS_HAS_RESET_STATUS),
1385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1386 .sysc_fields = &omap_hwmod_sysc_type1, 1397 .sysc_fields = &omap_hwmod_sysc_type1,
1387 }; 1398 };
1388 1399
1389 static struct omap_hwmod_class am33xx_spi_hwmod_class = { 1400 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1390 .name = "mcspi", 1401 .name = "mcspi",
1391 .sysc = &am33xx_mcspi_sysc, 1402 .sysc = &am33xx_mcspi_sysc,
1392 .rev = OMAP4_MCSPI_REV, 1403 .rev = OMAP4_MCSPI_REV,
1393 }; 1404 };
1394 1405
1395 /* spi0 */ 1406 /* spi0 */
1396 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = { 1407 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1397 { .irq = AM33XX_IRQ_MCSPIOCP0 }, 1408 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1398 { .irq = -1 }, 1409 { .irq = -1 }
1399 }; 1410 };
1400 1411
1401 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = { 1412 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
1402 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R }, 1413 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0R },
1403 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W }, 1414 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP0_CH0W },
1404 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R }, 1415 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1R },
1405 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W }, 1416 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP0_CH1W },
1406 { .dma_req = -1 } 1417 { .dma_req = -1 }
1407 }; 1418 };
1408 1419
1409 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = { 1420 struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
1410 { 1421 {
1411 .pa_start = AM33XX_SPI0_BASE, 1422 .pa_start = AM33XX_SPI0_BASE,
1412 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1, 1423 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1413 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 1424 .flags = ADDR_TYPE_RT
1414 }, 1425 },
1415 { }, 1426 { }
1416 }; 1427 };
1417 1428
1418 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = { 1429 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1419 .master = &am33xx_l4per_hwmod, 1430 .master = &am33xx_l4per_hwmod,
1420 .slave = &am33xx_spi0_hwmod, 1431 .slave = &am33xx_spi0_hwmod,
1421 .clk = "spi0_ick", 1432 .clk = "spi0_ick",
1422 .addr = am33xx_mcspi0_addr_space, 1433 .addr = am33xx_mcspi0_addr_space,
1423 .user = OCP_USER_MPU, 1434 .user = OCP_USER_MPU,
1424 }; 1435 };
1425 1436
1426 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = { 1437 static struct omap_hwmod_ocp_if *am33xx_mcspi0_slaves[] = {
1427 &am33xx_l4_core__mcspi0, 1438 &am33xx_l4_core__mcspi0,
1428 }; 1439 };
1429 1440
1430 struct omap2_mcspi_dev_attr mcspi_attrib = { 1441 struct omap2_mcspi_dev_attr mcspi_attrib = {
1431 .num_chipselect = 2, 1442 .num_chipselect = 2,
1432 }; 1443 };
1433 static struct omap_hwmod am33xx_spi0_hwmod = { 1444 static struct omap_hwmod am33xx_spi0_hwmod = {
1434 .name = "spi0", 1445 .name = "spi0",
1435 .class = &am33xx_spi_hwmod_class, 1446 .class = &am33xx_spi_hwmod_class,
1436 .mpu_irqs = am33xx_spi0_irqs, 1447 .mpu_irqs = am33xx_spi0_irqs,
1437 .sdma_reqs = am33xx_mcspi0_sdma_reqs, 1448 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1438 .main_clk = "spi0_fck", 1449 .main_clk = "spi0_fck",
1439 .clkdm_name = "l4ls_clkdm", 1450 .clkdm_name = "l4ls_clkdm",
1440 .prcm = { 1451 .prcm = {
1441 .omap4 = { 1452 .omap4 = {
1442 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, 1453 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1443 .modulemode = MODULEMODE_SWCTRL, 1454 .modulemode = MODULEMODE_SWCTRL,
1444 }, 1455 },
1445 }, 1456 },
1446 .dev_attr = &mcspi_attrib, 1457 .dev_attr = &mcspi_attrib,
1447 .slaves = am33xx_mcspi0_slaves, 1458 .slaves = am33xx_mcspi0_slaves,
1448 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves), 1459 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1449 }; 1460 };
1450 1461
1451 /* spi1 */ 1462 /* spi1 */
1452 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = { 1463 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1453 { .irq = AM33XX_IRQ_SPI1 }, 1464 { .irq = AM33XX_IRQ_SPI1 },
1454 { .irq = -1 }, 1465 { .irq = -1 }
1455 }; 1466 };
1456 1467
1457 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = { 1468 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
1458 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R }, 1469 { .name = "rx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0R },
1459 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W }, 1470 { .name = "tx0", .dma_req = AM33XX_DMA_SPIOCP1_CH0W },
1460 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R }, 1471 { .name = "rx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1R },
1461 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W }, 1472 { .name = "tx1", .dma_req = AM33XX_DMA_SPIOCP1_CH1W },
1462 { .dma_req = -1 } 1473 { .dma_req = -1 }
1463 }; 1474 };
1464 1475
1465 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = { 1476 struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
1466 { 1477 {
1467 .pa_start = AM33XX_SPI1_BASE, 1478 .pa_start = AM33XX_SPI1_BASE,
1468 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1, 1479 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1469 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 1480 .flags = ADDR_TYPE_RT
1470 }, 1481 },
1471 { }, 1482 { }
1472 }; 1483 };
1473 1484
1474 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = { 1485 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1475 .master = &am33xx_l4per_hwmod, 1486 .master = &am33xx_l4per_hwmod,
1476 .slave = &am33xx_spi1_hwmod, 1487 .slave = &am33xx_spi1_hwmod,
1477 .clk = "spi1_ick", 1488 .clk = "spi1_ick",
1478 .addr = am33xx_mcspi1_addr_space, 1489 .addr = am33xx_mcspi1_addr_space,
1479 .user = OCP_USER_MPU, 1490 .user = OCP_USER_MPU,
1480 }; 1491 };
1481 1492
1482 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = { 1493 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1483 &am33xx_l4_core__mcspi1, 1494 &am33xx_l4_core__mcspi1,
1484 }; 1495 };
1485 static struct omap_hwmod am33xx_spi1_hwmod = { 1496 static struct omap_hwmod am33xx_spi1_hwmod = {
1486 .name = "spi1", 1497 .name = "spi1",
1487 .class = &am33xx_spi_hwmod_class, 1498 .class = &am33xx_spi_hwmod_class,
1488 .mpu_irqs = am33xx_spi1_irqs, 1499 .mpu_irqs = am33xx_spi1_irqs,
1489 .sdma_reqs = am33xx_mcspi1_sdma_reqs, 1500 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1490 .main_clk = "spi1_fck", 1501 .main_clk = "spi1_fck",
1491 .clkdm_name = "l4ls_clkdm", 1502 .clkdm_name = "l4ls_clkdm",
1492 .prcm = { 1503 .prcm = {
1493 .omap4 = { 1504 .omap4 = {
1494 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, 1505 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1495 .modulemode = MODULEMODE_SWCTRL, 1506 .modulemode = MODULEMODE_SWCTRL,
1496 }, 1507 },
1497 }, 1508 },
1498 .dev_attr = &mcspi_attrib, 1509 .dev_attr = &mcspi_attrib,
1499 .slaves = am33xx_mcspi1_slaves, 1510 .slaves = am33xx_mcspi1_slaves,
1500 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves), 1511 .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1501 }; 1512 };
1502 1513
1503 /* 'spinlock' class */ 1514 /* 'spinlock' class */
1504 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { 1515 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1505 .name = "spinlock", 1516 .name = "spinlock",
1506 }; 1517 };
1507 1518
1508 /* spinlock */ 1519 /* spinlock */
1509 static struct omap_hwmod am33xx_spinlock_hwmod = { 1520 static struct omap_hwmod am33xx_spinlock_hwmod = {
1510 .name = "spinlock", 1521 .name = "spinlock",
1511 .class = &am33xx_spinlock_hwmod_class, 1522 .class = &am33xx_spinlock_hwmod_class,
1512 .main_clk = "spinlock_fck", 1523 .main_clk = "spinlock_fck",
1513 .clkdm_name = "l4ls_clkdm", 1524 .clkdm_name = "l4ls_clkdm",
1514 .prcm = { 1525 .prcm = {
1515 .omap4 = { 1526 .omap4 = {
1516 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, 1527 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL, 1528 .modulemode = MODULEMODE_SWCTRL,
1518 }, 1529 },
1519 }, 1530 },
1520 }; 1531 };
1521 1532
1522 /* 'timer 0 & 2-7' class */ 1533 /* 'timer 0 & 2-7' class */
1523 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { 1534 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1524 .rev_offs = 0x0000, 1535 .rev_offs = 0x0000,
1525 .sysc_offs = 0x0010, 1536 .sysc_offs = 0x0010,
1526 .syss_offs = 0x0014, 1537 .syss_offs = 0x0014,
1527 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1538 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1528 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1539 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1529 SIDLE_SMART_WKUP), 1540 SIDLE_SMART_WKUP),
1530 .sysc_fields = &omap_hwmod_sysc_type2, 1541 .sysc_fields = &omap_hwmod_sysc_type2,
1531 }; 1542 };
1532 1543
1533 static struct omap_hwmod_class am33xx_timer_hwmod_class = { 1544 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1534 .name = "timer", 1545 .name = "timer",
1535 .sysc = &am33xx_timer_sysc, 1546 .sysc = &am33xx_timer_sysc,
1536 }; 1547 };
1537 1548
1538 /* timer0 */ 1549 /* timer0 */
1539 /* l4 wkup -> timer0 interface */ 1550 /* l4 wkup -> timer0 interface */
1540 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = { 1551 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1541 { 1552 {
1542 .pa_start = AM33XX_TIMER0_BASE, 1553 .pa_start = AM33XX_TIMER0_BASE,
1543 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1, 1554 .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1544 .flags = ADDR_TYPE_RT 1555 .flags = ADDR_TYPE_RT
1545 }, 1556 },
1546 { }, 1557 { }
1547 }; 1558 };
1548 1559
1549 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = { 1560 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1550 .master = &am33xx_l4wkup_hwmod, 1561 .master = &am33xx_l4wkup_hwmod,
1551 .slave = &am33xx_timer0_hwmod, 1562 .slave = &am33xx_timer0_hwmod,
1552 .clk = "timer0_ick", 1563 .clk = "timer0_ick",
1553 .addr = am33xx_timer0_addr_space, 1564 .addr = am33xx_timer0_addr_space,
1554 .user = OCP_USER_MPU, 1565 .user = OCP_USER_MPU,
1555 }; 1566 };
1556 1567
1557 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = { 1568 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1558 &am33xx_l4wkup__timer0, 1569 &am33xx_l4wkup__timer0,
1559 }; 1570 };
1560 1571
1561 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = { 1572 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1562 { .irq = AM33XX_IRQ_DMTIMER0 }, 1573 { .irq = AM33XX_IRQ_DMTIMER0 },
1563 { .irq = -1 }, 1574 { .irq = -1 }
1564 }; 1575 };
1565 1576
1566 static struct omap_hwmod am33xx_timer0_hwmod = { 1577 static struct omap_hwmod am33xx_timer0_hwmod = {
1567 .name = "timer0", 1578 .name = "timer0",
1568 .class = &am33xx_timer_hwmod_class, 1579 .class = &am33xx_timer_hwmod_class,
1569 .mpu_irqs = am33xx_timer0_irqs, 1580 .mpu_irqs = am33xx_timer0_irqs,
1570 .main_clk = "timer0_fck", 1581 .main_clk = "timer0_fck",
1571 .clkdm_name = "l4_wkup_clkdm", 1582 .clkdm_name = "l4_wkup_clkdm",
1572 .prcm = { 1583 .prcm = {
1573 .omap4 = { 1584 .omap4 = {
1574 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET, 1585 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1575 .modulemode = MODULEMODE_SWCTRL, 1586 .modulemode = MODULEMODE_SWCTRL,
1576 }, 1587 },
1577 }, 1588 },
1578 .slaves = am33xx_timer0_slaves, 1589 .slaves = am33xx_timer0_slaves,
1579 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves), 1590 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1580 }; 1591 };
1581 1592
1582 /* timer1 1ms */ 1593 /* timer1 1ms */
1583 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { 1594 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1584 .rev_offs = 0x0000, 1595 .rev_offs = 0x0000,
1585 .sysc_offs = 0x0010, 1596 .sysc_offs = 0x0010,
1586 .syss_offs = 0x0014, 1597 .syss_offs = 0x0014,
1587 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1598 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1588 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1599 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1589 SYSS_HAS_RESET_STATUS), 1600 SYSS_HAS_RESET_STATUS),
1590 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1601 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1591 .sysc_fields = &omap_hwmod_sysc_type1, 1602 .sysc_fields = &omap_hwmod_sysc_type1,
1592 }; 1603 };
1593 1604
1594 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { 1605 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1595 .name = "timer", 1606 .name = "timer",
1596 .sysc = &am33xx_timer1ms_sysc, 1607 .sysc = &am33xx_timer1ms_sysc,
1597 }; 1608 };
1598 1609
1599 /* l4 wkup -> timer1 interface */ 1610 /* l4 wkup -> timer1 interface */
1600 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = { 1611 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1601 { 1612 {
1602 .pa_start = AM33XX_TIMER1_BASE, 1613 .pa_start = AM33XX_TIMER1_BASE,
1603 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1, 1614 .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1604 .flags = ADDR_TYPE_RT 1615 .flags = ADDR_TYPE_RT
1605 }, 1616 },
1606 { }, 1617 { }
1607 }; 1618 };
1608 1619
1609 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = { 1620 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1610 .master = &am33xx_l4wkup_hwmod, 1621 .master = &am33xx_l4wkup_hwmod,
1611 .slave = &am33xx_timer1_hwmod, 1622 .slave = &am33xx_timer1_hwmod,
1612 .clk = "timer1_ick", 1623 .clk = "timer1_ick",
1613 .addr = am33xx_timer1_addr_space, 1624 .addr = am33xx_timer1_addr_space,
1614 .user = OCP_USER_MPU, 1625 .user = OCP_USER_MPU,
1615 }; 1626 };
1616 1627
1617 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = { 1628 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1618 &am33xx_l4wkup__timer1, 1629 &am33xx_l4wkup__timer1,
1619 }; 1630 };
1620 1631
1621 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = { 1632 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1622 { .irq = AM33XX_IRQ_DMTIMER1 }, 1633 { .irq = AM33XX_IRQ_DMTIMER1 },
1623 { .irq = -1 }, 1634 { .irq = -1 }
1624 }; 1635 };
1625 1636
1626 static struct omap_hwmod am33xx_timer1_hwmod = { 1637 static struct omap_hwmod am33xx_timer1_hwmod = {
1627 .name = "timer1", 1638 .name = "timer1",
1628 .class = &am33xx_timer1ms_hwmod_class, 1639 .class = &am33xx_timer1ms_hwmod_class,
1629 .mpu_irqs = am33xx_timer1_irqs, 1640 .mpu_irqs = am33xx_timer1_irqs,
1630 .main_clk = "timer1_fck", 1641 .main_clk = "timer1_fck",
1631 .clkdm_name = "l4_wkup_clkdm", 1642 .clkdm_name = "l4_wkup_clkdm",
1632 .prcm = { 1643 .prcm = {
1633 .omap4 = { 1644 .omap4 = {
1634 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, 1645 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1635 .modulemode = MODULEMODE_SWCTRL, 1646 .modulemode = MODULEMODE_SWCTRL,
1636 }, 1647 },
1637 }, 1648 },
1638 .slaves = am33xx_timer1_slaves, 1649 .slaves = am33xx_timer1_slaves,
1639 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves), 1650 .slaves_cnt = ARRAY_SIZE(am33xx_timer1_slaves),
1640 }; 1651 };
1641 1652
1642 /* timer2 */ 1653 /* timer2 */
1643 /* l4 per -> timer2 interface */ 1654 /* l4 per -> timer2 interface */
1644 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = { 1655 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1645 { 1656 {
1646 .pa_start = AM33XX_TIMER2_BASE, 1657 .pa_start = AM33XX_TIMER2_BASE,
1647 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1, 1658 .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1648 .flags = ADDR_TYPE_RT 1659 .flags = ADDR_TYPE_RT
1649 }, 1660 },
1650 { }, 1661 { }
1651 }; 1662 };
1652 1663
1653 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = { 1664 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1654 .master = &am33xx_l4per_hwmod, 1665 .master = &am33xx_l4per_hwmod,
1655 .slave = &am33xx_timer2_hwmod, 1666 .slave = &am33xx_timer2_hwmod,
1656 .clk = "timer2_ick", 1667 .clk = "timer2_ick",
1657 .addr = am33xx_timer2_addr_space, 1668 .addr = am33xx_timer2_addr_space,
1658 .user = OCP_USER_MPU, 1669 .user = OCP_USER_MPU,
1659 }; 1670 };
1660 1671
1661 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = { 1672 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1662 &am33xx_l4per__timer2, 1673 &am33xx_l4per__timer2,
1663 }; 1674 };
1664 1675
1665 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = { 1676 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1666 { .irq = AM33XX_IRQ_DMTIMER2 }, 1677 { .irq = AM33XX_IRQ_DMTIMER2 },
1667 { .irq = -1 }, 1678 { .irq = -1 }
1668 }; 1679 };
1669 1680
1670 static struct omap_hwmod am33xx_timer2_hwmod = { 1681 static struct omap_hwmod am33xx_timer2_hwmod = {
1671 .name = "timer2", 1682 .name = "timer2",
1672 .class = &am33xx_timer_hwmod_class, 1683 .class = &am33xx_timer_hwmod_class,
1673 .mpu_irqs = am33xx_timer2_irqs, 1684 .mpu_irqs = am33xx_timer2_irqs,
1674 .main_clk = "timer2_fck", 1685 .main_clk = "timer2_fck",
1675 .prcm = { 1686 .prcm = {
1676 .omap4 = { 1687 .omap4 = {
1677 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, 1688 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1678 .modulemode = MODULEMODE_SWCTRL, 1689 .modulemode = MODULEMODE_SWCTRL,
1679 }, 1690 },
1680 }, 1691 },
1681 .slaves = am33xx_timer2_slaves, 1692 .slaves = am33xx_timer2_slaves,
1682 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves), 1693 .slaves_cnt = ARRAY_SIZE(am33xx_timer2_slaves),
1683 .clkdm_name = "l4ls_clkdm", 1694 .clkdm_name = "l4ls_clkdm",
1684 }; 1695 };
1685 1696
1686 /* timer3 */ 1697 /* timer3 */
1687 /* l4 per -> timer3 interface */ 1698 /* l4 per -> timer3 interface */
1688 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = { 1699 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1689 { 1700 {
1690 .pa_start = AM33XX_TIMER3_BASE, 1701 .pa_start = AM33XX_TIMER3_BASE,
1691 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1, 1702 .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1692 .flags = ADDR_TYPE_RT 1703 .flags = ADDR_TYPE_RT
1693 }, 1704 },
1694 { }, 1705 { }
1695 }; 1706 };
1696 1707
1697 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = { 1708 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1698 .master = &am33xx_l4per_hwmod, 1709 .master = &am33xx_l4per_hwmod,
1699 .slave = &am33xx_timer3_hwmod, 1710 .slave = &am33xx_timer3_hwmod,
1700 .clk = "timer3_ick", 1711 .clk = "timer3_ick",
1701 .addr = am33xx_timer3_addr_space, 1712 .addr = am33xx_timer3_addr_space,
1702 .user = OCP_USER_MPU, 1713 .user = OCP_USER_MPU,
1703 }; 1714 };
1704 1715
1705 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = { 1716 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1706 &am33xx_l4per__timer3, 1717 &am33xx_l4per__timer3,
1707 }; 1718 };
1708 1719
1709 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = { 1720 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1710 { .irq = AM33XX_IRQ_DMTIMER3 }, 1721 { .irq = AM33XX_IRQ_DMTIMER3 },
1711 { .irq = -1 }, 1722 { .irq = -1 }
1712 }; 1723 };
1713 1724
1714 static struct omap_hwmod am33xx_timer3_hwmod = { 1725 static struct omap_hwmod am33xx_timer3_hwmod = {
1715 .name = "timer3", 1726 .name = "timer3",
1716 .class = &am33xx_timer_hwmod_class, 1727 .class = &am33xx_timer_hwmod_class,
1717 .mpu_irqs = am33xx_timer3_irqs, 1728 .mpu_irqs = am33xx_timer3_irqs,
1718 .main_clk = "timer3_fck", 1729 .main_clk = "timer3_fck",
1719 .clkdm_name = "l4ls_clkdm", 1730 .clkdm_name = "l4ls_clkdm",
1720 .prcm = { 1731 .prcm = {
1721 .omap4 = { 1732 .omap4 = {
1722 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, 1733 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1723 .modulemode = MODULEMODE_SWCTRL, 1734 .modulemode = MODULEMODE_SWCTRL,
1724 }, 1735 },
1725 }, 1736 },
1726 .slaves = am33xx_timer3_slaves, 1737 .slaves = am33xx_timer3_slaves,
1727 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves), 1738 .slaves_cnt = ARRAY_SIZE(am33xx_timer3_slaves),
1728 }; 1739 };
1729 1740
1730 /* timer4 */ 1741 /* timer4 */
1731 /* l4 per -> timer4 interface */ 1742 /* l4 per -> timer4 interface */
1732 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = { 1743 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1733 { 1744 {
1734 .pa_start = AM33XX_TIMER4_BASE, 1745 .pa_start = AM33XX_TIMER4_BASE,
1735 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1, 1746 .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1736 .flags = ADDR_TYPE_RT 1747 .flags = ADDR_TYPE_RT
1737 }, 1748 },
1738 { }, 1749 { }
1739 }; 1750 };
1740 1751
1741 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = { 1752 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1742 .master = &am33xx_l4per_hwmod, 1753 .master = &am33xx_l4per_hwmod,
1743 .slave = &am33xx_timer4_hwmod, 1754 .slave = &am33xx_timer4_hwmod,
1744 .clk = "timer4_ick", 1755 .clk = "timer4_ick",
1745 .addr = am33xx_timer4_addr_space, 1756 .addr = am33xx_timer4_addr_space,
1746 .user = OCP_USER_MPU, 1757 .user = OCP_USER_MPU,
1747 }; 1758 };
1748 1759
1749 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = { 1760 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1750 &am33xx_l4per__timer4, 1761 &am33xx_l4per__timer4,
1751 }; 1762 };
1752 1763
1753 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = { 1764 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1754 { .irq = AM33XX_IRQ_DMTIMER4 }, 1765 { .irq = AM33XX_IRQ_DMTIMER4 },
1755 { .irq = -1 }, 1766 { .irq = -1 }
1756 }; 1767 };
1757 1768
1758 static struct omap_hwmod am33xx_timer4_hwmod = { 1769 static struct omap_hwmod am33xx_timer4_hwmod = {
1759 .name = "timer4", 1770 .name = "timer4",
1760 .class = &am33xx_timer_hwmod_class, 1771 .class = &am33xx_timer_hwmod_class,
1761 .mpu_irqs = am33xx_timer4_irqs, 1772 .mpu_irqs = am33xx_timer4_irqs,
1762 .main_clk = "timer4_fck", 1773 .main_clk = "timer4_fck",
1763 .prcm = { 1774 .prcm = {
1764 .omap4 = { 1775 .omap4 = {
1765 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, 1776 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1766 .modulemode = MODULEMODE_SWCTRL, 1777 .modulemode = MODULEMODE_SWCTRL,
1767 }, 1778 },
1768 }, 1779 },
1769 .slaves = am33xx_timer4_slaves, 1780 .slaves = am33xx_timer4_slaves,
1770 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves), 1781 .slaves_cnt = ARRAY_SIZE(am33xx_timer4_slaves),
1771 .clkdm_name = "l4ls_clkdm", 1782 .clkdm_name = "l4ls_clkdm",
1772 }; 1783 };
1773 1784
1774 1785
1775 /* timer5 */ 1786 /* timer5 */
1776 /* l4 per -> timer5 interface */ 1787 /* l4 per -> timer5 interface */
1777 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = { 1788 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1778 { 1789 {
1779 .pa_start = AM33XX_TIMER5_BASE, 1790 .pa_start = AM33XX_TIMER5_BASE,
1780 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1, 1791 .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1781 .flags = ADDR_TYPE_RT 1792 .flags = ADDR_TYPE_RT
1782 }, 1793 },
1783 { }, 1794 { }
1784 }; 1795 };
1785 1796
1786 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = { 1797 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1787 .master = &am33xx_l4per_hwmod, 1798 .master = &am33xx_l4per_hwmod,
1788 .slave = &am33xx_timer5_hwmod, 1799 .slave = &am33xx_timer5_hwmod,
1789 .clk = "timer5_ick", 1800 .clk = "timer5_ick",
1790 .addr = am33xx_timer5_addr_space, 1801 .addr = am33xx_timer5_addr_space,
1791 .user = OCP_USER_MPU, 1802 .user = OCP_USER_MPU,
1792 }; 1803 };
1793 1804
1794 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = { 1805 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1795 &am33xx_l4per__timer5, 1806 &am33xx_l4per__timer5,
1796 }; 1807 };
1797 1808
1798 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = { 1809 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1799 { .irq = AM33XX_IRQ_DMTIMER5 }, 1810 { .irq = AM33XX_IRQ_DMTIMER5 },
1800 { .irq = -1 }, 1811 { .irq = -1 }
1801 }; 1812 };
1802 1813
1803 static struct omap_hwmod am33xx_timer5_hwmod = { 1814 static struct omap_hwmod am33xx_timer5_hwmod = {
1804 .name = "timer5", 1815 .name = "timer5",
1805 .class = &am33xx_timer_hwmod_class, 1816 .class = &am33xx_timer_hwmod_class,
1806 .mpu_irqs = am33xx_timer5_irqs, 1817 .mpu_irqs = am33xx_timer5_irqs,
1807 .main_clk = "timer5_fck", 1818 .main_clk = "timer5_fck",
1808 .prcm = { 1819 .prcm = {
1809 .omap4 = { 1820 .omap4 = {
1810 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, 1821 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1811 .modulemode = MODULEMODE_SWCTRL, 1822 .modulemode = MODULEMODE_SWCTRL,
1812 }, 1823 },
1813 }, 1824 },
1814 .slaves = am33xx_timer5_slaves, 1825 .slaves = am33xx_timer5_slaves,
1815 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves), 1826 .slaves_cnt = ARRAY_SIZE(am33xx_timer5_slaves),
1816 .clkdm_name = "l4ls_clkdm", 1827 .clkdm_name = "l4ls_clkdm",
1817 }; 1828 };
1818 1829
1819 /* timer6 */ 1830 /* timer6 */
1820 /* l4 per -> timer6 interface */ 1831 /* l4 per -> timer6 interface */
1821 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = { 1832 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1822 { 1833 {
1823 .pa_start = AM33XX_TIMER6_BASE, 1834 .pa_start = AM33XX_TIMER6_BASE,
1824 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1, 1835 .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
1825 .flags = ADDR_TYPE_RT 1836 .flags = ADDR_TYPE_RT
1826 }, 1837 },
1827 { }, 1838 { }
1828 }; 1839 };
1829 1840
1830 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = { 1841 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1831 .master = &am33xx_l4per_hwmod, 1842 .master = &am33xx_l4per_hwmod,
1832 .slave = &am33xx_timer6_hwmod, 1843 .slave = &am33xx_timer6_hwmod,
1833 .clk = "timer6_ick", 1844 .clk = "timer6_ick",
1834 .addr = am33xx_timer6_addr_space, 1845 .addr = am33xx_timer6_addr_space,
1835 .user = OCP_USER_MPU, 1846 .user = OCP_USER_MPU,
1836 }; 1847 };
1837 1848
1838 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = { 1849 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1839 &am33xx_l4per__timer6, 1850 &am33xx_l4per__timer6,
1840 }; 1851 };
1841 1852
1842 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = { 1853 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1843 { .irq = AM33XX_IRQ_DMTIMER6 }, 1854 { .irq = AM33XX_IRQ_DMTIMER6 },
1844 { .irq = -1 }, 1855 { .irq = -1 }
1845 }; 1856 };
1846 1857
1847 static struct omap_hwmod am33xx_timer6_hwmod = { 1858 static struct omap_hwmod am33xx_timer6_hwmod = {
1848 .name = "timer6", 1859 .name = "timer6",
1849 .class = &am33xx_timer_hwmod_class, 1860 .class = &am33xx_timer_hwmod_class,
1850 .mpu_irqs = am33xx_timer6_irqs, 1861 .mpu_irqs = am33xx_timer6_irqs,
1851 .main_clk = "timer6_fck", 1862 .main_clk = "timer6_fck",
1852 .prcm = { 1863 .prcm = {
1853 .omap4 = { 1864 .omap4 = {
1854 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, 1865 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1855 .modulemode = MODULEMODE_SWCTRL, 1866 .modulemode = MODULEMODE_SWCTRL,
1856 }, 1867 },
1857 }, 1868 },
1858 .slaves = am33xx_timer6_slaves, 1869 .slaves = am33xx_timer6_slaves,
1859 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves), 1870 .slaves_cnt = ARRAY_SIZE(am33xx_timer6_slaves),
1860 .clkdm_name = "l4ls_clkdm", 1871 .clkdm_name = "l4ls_clkdm",
1861 }; 1872 };
1862 1873
1863 /* timer7 */ 1874 /* timer7 */
1864 /* l4 per -> timer7 interface */ 1875 /* l4 per -> timer7 interface */
1865 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = { 1876 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1866 { 1877 {
1867 .pa_start = AM33XX_TIMER7_BASE, 1878 .pa_start = AM33XX_TIMER7_BASE,
1868 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1, 1879 .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
1869 .flags = ADDR_TYPE_RT 1880 .flags = ADDR_TYPE_RT
1870 }, 1881 },
1871 { }, 1882 { }
1872 }; 1883 };
1873 1884
1874 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = { 1885 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1875 .master = &am33xx_l4per_hwmod, 1886 .master = &am33xx_l4per_hwmod,
1876 .slave = &am33xx_timer7_hwmod, 1887 .slave = &am33xx_timer7_hwmod,
1877 .clk = "timer7_ick", 1888 .clk = "timer7_ick",
1878 .addr = am33xx_timer7_addr_space, 1889 .addr = am33xx_timer7_addr_space,
1879 .user = OCP_USER_MPU, 1890 .user = OCP_USER_MPU,
1880 }; 1891 };
1881 1892
1882 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = { 1893 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1883 &am33xx_l4per__timer7, 1894 &am33xx_l4per__timer7,
1884 }; 1895 };
1885 1896
1886 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = { 1897 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1887 { .irq = AM33XX_IRQ_DMTIMER7 }, 1898 { .irq = AM33XX_IRQ_DMTIMER7 },
1888 { .irq = -1 }, 1899 { .irq = -1 }
1889 }; 1900 };
1890 1901
1891 static struct omap_hwmod am33xx_timer7_hwmod = { 1902 static struct omap_hwmod am33xx_timer7_hwmod = {
1892 .name = "timer7", 1903 .name = "timer7",
1893 .class = &am33xx_timer_hwmod_class, 1904 .class = &am33xx_timer_hwmod_class,
1894 .mpu_irqs = am33xx_timer7_irqs, 1905 .mpu_irqs = am33xx_timer7_irqs,
1895 .main_clk = "timer7_fck", 1906 .main_clk = "timer7_fck",
1896 .prcm = { 1907 .prcm = {
1897 .omap4 = { 1908 .omap4 = {
1898 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, 1909 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1899 .modulemode = MODULEMODE_SWCTRL, 1910 .modulemode = MODULEMODE_SWCTRL,
1900 }, 1911 },
1901 }, 1912 },
1902 .slaves = am33xx_timer7_slaves, 1913 .slaves = am33xx_timer7_slaves,
1903 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves), 1914 .slaves_cnt = ARRAY_SIZE(am33xx_timer7_slaves),
1904 .clkdm_name = "l4ls_clkdm", 1915 .clkdm_name = "l4ls_clkdm",
1905 }; 1916 };
1906 1917
1907 /* 'tpcc' class */ 1918 /* 'tpcc' class */
1908 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { 1919 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1909 .name = "tpcc", 1920 .name = "tpcc",
1910 }; 1921 };
1911 1922
1912 /* tpcc */ 1923 /* tpcc */
1913 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = { 1924 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1914 { .irq = AM33XX_IRQ_TPCC0_INT_PO0 }, 1925 { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
1915 { .irq = -1 }, 1926 { .irq = -1 },
1916 }; 1927 };
1917 1928
1918 static struct omap_hwmod am33xx_tpcc_hwmod = { 1929 static struct omap_hwmod am33xx_tpcc_hwmod = {
1919 .name = "tpcc", 1930 .name = "tpcc",
1920 .class = &am33xx_tpcc_hwmod_class, 1931 .class = &am33xx_tpcc_hwmod_class,
1921 .mpu_irqs = am33xx_tpcc_irqs, 1932 .mpu_irqs = am33xx_tpcc_irqs,
1922 .main_clk = "tpcc_ick", 1933 .main_clk = "tpcc_ick",
1923 .clkdm_name = "l3_clkdm", 1934 .clkdm_name = "l3_clkdm",
1924 .prcm = { 1935 .prcm = {
1925 .omap4 = { 1936 .omap4 = {
1926 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, 1937 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1927 .modulemode = MODULEMODE_SWCTRL, 1938 .modulemode = MODULEMODE_SWCTRL,
1928 }, 1939 },
1929 }, 1940 },
1930 }; 1941 };
1931 1942
1932 /* 'tptc' class */ 1943 /* 'tptc' class */
1933 static struct omap_hwmod_class am33xx_tptc_hwmod_class = { 1944 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1934 .name = "tptc", 1945 .name = "tptc",
1935 }; 1946 };
1936 1947
1937 /* tptc0 */ 1948 /* tptc0 */
1938 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = { 1949 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1939 { .irq = AM33XX_IRQ_TPTC0 }, 1950 { .irq = AM33XX_IRQ_TPTC0 },
1940 { .irq = -1 }, 1951 { .irq = -1 }
1941 }; 1952 };
1942 1953
1943 static struct omap_hwmod am33xx_tptc0_hwmod = { 1954 static struct omap_hwmod am33xx_tptc0_hwmod = {
1944 .name = "tptc0", 1955 .name = "tptc0",
1945 .class = &am33xx_tptc_hwmod_class, 1956 .class = &am33xx_tptc_hwmod_class,
1946 .mpu_irqs = am33xx_tptc0_irqs, 1957 .mpu_irqs = am33xx_tptc0_irqs,
1947 .main_clk = "tptc0_ick", 1958 .main_clk = "tptc0_ick",
1948 .clkdm_name = "l3_clkdm", 1959 .clkdm_name = "l3_clkdm",
1949 .prcm = { 1960 .prcm = {
1950 .omap4 = { 1961 .omap4 = {
1951 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, 1962 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1952 .modulemode = MODULEMODE_SWCTRL, 1963 .modulemode = MODULEMODE_SWCTRL,
1953 }, 1964 },
1954 }, 1965 },
1955 }; 1966 };
1956 1967
1957 /* tptc1 */ 1968 /* tptc1 */
1958 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = { 1969 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1959 { .irq = AM33XX_IRQ_TPTC1 }, 1970 { .irq = AM33XX_IRQ_TPTC1 },
1960 { .irq = -1 }, 1971 { .irq = -1 }
1961 }; 1972 };
1962 1973
1963 static struct omap_hwmod am33xx_tptc1_hwmod = { 1974 static struct omap_hwmod am33xx_tptc1_hwmod = {
1964 .name = "tptc1", 1975 .name = "tptc1",
1965 .class = &am33xx_tptc_hwmod_class, 1976 .class = &am33xx_tptc_hwmod_class,
1966 .mpu_irqs = am33xx_tptc1_irqs, 1977 .mpu_irqs = am33xx_tptc1_irqs,
1967 .main_clk = "tptc1_ick", 1978 .main_clk = "tptc1_ick",
1968 .clkdm_name = "l3_clkdm", 1979 .clkdm_name = "l3_clkdm",
1969 .prcm = { 1980 .prcm = {
1970 .omap4 = { 1981 .omap4 = {
1971 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, 1982 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1972 .modulemode = MODULEMODE_SWCTRL, 1983 .modulemode = MODULEMODE_SWCTRL,
1973 }, 1984 },
1974 }, 1985 },
1975 }; 1986 };
1976 1987
1977 /* tptc2 */ 1988 /* tptc2 */
1978 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = { 1989 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1979 { .irq = AM33XX_IRQ_TPTC2 }, 1990 { .irq = AM33XX_IRQ_TPTC2 },
1980 { .irq = -1 }, 1991 { .irq = -1 }
1981 }; 1992 };
1982 1993
1983 static struct omap_hwmod am33xx_tptc2_hwmod = { 1994 static struct omap_hwmod am33xx_tptc2_hwmod = {
1984 .name = "tptc2", 1995 .name = "tptc2",
1985 .class = &am33xx_tptc_hwmod_class, 1996 .class = &am33xx_tptc_hwmod_class,
1986 .mpu_irqs = am33xx_tptc2_irqs, 1997 .mpu_irqs = am33xx_tptc2_irqs,
1987 .main_clk = "tptc2_ick", 1998 .main_clk = "tptc2_ick",
1988 .clkdm_name = "l3_clkdm", 1999 .clkdm_name = "l3_clkdm",
1989 .prcm = { 2000 .prcm = {
1990 .omap4 = { 2001 .omap4 = {
1991 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, 2002 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1992 .modulemode = MODULEMODE_SWCTRL, 2003 .modulemode = MODULEMODE_SWCTRL,
1993 }, 2004 },
1994 }, 2005 },
1995 }; 2006 };
1996 2007
1997 /* 'uart' class */ 2008 /* 'uart' class */
1998 static struct omap_hwmod_class_sysconfig uart_sysc = { 2009 static struct omap_hwmod_class_sysconfig uart_sysc = {
1999 .rev_offs = 0x50, 2010 .rev_offs = 0x50,
2000 .sysc_offs = 0x54, 2011 .sysc_offs = 0x54,
2001 .syss_offs = 0x58, 2012 .syss_offs = 0x58,
2002 .sysc_flags = (SYSC_HAS_SIDLEMODE | 2013 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2003 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 2014 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2004 SYSC_HAS_AUTOIDLE), 2015 SYSC_HAS_AUTOIDLE),
2005 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2016 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2006 .sysc_fields = &omap_hwmod_sysc_type1, 2017 .sysc_fields = &omap_hwmod_sysc_type1,
2007 }; 2018 };
2008 2019
2009 static struct omap_hwmod_class uart_class = { 2020 static struct omap_hwmod_class uart_class = {
2010 .name = "uart", 2021 .name = "uart",
2011 .sysc = &uart_sysc, 2022 .sysc = &uart_sysc,
2012 }; 2023 };
2013 2024
2014 /* uart1 */ 2025 /* uart1 */
2015 static struct omap_hwmod_dma_info uart1_edma_reqs[] = { 2026 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
2016 { .name = "tx", .dma_req = 26, }, 2027 { .name = "tx", .dma_req = 26, },
2017 { .name = "rx", .dma_req = 27, }, 2028 { .name = "rx", .dma_req = 27, },
2018 { .dma_req = -1 } 2029 { .dma_req = -1 }
2019 }; 2030 };
2020 2031
2021 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = { 2032 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
2022 { 2033 {
2023 .pa_start = AM33XX_UART1_BASE, 2034 .pa_start = AM33XX_UART1_BASE,
2024 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1, 2035 .pa_end = AM33XX_UART1_BASE + SZ_8K - 1,
2025 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2036 .flags = ADDR_TYPE_RT
2026 }, 2037 },
2038 { }
2027 }; 2039 };
2028 2040
2029 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { 2041 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
2030 .master = &am33xx_l4wkup_hwmod, 2042 .master = &am33xx_l4wkup_hwmod,
2031 .slave = &am33xx_uart1_hwmod, 2043 .slave = &am33xx_uart1_hwmod,
2032 .clk = "uart1_ick", 2044 .clk = "uart1_ick",
2033 .addr = am33xx_uart1_addr_space, 2045 .addr = am33xx_uart1_addr_space,
2034 .user = OCP_USER_MPU, 2046 .user = OCP_USER_MPU,
2035 }; 2047 };
2036 2048
2037 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = { 2049 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2038 { .irq = AM33XX_IRQ_UART0 }, 2050 { .irq = AM33XX_IRQ_UART0 },
2039 { .irq = -1 } 2051 { .irq = -1 }
2040 }; 2052 };
2041 2053
2042 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = { 2054 static struct omap_hwmod_ocp_if *am33xx_uart1_slaves[] = {
2043 &am33xx_l4_wkup__uart1, 2055 &am33xx_l4_wkup__uart1,
2044 }; 2056 };
2045 2057
2046 static struct omap_hwmod am33xx_uart1_hwmod = { 2058 static struct omap_hwmod am33xx_uart1_hwmod = {
2047 .name = "uart1", 2059 .name = "uart1",
2048 .class = &uart_class, 2060 .class = &uart_class,
2049 .mpu_irqs = am33xx_uart1_irqs, 2061 .mpu_irqs = am33xx_uart1_irqs,
2050 .sdma_reqs = uart1_edma_reqs, 2062 .sdma_reqs = uart1_edma_reqs,
2051 .main_clk = "uart1_fck", 2063 .main_clk = "uart1_fck",
2052 .clkdm_name = "l4_wkup_clkdm", 2064 .clkdm_name = "l4_wkup_clkdm",
2053 .prcm = { 2065 .prcm = {
2054 .omap4 = { 2066 .omap4 = {
2055 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, 2067 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2056 .modulemode = MODULEMODE_SWCTRL, 2068 .modulemode = MODULEMODE_SWCTRL,
2057 }, 2069 },
2058 }, 2070 },
2059 .slaves = am33xx_uart1_slaves, 2071 .slaves = am33xx_uart1_slaves,
2060 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves), 2072 .slaves_cnt = ARRAY_SIZE(am33xx_uart1_slaves),
2061 }; 2073 };
2062 2074
2063 /* uart2 */ 2075 /* uart2 */
2064 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = { 2076 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
2065 { 2077 {
2066 .pa_start = AM33XX_UART2_BASE, 2078 .pa_start = AM33XX_UART2_BASE,
2067 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1, 2079 .pa_end = AM33XX_UART2_BASE + SZ_8K - 1,
2068 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2080 .flags = ADDR_TYPE_RT
2069 }, 2081 },
2082 { }
2070 }; 2083 };
2071 2084
2072 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { 2085 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
2073 .slave = &am33xx_uart2_hwmod, 2086 .slave = &am33xx_uart2_hwmod,
2074 .clk = "uart2_ick", 2087 .clk = "uart2_ick",
2075 .addr = am33xx_uart2_addr_space, 2088 .addr = am33xx_uart2_addr_space,
2076 .user = OCP_USER_MPU, 2089 .user = OCP_USER_MPU,
2077 }; 2090 };
2078 2091
2079 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { 2092 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2080 { .irq = AM33XX_IRQ_UART1 }, 2093 { .irq = AM33XX_IRQ_UART1 },
2081 { .irq = -1 }, 2094 { .irq = -1 }
2082 }; 2095 };
2083 2096
2084 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = { 2097 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2085 &am33xx_l4_ls__uart2, 2098 &am33xx_l4_ls__uart2,
2086 }; 2099 };
2087 2100
2088 static struct omap_hwmod am33xx_uart2_hwmod = { 2101 static struct omap_hwmod am33xx_uart2_hwmod = {
2089 .name = "uart2", 2102 .name = "uart2",
2090 .class = &uart_class, 2103 .class = &uart_class,
2091 .mpu_irqs = am33xx_uart2_irqs, 2104 .mpu_irqs = am33xx_uart2_irqs,
2092 .main_clk = "uart2_fck", 2105 .main_clk = "uart2_fck",
2093 .clkdm_name = "l4ls_clkdm", 2106 .clkdm_name = "l4ls_clkdm",
2094 .sdma_reqs = uart1_edma_reqs, 2107 .sdma_reqs = uart1_edma_reqs,
2095 .prcm = { 2108 .prcm = {
2096 .omap4 = { 2109 .omap4 = {
2097 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, 2110 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2098 .modulemode = MODULEMODE_SWCTRL, 2111 .modulemode = MODULEMODE_SWCTRL,
2099 }, 2112 },
2100 }, 2113 },
2101 .slaves = am33xx_uart2_slaves, 2114 .slaves = am33xx_uart2_slaves,
2102 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves), 2115 .slaves_cnt = ARRAY_SIZE(am33xx_uart2_slaves),
2103 }; 2116 };
2104 2117
2105 /* uart3 */ 2118 /* uart3 */
2106 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = { 2119 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
2107 { 2120 {
2108 .pa_start = AM33XX_UART3_BASE, 2121 .pa_start = AM33XX_UART3_BASE,
2109 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1, 2122 .pa_end = AM33XX_UART3_BASE + SZ_8K - 1,
2110 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2123 .flags = ADDR_TYPE_RT
2111 }, 2124 },
2125 { }
2112 }; 2126 };
2113 2127
2114 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { 2128 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
2115 .slave = &am33xx_uart3_hwmod, 2129 .slave = &am33xx_uart3_hwmod,
2116 .clk = "uart3_ick", 2130 .clk = "uart3_ick",
2117 .addr = am33xx_uart3_addr_space, 2131 .addr = am33xx_uart3_addr_space,
2118 .user = OCP_USER_MPU, 2132 .user = OCP_USER_MPU,
2119 }; 2133 };
2120 2134
2121 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = { 2135 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2122 { .irq = AM33XX_IRQ_UART2 }, 2136 { .irq = AM33XX_IRQ_UART2 },
2123 { .irq = -1 }, 2137 { .irq = -1 }
2124 }; 2138 };
2125 2139
2126 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = { 2140 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2127 &am33xx_l4_ls__uart3, 2141 &am33xx_l4_ls__uart3,
2128 }; 2142 };
2129 2143
2130 static struct omap_hwmod am33xx_uart3_hwmod = { 2144 static struct omap_hwmod am33xx_uart3_hwmod = {
2131 .name = "uart3", 2145 .name = "uart3",
2132 .class = &uart_class, 2146 .class = &uart_class,
2133 .mpu_irqs = am33xx_uart3_irqs, 2147 .mpu_irqs = am33xx_uart3_irqs,
2134 .main_clk = "uart3_fck", 2148 .main_clk = "uart3_fck",
2135 .clkdm_name = "l4ls_clkdm", 2149 .clkdm_name = "l4ls_clkdm",
2136 .sdma_reqs = uart1_edma_reqs, 2150 .sdma_reqs = uart1_edma_reqs,
2137 .prcm = { 2151 .prcm = {
2138 .omap4 = { 2152 .omap4 = {
2139 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, 2153 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2140 .modulemode = MODULEMODE_SWCTRL, 2154 .modulemode = MODULEMODE_SWCTRL,
2141 }, 2155 },
2142 }, 2156 },
2143 .slaves = am33xx_uart3_slaves, 2157 .slaves = am33xx_uart3_slaves,
2144 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves), 2158 .slaves_cnt = ARRAY_SIZE(am33xx_uart3_slaves),
2145 }; 2159 };
2146 2160
2147 /* uart4 */ 2161 /* uart4 */
2148 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = { 2162 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
2149 { 2163 {
2150 .pa_start = AM33XX_UART4_BASE, 2164 .pa_start = AM33XX_UART4_BASE,
2151 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1, 2165 .pa_end = AM33XX_UART4_BASE + SZ_8K - 1,
2152 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2166 .flags = ADDR_TYPE_RT
2153 }, 2167 },
2168 { }
2154 }; 2169 };
2155 2170
2156 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { 2171 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
2157 .slave = &am33xx_uart4_hwmod, 2172 .slave = &am33xx_uart4_hwmod,
2158 .clk = "uart4_ick", 2173 .clk = "uart4_ick",
2159 .addr = am33xx_uart4_addr_space, 2174 .addr = am33xx_uart4_addr_space,
2160 .user = OCP_USER_MPU, 2175 .user = OCP_USER_MPU,
2161 }; 2176 };
2162 2177
2163 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = { 2178 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2164 { .irq = AM33XX_IRQ_UART3 }, 2179 { .irq = AM33XX_IRQ_UART3 },
2165 { .irq = -1 }, 2180 { .irq = -1 }
2166 }; 2181 };
2167 2182
2168 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = { 2183 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2169 &am33xx_l4_ls__uart4, 2184 &am33xx_l4_ls__uart4,
2170 }; 2185 };
2171 2186
2172 static struct omap_hwmod am33xx_uart4_hwmod = { 2187 static struct omap_hwmod am33xx_uart4_hwmod = {
2173 .name = "uart4", 2188 .name = "uart4",
2174 .class = &uart_class, 2189 .class = &uart_class,
2175 .mpu_irqs = am33xx_uart4_irqs, 2190 .mpu_irqs = am33xx_uart4_irqs,
2176 .main_clk = "uart4_fck", 2191 .main_clk = "uart4_fck",
2177 .clkdm_name = "l4ls_clkdm", 2192 .clkdm_name = "l4ls_clkdm",
2178 .sdma_reqs = uart1_edma_reqs, 2193 .sdma_reqs = uart1_edma_reqs,
2179 .prcm = { 2194 .prcm = {
2180 .omap4 = { 2195 .omap4 = {
2181 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, 2196 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2182 .modulemode = MODULEMODE_SWCTRL, 2197 .modulemode = MODULEMODE_SWCTRL,
2183 }, 2198 },
2184 }, 2199 },
2185 .slaves = am33xx_uart4_slaves, 2200 .slaves = am33xx_uart4_slaves,
2186 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves), 2201 .slaves_cnt = ARRAY_SIZE(am33xx_uart4_slaves),
2187 }; 2202 };
2188 2203
2189 /* uart5 */ 2204 /* uart5 */
2190 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = { 2205 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
2191 { 2206 {
2192 .pa_start = AM33XX_UART5_BASE, 2207 .pa_start = AM33XX_UART5_BASE,
2193 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1, 2208 .pa_end = AM33XX_UART5_BASE + SZ_8K - 1,
2194 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2209 .flags = ADDR_TYPE_RT
2195 }, 2210 },
2211 { }
2196 }; 2212 };
2197 2213
2198 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { 2214 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
2199 .slave = &am33xx_uart5_hwmod, 2215 .slave = &am33xx_uart5_hwmod,
2200 .clk = "uart5_ick", 2216 .clk = "uart5_ick",
2201 .addr = am33xx_uart5_addr_space, 2217 .addr = am33xx_uart5_addr_space,
2202 .user = OCP_USER_MPU, 2218 .user = OCP_USER_MPU,
2203 }; 2219 };
2204 2220
2205 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = { 2221 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2206 { .irq = AM33XX_IRQ_UART4 }, 2222 { .irq = AM33XX_IRQ_UART4 },
2207 { .irq = -1 }, 2223 { .irq = -1 }
2208 }; 2224 };
2209 2225
2210 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = { 2226 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2211 &am33xx_l4_ls__uart5, 2227 &am33xx_l4_ls__uart5,
2212 }; 2228 };
2213 2229
2214 static struct omap_hwmod am33xx_uart5_hwmod = { 2230 static struct omap_hwmod am33xx_uart5_hwmod = {
2215 .name = "uart5", 2231 .name = "uart5",
2216 .class = &uart_class, 2232 .class = &uart_class,
2217 .mpu_irqs = am33xx_uart5_irqs, 2233 .mpu_irqs = am33xx_uart5_irqs,
2218 .main_clk = "uart5_fck", 2234 .main_clk = "uart5_fck",
2219 .clkdm_name = "l4ls_clkdm", 2235 .clkdm_name = "l4ls_clkdm",
2220 .sdma_reqs = uart1_edma_reqs, 2236 .sdma_reqs = uart1_edma_reqs,
2221 .prcm = { 2237 .prcm = {
2222 .omap4 = { 2238 .omap4 = {
2223 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, 2239 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2224 .modulemode = MODULEMODE_SWCTRL, 2240 .modulemode = MODULEMODE_SWCTRL,
2225 }, 2241 },
2226 }, 2242 },
2227 .slaves = am33xx_uart5_slaves, 2243 .slaves = am33xx_uart5_slaves,
2228 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves), 2244 .slaves_cnt = ARRAY_SIZE(am33xx_uart5_slaves),
2229 }; 2245 };
2230 2246
2231 /* uart6 */ 2247 /* uart6 */
2232 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = { 2248 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
2233 { 2249 {
2234 .pa_start = AM33XX_UART6_BASE, 2250 .pa_start = AM33XX_UART6_BASE,
2235 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1, 2251 .pa_end = AM33XX_UART6_BASE + SZ_8K - 1,
2236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2252 .flags = ADDR_TYPE_RT
2237 }, 2253 },
2254 { }
2238 }; 2255 };
2239 2256
2240 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { 2257 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
2241 .slave = &am33xx_uart6_hwmod, 2258 .slave = &am33xx_uart6_hwmod,
2242 .clk = "uart6_ick", 2259 .clk = "uart6_ick",
2243 .addr = am33xx_uart6_addr_space, 2260 .addr = am33xx_uart6_addr_space,
2244 .user = OCP_USER_MPU, 2261 .user = OCP_USER_MPU,
2245 }; 2262 };
2246 2263
2247 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = { 2264 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2248 { .irq = AM33XX_IRQ_UART5 }, 2265 { .irq = AM33XX_IRQ_UART5 },
2249 { .irq = -1 }, 2266 { .irq = -1 }
2250 }; 2267 };
2251 2268
2252 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = { 2269 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2253 &am33xx_l4_ls__uart6, 2270 &am33xx_l4_ls__uart6,
2254 }; 2271 };
2255 2272
2256 static struct omap_hwmod am33xx_uart6_hwmod = { 2273 static struct omap_hwmod am33xx_uart6_hwmod = {
2257 .name = "uart6", 2274 .name = "uart6",
2258 .class = &uart_class, 2275 .class = &uart_class,
2259 .mpu_irqs = am33xx_uart6_irqs, 2276 .mpu_irqs = am33xx_uart6_irqs,
2260 .main_clk = "uart6_fck", 2277 .main_clk = "uart6_fck",
2261 .clkdm_name = "l4ls_clkdm", 2278 .clkdm_name = "l4ls_clkdm",
2262 .sdma_reqs = uart1_edma_reqs, 2279 .sdma_reqs = uart1_edma_reqs,
2263 .prcm = { 2280 .prcm = {
2264 .omap4 = { 2281 .omap4 = {
2265 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, 2282 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2266 .modulemode = MODULEMODE_SWCTRL, 2283 .modulemode = MODULEMODE_SWCTRL,
2267 }, 2284 },
2268 }, 2285 },
2269 .slaves = am33xx_uart6_slaves, 2286 .slaves = am33xx_uart6_slaves,
2270 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves), 2287 .slaves_cnt = ARRAY_SIZE(am33xx_uart6_slaves),
2271 }; 2288 };
2272 2289
2273 /* 'wd_timer' class */ 2290 /* 'wd_timer' class */
2274 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { 2291 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2275 .name = "wd_timer", 2292 .name = "wd_timer",
2276 }; 2293 };
2277 2294
2278 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = { 2295 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2279 { 2296 {
2280 .pa_start = AM33XX_WDT1_BASE, 2297 .pa_start = AM33XX_WDT1_BASE,
2281 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1, 2298 .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2282 .flags = ADDR_TYPE_RT 2299 .flags = ADDR_TYPE_RT
2283 }, 2300 },
2284 { }, 2301 { }
2285 }; 2302 };
2286 2303
2287 /* l4_wkup -> wd_timer1 */ 2304 /* l4_wkup -> wd_timer1 */
2288 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = { 2305 static struct omap_hwmod_ocp_if am33xx_l4wkup__wd_timer1 = {
2289 .master = &am33xx_l4wkup_hwmod, 2306 .master = &am33xx_l4wkup_hwmod,
2290 .slave = &am33xx_wd_timer1_hwmod, 2307 .slave = &am33xx_wd_timer1_hwmod,
2291 .addr = am33xx_wd_timer1_addrs, 2308 .addr = am33xx_wd_timer1_addrs,
2292 .user = OCP_USER_MPU, 2309 .user = OCP_USER_MPU,
2293 }; 2310 };
2294 2311
2295 /* wd_timer1 slave ports */ 2312 /* wd_timer1 slave ports */
2296 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = { 2313 static struct omap_hwmod_ocp_if *am33xx_wd_timer1_slaves[] = {
2297 &am33xx_l4wkup__wd_timer1, 2314 &am33xx_l4wkup__wd_timer1,
2298 }; 2315 };
2299 2316
2300 /* wd_timer1 */ 2317 /* wd_timer1 */
2301 /* 2318 /*
2302 * TODO: device.c file uses hardcoded name for watchdog 2319 * TODO: device.c file uses hardcoded name for watchdog
2303 timer driver "wd_timer2, so we are also using 2320 timer driver "wd_timer2, so we are also using
2304 same name as of now... 2321 same name as of now...
2305 */ 2322 */
2306 static struct omap_hwmod am33xx_wd_timer1_hwmod = { 2323 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2307 .name = "wd_timer2", 2324 .name = "wd_timer2",
2308 .class = &am33xx_wd_timer_hwmod_class, 2325 .class = &am33xx_wd_timer_hwmod_class,
2309 .main_clk = "wdt1_fck", 2326 .main_clk = "wdt1_fck",
2310 .clkdm_name = "l4_wkup_clkdm", 2327 .clkdm_name = "l4_wkup_clkdm",
2311 .prcm = { 2328 .prcm = {
2312 .omap4 = { 2329 .omap4 = {
2313 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, 2330 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2314 .modulemode = MODULEMODE_SWCTRL, 2331 .modulemode = MODULEMODE_SWCTRL,
2315 }, 2332 },
2316 }, 2333 },
2317 .slaves = am33xx_wd_timer1_slaves, 2334 .slaves = am33xx_wd_timer1_slaves,
2318 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves), 2335 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2319 }; 2336 };
2320 2337
2321 /* 'wkup_m3' class */ 2338 /* 'wkup_m3' class */
2322 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { 2339 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2323 .name = "wkup_m3", 2340 .name = "wkup_m3",
2324 }; 2341 };
2325 2342
2326 /* wkup_m3 */ 2343 /* wkup_m3 */
2327 static struct omap_hwmod am33xx_wkup_m3_hwmod = { 2344 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
2328 .name = "wkup_m3", 2345 .name = "wkup_m3",
2329 .class = &am33xx_wkup_m3_hwmod_class, 2346 .class = &am33xx_wkup_m3_hwmod_class,
2330 .clkdm_name = "l4_wkup_aon_clkdm", 2347 .clkdm_name = "l4_wkup_aon_clkdm",
2331 .main_clk = "wkup_m3_fck", 2348 .main_clk = "wkup_m3_fck",
2332 .prcm = { 2349 .prcm = {
2333 .omap4 = { 2350 .omap4 = {
2334 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, 2351 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2335 .modulemode = MODULEMODE_SWCTRL, 2352 .modulemode = MODULEMODE_SWCTRL,
2336 }, 2353 },
2337 }, 2354 },
2338 }; 2355 };
2339 2356
2340 /* L3 SLOW -> USBSS interface */ 2357 /* L3 SLOW -> USBSS interface */
2341 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = { 2358 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2342 { 2359 {
2343 .name = "usbss", 2360 .name = "usbss",
2344 .pa_start = AM33XX_USBSS_BASE, 2361 .pa_start = AM33XX_USBSS_BASE,
2345 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1, 2362 .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2346 .flags = ADDR_TYPE_RT 2363 .flags = ADDR_TYPE_RT
2347 }, 2364 },
2348 { 2365 {
2349 .name = "musb0", 2366 .name = "musb0",
2350 .pa_start = AM33XX_USB0_BASE, 2367 .pa_start = AM33XX_USB0_BASE,
2351 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1, 2368 .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2352 .flags = ADDR_TYPE_RT 2369 .flags = ADDR_TYPE_RT
2353 }, 2370 },
2354 { 2371 {
2355 .name = "musb1", 2372 .name = "musb1",
2356 .pa_start = AM33XX_USB1_BASE, 2373 .pa_start = AM33XX_USB1_BASE,
2357 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1, 2374 .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2358 .flags = ADDR_TYPE_RT 2375 .flags = ADDR_TYPE_RT
2359 }, 2376 },
2360 { 2377 { }
2361 },
2362 }; 2378 };
2363 2379
2364 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { 2380 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2365 .rev_offs = 0x0, 2381 .rev_offs = 0x0,
2366 .sysc_offs = 0x10, 2382 .sysc_offs = 0x10,
2367 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2383 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2368 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2369 .sysc_fields = &omap_hwmod_sysc_type2, 2385 .sysc_fields = &omap_hwmod_sysc_type2,
2370 }; 2386 };
2371 2387
2372 static struct omap_hwmod_class am33xx_usbotg_class = { 2388 static struct omap_hwmod_class am33xx_usbotg_class = {
2373 .name = "usbotg", 2389 .name = "usbotg",
2374 .sysc = &am33xx_usbhsotg_sysc, 2390 .sysc = &am33xx_usbhsotg_sysc,
2375 }; 2391 };
2376 2392
2377 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = { 2393 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2378 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, }, 2394 { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
2379 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, }, 2395 { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
2380 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, }, 2396 { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2381 { .irq = -1, }, 2397 { .irq = -1, },
2382 }; 2398 };
2383 2399
2384 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = { 2400 static struct omap_hwmod_ocp_if am33xx_l3_slow__usbss = {
2385 .master = &am33xx_l3slow_hwmod, 2401 .master = &am33xx_l3slow_hwmod,
2386 .slave = &am33xx_usbss_hwmod, 2402 .slave = &am33xx_usbss_hwmod,
2387 .addr = am33xx_usbss_addr_space, 2403 .addr = am33xx_usbss_addr_space,
2388 .user = OCP_USER_MPU, 2404 .user = OCP_USER_MPU,
2389 .flags = OCPIF_SWSUP_IDLE, 2405 .flags = OCPIF_SWSUP_IDLE,
2390 }; 2406 };
2391 2407
2392 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = { 2408 static struct omap_hwmod_ocp_if *am33xx_usbss_slaves[] = {
2393 &am33xx_l3_slow__usbss, 2409 &am33xx_l3_slow__usbss,
2394 }; 2410 };
2395 2411
2396 static struct omap_hwmod_opt_clk usbss_opt_clks[] = { 2412 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2397 { .role = "clkdcoldo", .clk = "usbotg_fck" }, 2413 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2398 }; 2414 };
2399 2415
2400 static struct omap_hwmod am33xx_usbss_hwmod = { 2416 static struct omap_hwmod am33xx_usbss_hwmod = {
2401 .name = "usb_otg_hs", 2417 .name = "usb_otg_hs",
2402 .mpu_irqs = am33xx_usbss_mpu_irqs, 2418 .mpu_irqs = am33xx_usbss_mpu_irqs,
2403 .main_clk = "usbotg_ick", 2419 .main_clk = "usbotg_ick",
2404 .clkdm_name = "l4ls_clkdm", 2420 .clkdm_name = "l4ls_clkdm",
2405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2421 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2406 .prcm = { 2422 .prcm = {
2407 .omap4 = { 2423 .omap4 = {
2408 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, 2424 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2409 .modulemode = MODULEMODE_SWCTRL, 2425 .modulemode = MODULEMODE_SWCTRL,
2410 }, 2426 },
2411 }, 2427 },
2412 .opt_clks = usbss_opt_clks, 2428 .opt_clks = usbss_opt_clks,
2413 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks), 2429 .opt_clks_cnt = ARRAY_SIZE(usbss_opt_clks),
2414 .slaves = am33xx_usbss_slaves, 2430 .slaves = am33xx_usbss_slaves,
2415 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves), 2431 .slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
2416 .class = &am33xx_usbotg_class, 2432 .class = &am33xx_usbotg_class,
2417 }; 2433 };
2418 2434
2419 /* sgx/gfx */ 2435 /* sgx/gfx */
2420 /* Pseudo hwmod for reset control purpose only */ 2436 /* Pseudo hwmod for reset control purpose only */
2421 static struct omap_hwmod_class am33xx_gfx_hwmod_class = { 2437 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
2422 .name = "gfx", 2438 .name = "gfx",
2423 }; 2439 };
2424 2440
2425 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { 2441 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
2426 { .name = "gfx", .rst_shift = 0, .st_shift = 0 }, 2442 { .name = "gfx", .rst_shift = 0, .st_shift = 0 },
2427 }; 2443 };
2428 2444
2429 static struct omap_hwmod am33xx_gfx_hwmod = { 2445 static struct omap_hwmod am33xx_gfx_hwmod = {
2430 .name = "gfx", 2446 .name = "gfx",
2431 .class = &am33xx_gfx_hwmod_class, 2447 .class = &am33xx_gfx_hwmod_class,
2432 .clkdm_name = "gfx_l3_clkdm", 2448 .clkdm_name = "gfx_l3_clkdm",
2433 .rst_lines = am33xx_gfx_resets, 2449 .rst_lines = am33xx_gfx_resets,
2434 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), 2450 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
2435 }; 2451 };
2436 2452
2437 /* PRUSS/ICSS */ 2453 /* PRUSS/ICSS */
2438 /* Pseudo hwmod for reset control purpose only */ 2454 /* Pseudo hwmod for reset control purpose only */
2439 static struct omap_hwmod_class am33xx_pruss_hwmod_class = { 2455 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
2440 .name = "pruss", 2456 .name = "pruss",
2441 }; 2457 };
2442 2458
2443 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { 2459 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
2444 { .name = "pruss", .rst_shift = 1, .st_shift = 1 }, 2460 { .name = "pruss", .rst_shift = 1, .st_shift = 1 },
2445 }; 2461 };
2446 2462
2447 static struct omap_hwmod am33xx_pruss_hwmod = { 2463 static struct omap_hwmod am33xx_pruss_hwmod = {
2448 .name = "pruss", 2464 .name = "pruss",
2449 .class = &am33xx_pruss_hwmod_class, 2465 .class = &am33xx_pruss_hwmod_class,
2450 .clkdm_name = "icss_ocp_clkdm", 2466 .clkdm_name = "icss_ocp_clkdm",
2451 .rst_lines = am33xx_pruss_resets, 2467 .rst_lines = am33xx_pruss_resets,
2452 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), 2468 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
2453 }; 2469 };
2454 2470
2455 static __initdata struct omap_hwmod *am33xx_hwmods[] = { 2471 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2456 /* l3 class */ 2472 /* l3 class */
2457 &am33xx_l3_instr_hwmod, 2473 &am33xx_l3_instr_hwmod,
2458 &am33xx_l3_main_hwmod, 2474 &am33xx_l3_main_hwmod,
2459 /* l3s class */ 2475 /* l3s class */
2460 &am33xx_l3slow_hwmod, 2476 &am33xx_l3slow_hwmod,
2461 /* l4hs class */ 2477 /* l4hs class */
2462 &am33xx_l4_hs_hwmod, 2478 &am33xx_l4_hs_hwmod,
2463 /* l4fw class */ 2479 /* l4fw class */
2464 &am33xx_l4fw_hwmod, 2480 &am33xx_l4fw_hwmod,
2465 /* l4ls class */ 2481 /* l4ls class */
2466 &am33xx_l4ls_hwmod, 2482 &am33xx_l4ls_hwmod,
2467 /* l4per class */ 2483 /* l4per class */
2468 &am33xx_l4per_hwmod, 2484 &am33xx_l4per_hwmod,
2469 /* l4wkup class */ 2485 /* l4wkup class */
2470 &am33xx_l4wkup_hwmod, 2486 &am33xx_l4wkup_hwmod,
2471 2487
2472 /* clkdiv32k class */ 2488 /* clkdiv32k class */
2473 &am33xx_clkdiv32k_hwmod, 2489 &am33xx_clkdiv32k_hwmod,
2474 /* mpu class */ 2490 /* mpu class */
2475 &am33xx_mpu_hwmod, 2491 &am33xx_mpu_hwmod,
2476 /* adc_tsc class */ 2492 /* adc_tsc class */
2477 &am33xx_adc_tsc_hwmod, 2493 &am33xx_adc_tsc_hwmod,
2478 /* aes class */ 2494 /* aes class */
2479 &am33xx_aes0_hwmod, 2495 &am33xx_aes0_hwmod,
2480 /* cefuse class */ 2496 /* cefuse class */
2481 &am33xx_cefuse_hwmod, 2497 &am33xx_cefuse_hwmod,
2482 /* control class */ 2498 /* control class */
2483 &am33xx_control_hwmod, 2499 &am33xx_control_hwmod,
2484 /* dcan class */ 2500 /* dcan class */
2485 &am33xx_dcan0_hwmod, 2501 &am33xx_dcan0_hwmod,
2486 &am33xx_dcan1_hwmod, 2502 &am33xx_dcan1_hwmod,
2487 /* debugss class */ 2503 /* debugss class */
2488 &am33xx_debugss_hwmod, 2504 &am33xx_debugss_hwmod,
2489 /* elm class */ 2505 /* elm class */
2490 &am33xx_elm_hwmod, 2506 &am33xx_elm_hwmod,
2491 /* emif_fw class */ 2507 /* emif_fw class */
2492 &am33xx_emif_fw_hwmod, 2508 &am33xx_emif_fw_hwmod,
2493 /* epwmss class */ 2509 /* epwmss class */
2494 &am33xx_epwmss0_hwmod, 2510 &am33xx_epwmss0_hwmod,
2495 &am33xx_epwmss1_hwmod, 2511 &am33xx_epwmss1_hwmod,
2496 &am33xx_epwmss2_hwmod, 2512 &am33xx_epwmss2_hwmod,
2497 /* gpio class */ 2513 /* gpio class */
2498 &am33xx_gpio0_hwmod, 2514 &am33xx_gpio0_hwmod,
2499 &am33xx_gpio1_hwmod, 2515 &am33xx_gpio1_hwmod,
2500 &am33xx_gpio2_hwmod, 2516 &am33xx_gpio2_hwmod,
2501 &am33xx_gpio3_hwmod, 2517 &am33xx_gpio3_hwmod,
2502 /* gpmc class */ 2518 /* gpmc class */
2503 &am33xx_gpmc_hwmod, 2519 &am33xx_gpmc_hwmod,
2504 /* i2c class */ 2520 /* i2c class */
2505 &am33xx_i2c1_hwmod, 2521 &am33xx_i2c1_hwmod,
2506 &am33xx_i2c2_hwmod, 2522 &am33xx_i2c2_hwmod,
2507 /* icss class */ 2523 /* icss class */
2508 &am33xx_icss_hwmod, 2524 &am33xx_icss_hwmod,
2509 /* ieee5000 class */ 2525 /* ieee5000 class */
2510 &am33xx_ieee5000_hwmod, 2526 &am33xx_ieee5000_hwmod,
2511 /* mcasp class */ 2527 /* mcasp class */
2512 &am33xx_mcasp0_hwmod, 2528 &am33xx_mcasp0_hwmod,
2513 /* mmc class */ 2529 /* mmc class */
2514 &am33xx_mmc0_hwmod, 2530 &am33xx_mmc0_hwmod,
2515 &am33xx_mmc1_hwmod, 2531 &am33xx_mmc1_hwmod,
2516 &am33xx_mmc2_hwmod, 2532 &am33xx_mmc2_hwmod,
2517 /* ocmcram class */ 2533 /* ocmcram class */
2518 &am33xx_ocmcram_hwmod, 2534 &am33xx_ocmcram_hwmod,
2519 /* ocpwp class */ 2535 /* ocpwp class */
2520 &am33xx_ocpwp_hwmod, 2536 &am33xx_ocpwp_hwmod,
2521 /* sha0 class */ 2537 /* sha0 class */
2522 &am33xx_sha0_hwmod, 2538 &am33xx_sha0_hwmod,
2523 /* smartreflex class */ 2539 /* smartreflex class */
2524 &am33xx_smartreflex0_hwmod, 2540 &am33xx_smartreflex0_hwmod,
2525 &am33xx_smartreflex1_hwmod, 2541 &am33xx_smartreflex1_hwmod,
2526 /* spi class */ 2542 /* spi class */
2527 &am33xx_spi0_hwmod, 2543 &am33xx_spi0_hwmod,
2528 &am33xx_spi1_hwmod, 2544 &am33xx_spi1_hwmod,
2529 /* spinlock class */ 2545 /* spinlock class */
2530 &am33xx_spinlock_hwmod, 2546 &am33xx_spinlock_hwmod,
2531 /* uart class */ 2547 /* uart class */
2532 &am33xx_uart1_hwmod, 2548 &am33xx_uart1_hwmod,
2533 &am33xx_uart2_hwmod, 2549 &am33xx_uart2_hwmod,
2534 &am33xx_uart3_hwmod, 2550 &am33xx_uart3_hwmod,
2535 &am33xx_uart4_hwmod, 2551 &am33xx_uart4_hwmod,
2536 &am33xx_uart5_hwmod, 2552 &am33xx_uart5_hwmod,
2537 &am33xx_uart6_hwmod, 2553 &am33xx_uart6_hwmod,
2538 /* timer class */ 2554 /* timer class */
2539 &am33xx_timer0_hwmod, 2555 &am33xx_timer0_hwmod,
2540 &am33xx_timer1_hwmod, 2556 &am33xx_timer1_hwmod,
2541 &am33xx_timer2_hwmod, 2557 &am33xx_timer2_hwmod,
2542 &am33xx_timer3_hwmod, 2558 &am33xx_timer3_hwmod,
2543 &am33xx_timer4_hwmod, 2559 &am33xx_timer4_hwmod,
2544 &am33xx_timer5_hwmod, 2560 &am33xx_timer5_hwmod,
2545 &am33xx_timer6_hwmod, 2561 &am33xx_timer6_hwmod,
2546 &am33xx_timer7_hwmod, 2562 &am33xx_timer7_hwmod,
2547 /* wkup_m3 class */ 2563 /* wkup_m3 class */
2548 &am33xx_wkup_m3_hwmod, 2564 &am33xx_wkup_m3_hwmod,
2549 /* wd_timer class */ 2565 /* wd_timer class */
2550 &am33xx_wd_timer1_hwmod, 2566 &am33xx_wd_timer1_hwmod,
2551 /* usbss hwmod */ 2567 /* usbss hwmod */
2552 &am33xx_usbss_hwmod, 2568 &am33xx_usbss_hwmod,
2553 /* cpgmac0 class */ 2569 /* cpgmac0 class */
2554 &am33xx_cpgmac0_hwmod, 2570 &am33xx_cpgmac0_hwmod,
2555 /* tptc class */ 2571 /* tptc class */
2556 &am33xx_tptc0_hwmod, 2572 &am33xx_tptc0_hwmod,
2557 &am33xx_tptc1_hwmod, 2573 &am33xx_tptc1_hwmod,
2558 &am33xx_tptc2_hwmod, 2574 &am33xx_tptc2_hwmod,
2559 /* tpcc class */ 2575 /* tpcc class */
2560 &am33xx_tpcc_hwmod, 2576 &am33xx_tpcc_hwmod,
2561 /* LCDC class */ 2577 /* LCDC class */
2562 &am33xx_lcdc_hwmod, 2578 &am33xx_lcdc_hwmod,
2563 /* gfx/sgx */ 2579 /* gfx/sgx */
2564 &am33xx_gfx_hwmod, 2580 &am33xx_gfx_hwmod,
2565 /* pruss/icss */ 2581 /* pruss/icss */
2566 &am33xx_pruss_hwmod, 2582 &am33xx_pruss_hwmod,
2567 /* rtc */ 2583 /* rtc */
2568 &am33xx_rtc_hwmod, 2584 &am33xx_rtc_hwmod,
2569 NULL, 2585 NULL,
2570 }; 2586 };
2571 2587
2572 int __init am33xx_hwmod_init(void) 2588 int __init am33xx_hwmod_init(void)
2573 { 2589 {
2574 return omap_hwmod_register(am33xx_hwmods); 2590 return omap_hwmod_register(am33xx_hwmods);
2575 } 2591 }