Eric Lee / linux-smarc-t335x-v3.2

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Commit 73f10281ea96d7e8b4fc1c5d755a7c8eb484155b

Authored by Nick Piggin
Committed by Linus Torvalds
1 parent 4ef7e3e90f
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

read_barrier_depends arch fixlets 

read_barrie_depends has always been a noop (not a compiler barrier) on all
architectures except SMP alpha. This brings UP alpha and frv into line with all
other architectures, and fixes incorrect documentation.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 3 changed files with 13 additions and 3 deletions Side-by-side Diff

Documentation/memory-barriers.txt
Diff comments   View file @ 73f1028
... ... @@ -994,7 +994,17 @@
994 994 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
995 995  
996 996  
997   -All CPU memory barriers unconditionally imply compiler barriers.
  997 +All memory barriers except the data dependency barriers imply a compiler
  998 +barrier. Data dependencies do not impose any additional compiler ordering.
  999 +
  1000 +Aside: In the case of data dependencies, the compiler would be expected to
  1001 +issue the loads in the correct order (eg. `a[b]` would have to load the value
  1002 +of b before loading a[b]), however there is no guarantee in the C specification
  1003 +that the compiler may not speculate the value of b (eg. is equal to 1) and load
  1004 +a before b (eg. tmp = a[1]; if (b != 1) tmp = a[b]; ). There is also the
  1005 +problem of a compiler reloading b after having loaded a[b], thus having a newer
  1006 +copy of b than a[b]. A consensus has not yet been reached about these problems,
  1007 +however the ACCESS_ONCE macro is a good place to start looking.
998 1008  
999 1009 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1000 1010 systems because it is assumed that a CPU will appear to be self-consistent,
include/asm-alpha/barrier.h
Diff comments   View file @ 73f1028
... ... @@ -24,7 +24,7 @@
24 24 #define smp_mb() barrier()
25 25 #define smp_rmb() barrier()
26 26 #define smp_wmb() barrier()
27   -#define smp_read_barrier_depends() barrier()
  27 +#define smp_read_barrier_depends() do { } while (0)
28 28 #endif
29 29  
30 30 #define set_mb(var, value) \
include/asm-frv/system.h
Diff comments   View file @ 73f1028
... ... @@ -179,7 +179,7 @@
179 179 #define mb() asm volatile ("membar" : : :"memory")
180 180 #define rmb() asm volatile ("membar" : : :"memory")
181 181 #define wmb() asm volatile ("membar" : : :"memory")
182   -#define read_barrier_depends() barrier()
  182 +#define read_barrier_depends() do { } while (0)
183 183  
184 184 #ifdef CONFIG_SMP
185 185 #define smp_mb() mb()