Eric Lee / linux-smarc-t335x-v3.2

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Commit 7a4a207e74d6aeb63a38e9a3f0cfc40223d5c40e

Authored by Michael Hennerich
Committed by Mike Frysinger
1 parent 812ae98f08
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options 

Newer parts have optional Hysteresis/Schmitt Trigger options to help with
dirty signals.  So add some kconfig options for tuning this and enable it
by default for people.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Showing 5 changed files with 359 additions and 0 deletions Side-by-side Diff

arch/blackfin/kernel/setup.c
Diff comments   View file @ 7a4a207
... ... @@ -864,6 +864,13 @@
864 864 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
865 865 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
866 866 #endif
  867 +#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
  868 + bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
  869 + bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
  870 + bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
  871 + bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
  872 + ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
  873 +#endif
867 874  
868 875 cclk = get_cclk();
869 876 sclk = get_sclk();
arch/blackfin/mach-bf518/Kconfig
Diff comments   View file @ 7a4a207
... ... @@ -62,6 +62,67 @@
62 62 PORT G
63 63 endchoice
64 64  
  65 +comment "Hysteresis/Schmitt Trigger Control"
  66 +config BFIN_HYSTERESIS_CONTROL
  67 + bool "Enable Hysteresis Control"
  68 + help
  69 + The ADSP-BF51x allows to control input hysteresis for Port F,
  70 + Port G and Port H and other processor signal inputs.
  71 + The Schmitt trigger enables can be set only for pin groups.
  72 + Saying Y will overwrite the default reset or boot loader
  73 + initialization.
  74 +
  75 +menu "PORT F"
  76 + depends on BFIN_HYSTERESIS_CONTROL
  77 +config GPIO_HYST_PORTF_0_7
  78 + bool "Enable Hysteresis on PORTF {0...7}"
  79 +config GPIO_HYST_PORTF_8_9
  80 + bool "Enable Hysteresis on PORTF {8, 9}"
  81 +config GPIO_HYST_PORTF_10
  82 + bool "Enable Hysteresis on PORTF 10"
  83 +config GPIO_HYST_PORTF_11
  84 + bool "Enable Hysteresis on PORTF 11"
  85 +config GPIO_HYST_PORTF_12_13
  86 + bool "Enable Hysteresis on PORTF {12, 13}"
  87 +config GPIO_HYST_PORTF_14_15
  88 + bool "Enable Hysteresis on PORTF {14, 15}"
  89 +endmenu
  90 +
  91 +menu "PORT G"
  92 + depends on BFIN_HYSTERESIS_CONTROL
  93 +config GPIO_HYST_PORTG_0
  94 + bool "Enable Hysteresis on PORTG 0"
  95 +config GPIO_HYST_PORTG_1_4
  96 + bool "Enable Hysteresis on PORTG {1...4}"
  97 +config GPIO_HYST_PORTG_5_6
  98 + bool "Enable Hysteresis on PORTG {5, 6}"
  99 +config GPIO_HYST_PORTG_7_8
  100 + bool "Enable Hysteresis on PORTG {7, 8}"
  101 +config GPIO_HYST_PORTG_9
  102 + bool "Enable Hysteresis on PORTG 9"
  103 +config GPIO_HYST_PORTG_10
  104 + bool "Enable Hysteresis on PORTG 10"
  105 +config GPIO_HYST_PORTG_11_13
  106 + bool "Enable Hysteresis on PORTG {11...13}"
  107 +config GPIO_HYST_PORTG_14_15
  108 + bool "Enable Hysteresis on PORTG {14, 15}"
  109 +endmenu
  110 +
  111 +menu "PORT H"
  112 + depends on BFIN_HYSTERESIS_CONTROL
  113 +config GPIO_HYST_PORTH_0_7
  114 + bool "Enable Hysteresis on PORTH {0...7}"
  115 +
  116 +endmenu
  117 +
  118 +menu "None-GPIO"
  119 + depends on BFIN_HYSTERESIS_CONTROL
  120 +config NONEGPIO_HYST_NMI_RST_BMODE
  121 + bool "Enable Hysteresis on {NMI, RESET, BMODE}"
  122 +config NONEGPIO_HYST_JTAG
  123 + bool "Enable Hysteresis on JTAG"
  124 +endmenu
  125 +
65 126 comment "Interrupt Priority Assignment"
66 127 menu "Priority"
67 128  
arch/blackfin/mach-bf518/include/mach/bf518.h
Diff comments   View file @ 7a4a207
... ... @@ -85,6 +85,111 @@
85 85  
86 86 #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
87 87  
  88 +/**************************** Hysteresis Settings ****************************/
  89 +
  90 +#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
  91 +#ifdef CONFIG_GPIO_HYST_PORTF_0_7
  92 +#define HYST_PORTF_0_7 (1 << 0)
  93 +#else
  94 +#define HYST_PORTF_0_7 (0 << 0)
  95 +#endif
  96 +#ifdef CONFIG_GPIO_HYST_PORTF_8_9
  97 +#define HYST_PORTF_8_9 (1 << 2)
  98 +#else
  99 +#define HYST_PORTF_8_9 (0 << 2)
  100 +#endif
  101 +#ifdef CONFIG_GPIO_HYST_PORTF_10
  102 +#define HYST_PORTF_10 (1 << 4)
  103 +#else
  104 +#define HYST_PORTF_10 (0 << 4)
  105 +#endif
  106 +#ifdef CONFIG_GPIO_HYST_PORTF_11
  107 +#define HYST_PORTF_11 (1 << 6)
  108 +#else
  109 +#define HYST_PORTF_11 (0 << 6)
  110 +#endif
  111 +#ifdef CONFIG_GPIO_HYST_PORTF_12_13
  112 +#define HYST_PORTF_12_13 (1 << 8)
  113 +#else
  114 +#define HYST_PORTF_12_13 (0 << 8)
  115 +#endif
  116 +#ifdef CONFIG_GPIO_HYST_PORTF_14_15
  117 +#define HYST_PORTF_14_15 (1 << 10)
  118 +#else
  119 +#define HYST_PORTF_14_15 (0 << 10)
  120 +#endif
  121 +
  122 +#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
  123 + HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
  124 +
  125 +#ifdef CONFIG_GPIO_HYST_PORTG_0
  126 +#define HYST_PORTG_0 (1 << 0)
  127 +#else
  128 +#define HYST_PORTG_0 (0 << 0)
  129 +#endif
  130 +#ifdef CONFIG_GPIO_HYST_PORTG_1_4
  131 +#define HYST_PORTG_1_4 (1 << 2)
  132 +#else
  133 +#define HYST_PORTG_1_4 (0 << 2)
  134 +#endif
  135 +#ifdef CONFIG_GPIO_HYST_PORTG_5_6
  136 +#define HYST_PORTG_5_6 (1 << 4)
  137 +#else
  138 +#define HYST_PORTG_5_6 (0 << 4)
  139 +#endif
  140 +#ifdef CONFIG_GPIO_HYST_PORTG_7_8
  141 +#define HYST_PORTG_7_8 (1 << 6)
  142 +#else
  143 +#define HYST_PORTG_7_8 (0 << 6)
  144 +#endif
  145 +#ifdef CONFIG_GPIO_HYST_PORTG_9
  146 +#define HYST_PORTG_9 (1 << 8)
  147 +#else
  148 +#define HYST_PORTG_9 (0 << 8)
  149 +#endif
  150 +#ifdef CONFIG_GPIO_HYST_PORTG_10
  151 +#define HYST_PORTG_10 (1 << 10)
  152 +#else
  153 +#define HYST_PORTG_10 (0 << 10)
  154 +#endif
  155 +#ifdef CONFIG_GPIO_HYST_PORTG_11_13
  156 +#define HYST_PORTG_11_13 (1 << 12)
  157 +#else
  158 +#define HYST_PORTG_11_13 (0 << 12)
  159 +#endif
  160 +#ifdef CONFIG_GPIO_HYST_PORTG_14_15
  161 +#define HYST_PORTG_14_15 (1 << 14)
  162 +#else
  163 +#define HYST_PORTG_14_15 (0 << 14)
  164 +#endif
  165 +
  166 +#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
  167 + HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
  168 + HYST_PORTG_11_13 | HYST_PORTG_14_15)
  169 +
  170 +#ifdef CONFIG_GPIO_HYST_PORTH_0_7
  171 +#define HYST_PORTH_0_7 (1 << 0)
  172 +#else
  173 +#define HYST_PORTH_0_7 (0 << 0)
  174 +#endif
  175 +
  176 +#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
  177 +
  178 +#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
  179 +#define HYST_NMI_RST_BMODE (1 << 2)
  180 +#else
  181 +#define HYST_NMI_RST_BMODE (0 << 2)
  182 +#endif
  183 +#ifdef CONFIG_NONEGPIO_HYST_JTAG
  184 +#define HYST_JTAG (1 << 4)
  185 +#else
  186 +#define HYST_JTAG (0 << 4)
  187 +#endif
  188 +
  189 +#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
  190 +#define HYST_NONEGPIO_MASK (0x3C)
  191 +#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
  192 +
88 193 #ifdef CONFIG_BF518
89 194 #define CPU "BF518"
90 195 #define CPUID 0x27e8
arch/blackfin/mach-bf527/Kconfig
Diff comments   View file @ 7a4a207
... ... @@ -79,6 +79,72 @@
79 79 PORT H
80 80 endchoice
81 81  
  82 +comment "Hysteresis/Schmitt Trigger Control"
  83 +config BFIN_HYSTERESIS_CONTROL
  84 + bool "Enable Hysteresis Control"
  85 + help
  86 + The ADSP-BF52x allows to control input hysteresis for Port F,
  87 + Port G and Port H and other processor signal inputs.
  88 + The Schmitt trigger enables can be set only for pin groups.
  89 + Saying Y will overwrite the default reset or boot loader
  90 + initialization.
  91 +
  92 +menu "PORT F"
  93 + depends on BFIN_HYSTERESIS_CONTROL
  94 +config GPIO_HYST_PORTF_0_7
  95 + bool "Enable Hysteresis on PORTF {0...7}"
  96 +config GPIO_HYST_PORTF_8_9
  97 + bool "Enable Hysteresis on PORTF {8, 9}"
  98 +config GPIO_HYST_PORTF_10
  99 + bool "Enable Hysteresis on PORTF 10"
  100 +config GPIO_HYST_PORTF_11
  101 + bool "Enable Hysteresis on PORTF 11"
  102 +config GPIO_HYST_PORTF_12_13
  103 + bool "Enable Hysteresis on PORTF {12, 13}"
  104 +config GPIO_HYST_PORTF_14_15
  105 + bool "Enable Hysteresis on PORTF {14, 15}"
  106 +endmenu
  107 +
  108 +menu "PORT G"
  109 + depends on BFIN_HYSTERESIS_CONTROL
  110 +config GPIO_HYST_PORTG_0
  111 + bool "Enable Hysteresis on PORTG 0"
  112 +config GPIO_HYST_PORTG_1_4
  113 + bool "Enable Hysteresis on PORTG {1...4}"
  114 +config GPIO_HYST_PORTG_5_6
  115 + bool "Enable Hysteresis on PORTG {5, 6}"
  116 +config GPIO_HYST_PORTG_7_8
  117 + bool "Enable Hysteresis on PORTG {7, 8}"
  118 +config GPIO_HYST_PORTG_9
  119 + bool "Enable Hysteresis on PORTG 9"
  120 +config GPIO_HYST_PORTG_10
  121 + bool "Enable Hysteresis on PORTG 10"
  122 +config GPIO_HYST_PORTG_11_13
  123 + bool "Enable Hysteresis on PORTG {11...13}"
  124 +config GPIO_HYST_PORTG_14_15
  125 + bool "Enable Hysteresis on PORTG {14, 15}"
  126 +endmenu
  127 +
  128 +menu "PORT H"
  129 + depends on BFIN_HYSTERESIS_CONTROL
  130 +config GPIO_HYST_PORTH_0_7
  131 + bool "Enable Hysteresis on PORTH {0...7}"
  132 +config GPIO_HYST_PORTH_8
  133 + bool "Enable Hysteresis on PORTH 8"
  134 +config GPIO_HYST_PORTH_9_15
  135 + bool "Enable Hysteresis on PORTH {9...15}"
  136 +endmenu
  137 +
  138 +menu "None-GPIO"
  139 + depends on BFIN_HYSTERESIS_CONTROL
  140 +config NONEGPIO_HYST_TMR0_FS1_PPICLK
  141 + bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
  142 +config NONEGPIO_HYST_NMI_RST_BMODE
  143 + bool "Enable Hysteresis on {NMI, RESET, BMODE}"
  144 +config NONEGPIO_HYST_JTAG
  145 + bool "Enable Hysteresis on JTAG"
  146 +endmenu
  147 +
82 148 comment "Interrupt Priority Assignment"
83 149 menu "Priority"
84 150  
arch/blackfin/mach-bf527/include/mach/bf527.h
Diff comments   View file @ 7a4a207
... ... @@ -85,6 +85,126 @@
85 85  
86 86 #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
87 87  
  88 +/**************************** Hysteresis Settings ****************************/
  89 +
  90 +#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
  91 +#ifdef CONFIG_GPIO_HYST_PORTF_0_7
  92 +#define HYST_PORTF_0_7 (1 << 0)
  93 +#else
  94 +#define HYST_PORTF_0_7 (0 << 0)
  95 +#endif
  96 +#ifdef CONFIG_GPIO_HYST_PORTF_8_9
  97 +#define HYST_PORTF_8_9 (1 << 2)
  98 +#else
  99 +#define HYST_PORTF_8_9 (0 << 2)
  100 +#endif
  101 +#ifdef CONFIG_GPIO_HYST_PORTF_10
  102 +#define HYST_PORTF_10 (1 << 4)
  103 +#else
  104 +#define HYST_PORTF_10 (0 << 4)
  105 +#endif
  106 +#ifdef CONFIG_GPIO_HYST_PORTF_11
  107 +#define HYST_PORTF_11 (1 << 6)
  108 +#else
  109 +#define HYST_PORTF_11 (0 << 6)
  110 +#endif
  111 +#ifdef CONFIG_GPIO_HYST_PORTF_12_13
  112 +#define HYST_PORTF_12_13 (1 << 8)
  113 +#else
  114 +#define HYST_PORTF_12_13 (0 << 8)
  115 +#endif
  116 +#ifdef CONFIG_GPIO_HYST_PORTF_14_15
  117 +#define HYST_PORTF_14_15 (1 << 10)
  118 +#else
  119 +#define HYST_PORTF_14_15 (0 << 10)
  120 +#endif
  121 +
  122 +#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
  123 + HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
  124 +
  125 +#ifdef CONFIG_GPIO_HYST_PORTG_0
  126 +#define HYST_PORTG_0 (1 << 0)
  127 +#else
  128 +#define HYST_PORTG_0 (0 << 0)
  129 +#endif
  130 +#ifdef CONFIG_GPIO_HYST_PORTG_1_4
  131 +#define HYST_PORTG_1_4 (1 << 2)
  132 +#else
  133 +#define HYST_PORTG_1_4 (0 << 2)
  134 +#endif
  135 +#ifdef CONFIG_GPIO_HYST_PORTG_5_6
  136 +#define HYST_PORTG_5_6 (1 << 4)
  137 +#else
  138 +#define HYST_PORTG_5_6 (0 << 4)
  139 +#endif
  140 +#ifdef CONFIG_GPIO_HYST_PORTG_7_8
  141 +#define HYST_PORTG_7_8 (1 << 6)
  142 +#else
  143 +#define HYST_PORTG_7_8 (0 << 6)
  144 +#endif
  145 +#ifdef CONFIG_GPIO_HYST_PORTG_9
  146 +#define HYST_PORTG_9 (1 << 8)
  147 +#else
  148 +#define HYST_PORTG_9 (0 << 8)
  149 +#endif
  150 +#ifdef CONFIG_GPIO_HYST_PORTG_10
  151 +#define HYST_PORTG_10 (1 << 10)
  152 +#else
  153 +#define HYST_PORTG_10 (0 << 10)
  154 +#endif
  155 +#ifdef CONFIG_GPIO_HYST_PORTG_11_13
  156 +#define HYST_PORTG_11_13 (1 << 12)
  157 +#else
  158 +#define HYST_PORTG_11_13 (0 << 12)
  159 +#endif
  160 +#ifdef CONFIG_GPIO_HYST_PORTG_14_15
  161 +#define HYST_PORTG_14_15 (1 << 14)
  162 +#else
  163 +#define HYST_PORTG_14_15 (0 << 14)
  164 +#endif
  165 +
  166 +#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
  167 + HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
  168 + HYST_PORTG_11_13 | HYST_PORTG_14_15)
  169 +
  170 +#ifdef CONFIG_GPIO_HYST_PORTH_0_7
  171 +#define HYST_PORTH_0_7 (1 << 0)
  172 +#else
  173 +#define HYST_PORTH_0_7 (0 << 0)
  174 +#endif
  175 +#ifdef CONFIG_GPIO_HYST_PORTH_8
  176 +#define HYST_PORTH_8 (1 << 2)
  177 +#else
  178 +#define HYST_PORTH_8 (0 << 2)
  179 +#endif
  180 +#ifdef CONFIG_GPIO_HYST_PORTH_9_15
  181 +#define HYST_PORTH_9_15 (1 << 4)
  182 +#else
  183 +#define HYST_PORTH_9_15 (0 << 4)
  184 +#endif
  185 +
  186 +#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
  187 +
  188 +#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
  189 +#define HYST_TMR0_FS1_PPICLK (1 << 0)
  190 +#else
  191 +#define HYST_TMR0_FS1_PPICLK (0 << 0)
  192 +#endif
  193 +#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
  194 +#define HYST_NMI_RST_BMODE (1 << 2)
  195 +#else
  196 +#define HYST_NMI_RST_BMODE (0 << 2)
  197 +#endif
  198 +#ifdef CONFIG_NONEGPIO_HYST_JTAG
  199 +#define HYST_JTAG (1 << 4)
  200 +#else
  201 +#define HYST_JTAG (0 << 4)
  202 +#endif
  203 +
  204 +#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
  205 +#define HYST_NONEGPIO_MASK (0x3F)
  206 +#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
  207 +
88 208 #ifdef CONFIG_BF527
89 209 #define CPU "BF527"
90 210 #define CPUID 0x27e0