Eric Lee / linux-smarc-t335x-v3.2

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Commit 7a4a31c40f21bdc119f48ab91363d35e7d4267c2

Authored by Vaibhav Hiremath
1 parent bef9c578f3
Exists in master

arm:omap:am33xx: Cleanup in HWMOD data 

Due to cleanup in clock tree, hwmod data also needs some cleanup.

Showing 4 changed files with 645 additions and 597 deletions Side-by-side Diff

arch/arm/mach-omap2/devices.c
Diff comments   View file @ 7a4a31c
... ... @@ -1199,13 +1199,13 @@
1199 1199 .flags = IORESOURCE_IRQ,
1200 1200 },
1201 1201 {
1202   - .start = AM33XX_IRQ_DMTIMER_5,
1203   - .end = AM33XX_IRQ_DMTIMER_5,
  1202 + .start = AM33XX_IRQ_DMTIMER5,
  1203 + .end = AM33XX_IRQ_DMTIMER5,
1204 1204 .flags = IORESOURCE_IRQ,
1205 1205 },
1206 1206 {
1207   - .start = AM33XX_IRQ_DMTIMER_6,
1208   - .end = AM33XX_IRQ_DMTIMER_6,
  1207 + .start = AM33XX_IRQ_DMTIMER6,
  1208 + .end = AM33XX_IRQ_DMTIMER6,
1209 1209 .flags = IORESOURCE_IRQ,
1210 1210 },
1211 1211 {
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
Diff comments   View file @ 7a4a31c
Changes suppressed. Click to show
... ... @@ -10,7 +10,7 @@
10 10 *
11 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 12 * kind, whether express or implied; without even the implied warranty
13   - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 * GNU General Public License for more details.
15 15 */
16 16  
17 17  
18 18  
... ... @@ -74,23 +74,23 @@
74 74  
75 75 /* MPU -> L3_SLOW Peripheral interface */
76 76 static struct omap_hwmod_ocp_if am33xx_mpu__l3_slow = {
77   - .master = &am33xx_mpu_hwmod,
78   - .slave = &am33xx_l3slow_hwmod,
79   - .user = OCP_USER_MPU,
  77 + .master = &am33xx_mpu_hwmod,
  78 + .slave = &am33xx_l3slow_hwmod,
  79 + .user = OCP_USER_MPU,
80 80 };
81 81  
82 82 /* L3 SLOW -> L4_PER Peripheral interface */
83 83 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_per = {
84   - .master = &am33xx_l3slow_hwmod,
85   - .slave = &am33xx_l4per_hwmod,
86   - .user = OCP_USER_MPU,
  84 + .master = &am33xx_l3slow_hwmod,
  85 + .slave = &am33xx_l4per_hwmod,
  86 + .user = OCP_USER_MPU,
87 87 };
88 88  
89 89 /* L3 SLOW -> L4_WKUP Peripheral interface */
90 90 static struct omap_hwmod_ocp_if am33xx_l3_slow__l4_wkup = {
91   - .master = &am33xx_l3slow_hwmod,
92   - .slave = &am33xx_l4wkup_hwmod,
93   - .user = OCP_USER_MPU,
  91 + .master = &am33xx_l3slow_hwmod,
  92 + .slave = &am33xx_l4wkup_hwmod,
  93 + .user = OCP_USER_MPU,
94 94 };
95 95  
96 96 /* Master interfaces on the L4_WKUP interconnect */
97 97  
98 98  
99 99  
100 100  
101 101  
102 102  
103 103  
... ... @@ -105,65 +105,65 @@
105 105 };
106 106  
107 107 static struct omap_hwmod am33xx_l3slow_hwmod = {
108   - .name = "l3_slow",
109   - .class = &l3_hwmod_class,
  108 + .name = "l3_slow",
  109 + .class = &l3_hwmod_class,
110 110 .clkdm_name = "l3s_clkdm",
111 111 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
112   - .masters = am33xx_l3_slow_masters,
113   - .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
114   - .slaves = am33xx_l3_slow_slaves,
115   - .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
  112 + .masters = am33xx_l3_slow_masters,
  113 + .masters_cnt = ARRAY_SIZE(am33xx_l3_slow_masters),
  114 + .slaves = am33xx_l3_slow_slaves,
  115 + .slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
116 116 };
117 117  
118 118 /* L4 PER -> GPIO2 */
119 119 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
120 120 {
121   - .pa_start = AM33XX_GPIO1_BASE,
122   - .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
123   - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  121 + .pa_start = AM33XX_GPIO1_BASE,
  122 + .pa_end = AM33XX_GPIO1_BASE + SZ_4K - 1,
  123 + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
124 124 },
125 125 };
126 126  
127 127 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
128   - .master = &am33xx_l4per_hwmod,
129   - .slave = &am33xx_gpio1_hwmod,
130   - .clk = "l4ls_fck",
131   - .addr = am33xx_gpio1_addrs,
132   - .user = OCP_USER_MPU | OCP_USER_SDMA,
  128 + .master = &am33xx_l4per_hwmod,
  129 + .slave = &am33xx_gpio1_hwmod,
  130 + .clk = "l4ls_gclk",
  131 + .addr = am33xx_gpio1_addrs,
  132 + .user = OCP_USER_MPU | OCP_USER_SDMA,
133 133 };
134 134  
135 135 /* L4 PER -> GPIO3 */
136 136 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
137 137 {
138   - .pa_start = AM33XX_GPIO2_BASE,
139   - .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
140   - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  138 + .pa_start = AM33XX_GPIO2_BASE,
  139 + .pa_end = AM33XX_GPIO2_BASE + SZ_4K - 1,
  140 + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
141 141 },
142 142 };
143 143  
144 144 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
145   - .master = &am33xx_l4per_hwmod,
146   - .slave = &am33xx_gpio2_hwmod,
147   - .clk = "l4ls_fck",
148   - .addr = am33xx_gpio2_addrs,
149   - .user = OCP_USER_MPU | OCP_USER_SDMA,
  145 + .master = &am33xx_l4per_hwmod,
  146 + .slave = &am33xx_gpio2_hwmod,
  147 + .clk = "l4ls_gclk",
  148 + .addr = am33xx_gpio2_addrs,
  149 + .user = OCP_USER_MPU | OCP_USER_SDMA,
150 150 };
151 151  
152 152 /* L4 PER -> GPIO4 */
153 153 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
154 154 {
155   - .pa_start = AM33XX_GPIO3_BASE,
156   - .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
157   - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  155 + .pa_start = AM33XX_GPIO3_BASE,
  156 + .pa_end = AM33XX_GPIO3_BASE + SZ_4K - 1,
  157 + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
158 158 },
159 159 };
160 160  
161 161 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
162   - .master = &am33xx_l4per_hwmod,
163   - .slave = &am33xx_gpio3_hwmod,
164   - .clk = "l4ls_fck",
165   - .addr = am33xx_gpio3_addrs,
166   - .user = OCP_USER_MPU | OCP_USER_SDMA,
  162 + .master = &am33xx_l4per_hwmod,
  163 + .slave = &am33xx_gpio3_hwmod,
  164 + .clk = "l4ls_gclk",
  165 + .addr = am33xx_gpio3_addrs,
  166 + .user = OCP_USER_MPU | OCP_USER_SDMA,
167 167 };
168 168  
169 169 /* Master interfaces on the L4_PER interconnect */
170 170  
171 171  
172 172  
173 173  
174 174  
... ... @@ -178,47 +178,47 @@
178 178 };
179 179  
180 180 static struct omap_hwmod am33xx_l4per_hwmod = {
181   - .name = "l4_per",
182   - .class = &l4_hwmod_class,
  181 + .name = "l4_per",
  182 + .class = &l4_hwmod_class,
183 183 .clkdm_name = "l4ls_clkdm",
184 184 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
185   - .masters = am33xx_l4_per_masters,
186   - .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
187   - .slaves = am33xx_l4_per_slaves,
188   - .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
  185 + .masters = am33xx_l4_per_masters,
  186 + .masters_cnt = ARRAY_SIZE(am33xx_l4_per_masters),
  187 + .slaves = am33xx_l4_per_slaves,
  188 + .slaves_cnt = ARRAY_SIZE(am33xx_l4_per_slaves),
189 189 };
190 190  
191 191 /* L4 WKUP -> I2C1 */
192 192 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
193 193 {
194   - .pa_start = 0x44E0B000,
195   - .pa_end = 0x44E0B000 + SZ_4K - 1,
196   - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  194 + .pa_start = AM33XX_I2C0_BASE,
  195 + .pa_end = AM33XX_I2C0_BASE + SZ_4K - 1,
  196 + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
197 197 },
198 198 };
199 199  
200 200 static struct omap_hwmod_ocp_if am33xx_l4_wkup_i2c1 = {
201   - .master = &am33xx_l4wkup_hwmod,
202   - .slave = &am33xx_i2c1_hwmod,
203   - .addr = am33xx_i2c1_addr_space,
204   - .user = OCP_USER_MPU,
  201 + .master = &am33xx_l4wkup_hwmod,
  202 + .slave = &am33xx_i2c1_hwmod,
  203 + .addr = am33xx_i2c1_addr_space,
  204 + .user = OCP_USER_MPU,
205 205 };
206 206  
207 207 /* L4 WKUP -> GPIO1 */
208 208 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
209 209 {
210   - .pa_start = AM33XX_GPIO0_BASE,
211   - .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
212   - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  210 + .pa_start = AM33XX_GPIO0_BASE,
  211 + .pa_end = AM33XX_GPIO0_BASE + SZ_4K - 1,
  212 + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
213 213 },
214 214 };
215 215  
216 216 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
217   - .master = &am33xx_l4wkup_hwmod,
218   - .slave = &am33xx_gpio0_hwmod,
219   - .clk = "l4ls_fck",
220   - .addr = am33xx_gpio0_addrs,
221   - .user = OCP_USER_MPU | OCP_USER_SDMA,
  217 + .master = &am33xx_l4wkup_hwmod,
  218 + .slave = &am33xx_gpio0_hwmod,
  219 + .clk = "l4ls_gclk",
  220 + .addr = am33xx_gpio0_addrs,
  221 + .user = OCP_USER_MPU | OCP_USER_SDMA,
222 222 };
223 223  
224 224 /* Master interfaces on the L4_WKUP interconnect */
225 225  
226 226  
227 227  
228 228  
229 229  
... ... @@ -231,35 +231,35 @@
231 231 };
232 232  
233 233 static struct omap_hwmod am33xx_l4wkup_hwmod = {
234   - .name = "l4_wkup",
235   - .class = &l4_hwmod_class,
  234 + .name = "l4_wkup",
  235 + .class = &l4_hwmod_class,
236 236 .clkdm_name = "l4_wkup_clkdm",
237 237 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
238   - .masters = am33xx_l4_wkup_masters,
239   - .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
240   - .slaves = am33xx_l4_wkup_slaves,
241   - .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
  238 + .masters = am33xx_l4_wkup_masters,
  239 + .masters_cnt = ARRAY_SIZE(am33xx_l4_wkup_masters),
  240 + .slaves = am33xx_l4_wkup_slaves,
  241 + .slaves_cnt = ARRAY_SIZE(am33xx_l4_wkup_slaves),
242 242 };
243 243  
244 244 /* 'adc_tsc' class */
245 245 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
246   - .name = "adc_tsc",
  246 + .name = "adc_tsc",
247 247 };
248 248  
249 249 /* adc_tsc */
250 250 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
251   - { .irq = 115 },
  251 + { .irq = AM33XX_IRQ_TSC },
252 252 { .irq = -1 }
253 253 };
254 254  
255 255 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
256 256 .name = "adc_tsc",
257 257 .class = &am33xx_adc_tsc_hwmod_class,
258   - .mpu_irqs = am33xx_adc_tsc_irqs,
  258 + .mpu_irqs = am33xx_adc_tsc_irqs,
259 259 .main_clk = "adc_tsc_fck",
260 260 .clkdm_name = "l4_wkup_clkdm",
261   - .prcm = {
262   - .omap4 = {
  261 + .prcm = {
  262 + .omap4 = {
263 263 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
264 264 .modulemode = MODULEMODE_SWCTRL,
265 265 },
266 266  
267 267  
268 268  
... ... @@ -268,23 +268,23 @@
268 268  
269 269 /* 'aes' class */
270 270 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
271   - .name = "aes",
  271 + .name = "aes",
272 272 };
273 273  
274 274 /* aes0 */
275 275 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
276   - { .irq = 102 },
277   - { .irq = -1 }
  276 + { .irq = AM33XX_IRQ_AESEIP36t0_S },
  277 + { .irq = -1 },
278 278 };
279 279  
280 280 static struct omap_hwmod am33xx_aes0_hwmod = {
281 281 .name = "aes0",
282 282 .class = &am33xx_aes_hwmod_class,
283   - .mpu_irqs = am33xx_aes0_irqs,
  283 + .mpu_irqs = am33xx_aes0_irqs,
284 284 .main_clk = "aes0_fck",
285 285 .clkdm_name = "l3_clkdm",
286   - .prcm = {
287   - .omap4 = {
  286 + .prcm = {
  287 + .omap4 = {
288 288 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
289 289 .modulemode = MODULEMODE_SWCTRL,
290 290 },
... ... @@ -293,7 +293,7 @@
293 293  
294 294 /* 'cefuse' class */
295 295 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
296   - .name = "cefuse",
  296 + .name = "cefuse",
297 297 };
298 298  
299 299 /* cefuse */
... ... @@ -302,8 +302,8 @@
302 302 .class = &am33xx_cefuse_hwmod_class,
303 303 .main_clk = "cefuse_fck",
304 304 .clkdm_name = "l4_cefuse_clkdm",
305   - .prcm = {
306   - .omap4 = {
  305 + .prcm = {
  306 + .omap4 = {
307 307 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
308 308 .modulemode = MODULEMODE_SWCTRL,
309 309 },
310 310  
311 311  
... ... @@ -312,17 +312,17 @@
312 312  
313 313 /* 'clkdiv32k' class */
314 314 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
315   - .name = "clkdiv32k",
  315 + .name = "clkdiv32k",
316 316 };
317 317  
318 318 /* clkdiv32k */
319 319 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
320 320 .name = "clkdiv32k",
321 321 .class = &am33xx_clkdiv32k_hwmod_class,
322   - .main_clk = "clkdiv32k_fck",
  322 + .main_clk = "clkdiv32k_ick",
323 323 .clkdm_name = "clk_24mhz_clkdm",
324   - .prcm = {
325   - .omap4 = {
  324 + .prcm = {
  325 + .omap4 = {
326 326 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
327 327 .modulemode = MODULEMODE_SWCTRL,
328 328 },
329 329  
330 330  
331 331  
332 332  
333 333  
334 334  
335 335  
... ... @@ -332,43 +332,43 @@
332 332  
333 333 /* 'control' class */
334 334 static struct omap_hwmod_class am33xx_control_hwmod_class = {
335   - .name = "control",
  335 + .name = "control",
336 336 };
337 337  
338 338 /* control */
339 339 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
340   - { .irq = 8 },
341   - { .irq = -1 }
  340 + { .irq = AM33XX_IRQ_CONTROL_PLATFORM },
  341 + { .irq = -1 },
342 342 };
343 343  
344 344 static struct omap_hwmod am33xx_control_hwmod = {
345 345 .name = "control",
346 346 .class = &am33xx_control_hwmod_class,
347   - .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
348   - .mpu_irqs = am33xx_control_irqs,
  347 + .mpu_irqs = am33xx_control_irqs,
349 348 .main_clk = "control_fck",
350 349 .clkdm_name = "l4_wkup_clkdm",
351   - .prcm = {
352   - .omap4 = {
  350 + .prcm = {
  351 + .omap4 = {
353 352 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
354 353 .modulemode = MODULEMODE_SWCTRL,
355 354 },
356 355 },
  356 + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
357 357 };
358 358  
359 359 /* 'cpgmac0' class */
360 360 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
361   - .name = "cpgmac0",
  361 + .name = "cpgmac0",
362 362 };
363 363  
364 364 /* cpgmac0 */
365 365 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
366 366 .name = "cpgmac0",
367 367 .class = &am33xx_cpgmac0_hwmod_class,
368   - .main_clk = "cpgmac0_fck",
  368 + .main_clk = "cpgmac0_ick",
369 369 .clkdm_name = "cpsw_125mhz_clkdm",
370   - .prcm = {
371   - .omap4 = {
  370 + .prcm = {
  371 + .omap4 = {
372 372 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
373 373 .modulemode = MODULEMODE_SWCTRL,
374 374 },
375 375  
376 376  
377 377  
... ... @@ -377,23 +377,23 @@
377 377  
378 378 /* 'dcan' class */
379 379 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
380   - .name = "dcan",
  380 + .name = "dcan",
381 381 };
382 382  
383 383 /* dcan0 */
384 384 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
385   - { .irq = 52 },
386   - { .irq = -1 }
  385 + { .irq = AM33XX_IRQ_DCAN0_0 },
  386 + { .irq = -1 },
387 387 };
388 388  
389 389 static struct omap_hwmod am33xx_dcan0_hwmod = {
390 390 .name = "dcan0",
391 391 .class = &am33xx_dcan_hwmod_class,
392   - .mpu_irqs = am33xx_dcan0_irqs,
  392 + .mpu_irqs = am33xx_dcan0_irqs,
393 393 .main_clk = "dcan0_fck",
394 394 .clkdm_name = "l4ls_clkdm",
395   - .prcm = {
396   - .omap4 = {
  395 + .prcm = {
  396 + .omap4 = {
397 397 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
398 398 .modulemode = MODULEMODE_SWCTRL,
399 399 },
400 400  
401 401  
... ... @@ -402,17 +402,17 @@
402 402  
403 403 /* dcan1 */
404 404 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
405   - { .irq = 55 },
406   - { .irq = -1 }
  405 + { .irq = AM33XX_IRQ_DCAN1_0 },
  406 + { .irq = -1 },
407 407 };
408 408 static struct omap_hwmod am33xx_dcan1_hwmod = {
409 409 .name = "dcan1",
410 410 .class = &am33xx_dcan_hwmod_class,
411   - .mpu_irqs = am33xx_dcan1_irqs,
  411 + .mpu_irqs = am33xx_dcan1_irqs,
412 412 .main_clk = "dcan1_fck",
413 413 .clkdm_name = "l4ls_clkdm",
414   - .prcm = {
415   - .omap4 = {
  414 + .prcm = {
  415 + .omap4 = {
416 416 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
417 417 .modulemode = MODULEMODE_SWCTRL,
418 418 },
419 419  
420 420  
... ... @@ -421,17 +421,17 @@
421 421  
422 422 /* 'debugss' class */
423 423 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
424   - .name = "debugss",
  424 + .name = "debugss",
425 425 };
426 426  
427 427 /* debugss */
428 428 static struct omap_hwmod am33xx_debugss_hwmod = {
429 429 .name = "debugss",
430 430 .class = &am33xx_debugss_hwmod_class,
431   - .main_clk = "debugss_fck",
  431 + .main_clk = "debugss_ick",
432 432 .clkdm_name = "l3_aon_clkdm",
433   - .prcm = {
434   - .omap4 = {
  433 + .prcm = {
  434 + .omap4 = {
435 435 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
436 436 .modulemode = MODULEMODE_SWCTRL,
437 437 },
... ... @@ -491,8 +491,8 @@
491 491 .clkdm_name = "l4ls_clkdm",
492 492 .slaves = am33xx_elm_slaves,
493 493 .slaves_cnt = ARRAY_SIZE(am33xx_elm_slaves),
494   - .prcm = {
495   - .omap4 = {
  494 + .prcm = {
  495 + .omap4 = {
496 496 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
497 497 .modulemode = MODULEMODE_SWCTRL,
498 498 },
... ... @@ -501,7 +501,7 @@
501 501  
502 502 /* 'emif_fw' class */
503 503 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
504   - .name = "emif_fw",
  504 + .name = "emif_fw",
505 505 };
506 506  
507 507 /* emif_fw */
... ... @@ -510,8 +510,8 @@
510 510 .class = &am33xx_emif_fw_hwmod_class,
511 511 .main_clk = "emif_fw_fck",
512 512 .clkdm_name = "l4fw_clkdm",
513   - .prcm = {
514   - .omap4 = {
  513 + .prcm = {
  514 + .omap4 = {
515 515 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
516 516 .modulemode = MODULEMODE_SWCTRL,
517 517 },
... ... @@ -521,7 +521,7 @@
521 521  
522 522 /* 'epwmss' class */
523 523 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
524   - .name = "epwmss",
  524 + .name = "epwmss",
525 525 };
526 526  
527 527 /* epwmss0 */
... ... @@ -530,8 +530,8 @@
530 530 .class = &am33xx_epwmss_hwmod_class,
531 531 .main_clk = "epwmss0_fck",
532 532 .clkdm_name = "l4ls_clkdm",
533   - .prcm = {
534   - .omap4 = {
  533 + .prcm = {
  534 + .omap4 = {
535 535 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
536 536 .modulemode = MODULEMODE_SWCTRL,
537 537 },
... ... @@ -544,8 +544,8 @@
544 544 .class = &am33xx_epwmss_hwmod_class,
545 545 .main_clk = "epwmss1_fck",
546 546 .clkdm_name = "l4ls_clkdm",
547   - .prcm = {
548   - .omap4 = {
  547 + .prcm = {
  548 + .omap4 = {
549 549 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
550 550 .modulemode = MODULEMODE_SWCTRL,
551 551 },
... ... @@ -558,8 +558,8 @@
558 558 .class = &am33xx_epwmss_hwmod_class,
559 559 .main_clk = "epwmss2_fck",
560 560 .clkdm_name = "l4ls_clkdm",
561   - .prcm = {
562   - .omap4 = {
  561 + .prcm = {
  562 + .omap4 = {
563 563 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
564 564 .modulemode = MODULEMODE_SWCTRL,
565 565 },
566 566  
567 567  
568 568  
569 569  
570 570  
... ... @@ -567,34 +567,34 @@
567 567 };
568 568  
569 569 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
570   - .rev_offs = 0x0000,
571   - .sysc_offs = 0x0010,
572   - .syss_offs = 0x0114,
573   - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
  570 + .rev_offs = 0x0000,
  571 + .sysc_offs = 0x0010,
  572 + .syss_offs = 0x0114,
  573 + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
574 574 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
575 575 SYSS_HAS_RESET_STATUS),
576   - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  576 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
577 577 SIDLE_SMART_WKUP),
578   - .sysc_fields = &omap_hwmod_sysc_type1,
  578 + .sysc_fields = &omap_hwmod_sysc_type1,
579 579 };
580 580  
581 581 /* 'gpio' class */
582 582 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
583   - .name = "gpio",
584   - .sysc = &am33xx_gpio_sysc,
585   - .rev = 2,
  583 + .name = "gpio",
  584 + .sysc = &am33xx_gpio_sysc,
  585 + .rev = 2,
586 586 };
587 587  
588 588 /* gpio dev_attr */
589 589 static struct omap_gpio_dev_attr gpio_dev_attr = {
590   - .bank_width = 32,
591   - .dbck_flag = true,
  590 + .bank_width = 32,
  591 + .dbck_flag = true,
592 592 };
593 593  
594 594 /* gpio0 */
595 595 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
596   - { .irq = 96 },
597   - { .irq = -1 }
  596 + { .irq = AM33XX_IRQ_GPIO0_1 },
  597 + { .irq = -1 },
598 598 };
599 599  
600 600 /* gpio0 slave ports */
601 601  
602 602  
603 603  
... ... @@ -611,26 +611,26 @@
611 611 .name = "gpio1",
612 612 .class = &am33xx_gpio_hwmod_class,
613 613 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
614   - .mpu_irqs = am33xx_gpio0_irqs,
615   - .main_clk = "gpio0_fck",
  614 + .mpu_irqs = am33xx_gpio0_irqs,
  615 + .main_clk = "gpio0_ick",
616 616 .clkdm_name = "l4_wkup_clkdm",
617   - .prcm = {
618   - .omap4 = {
  617 + .prcm = {
  618 + .omap4 = {
619 619 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
620 620 .modulemode = MODULEMODE_SWCTRL,
621 621 },
622 622 },
623   - .opt_clks = gpio0_opt_clks,
624   - .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
625   - .dev_attr = &gpio_dev_attr,
626   - .slaves = am33xx_gpio0_slaves,
627   - .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
  623 + .opt_clks = gpio0_opt_clks,
  624 + .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
  625 + .dev_attr = &gpio_dev_attr,
  626 + .slaves = am33xx_gpio0_slaves,
  627 + .slaves_cnt = ARRAY_SIZE(am33xx_gpio0_slaves),
628 628 };
629 629  
630 630 /* gpio1 */
631 631 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
632   - { .irq = 98 },
633   - { .irq = -1 }
  632 + { .irq = AM33XX_IRQ_GPIO1_1 },
  633 + { .irq = -1 },
634 634 };
635 635  
636 636 /* gpio1 slave ports */
637 637  
638 638  
639 639  
... ... @@ -646,26 +646,26 @@
646 646 .name = "gpio2",
647 647 .class = &am33xx_gpio_hwmod_class,
648 648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
649   - .mpu_irqs = am33xx_gpio1_irqs,
650   - .main_clk = "gpio1_fck",
  649 + .mpu_irqs = am33xx_gpio1_irqs,
  650 + .main_clk = "gpio1_ick",
651 651 .clkdm_name = "l4ls_clkdm",
652   - .prcm = {
653   - .omap4 = {
  652 + .prcm = {
  653 + .omap4 = {
654 654 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
655 655 .modulemode = MODULEMODE_SWCTRL,
656 656 },
657 657 },
658   - .opt_clks = gpio1_opt_clks,
659   - .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
660   - .dev_attr = &gpio_dev_attr,
661   - .slaves = am33xx_gpio1_slaves,
662   - .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
  658 + .opt_clks = gpio1_opt_clks,
  659 + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  660 + .dev_attr = &gpio_dev_attr,
  661 + .slaves = am33xx_gpio1_slaves,
  662 + .slaves_cnt = ARRAY_SIZE(am33xx_gpio1_slaves),
663 663 };
664 664  
665 665 /* gpio2 */
666 666 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
667   - { .irq = 32 },
668   - { .irq = -1 }
  667 + { .irq = AM33XX_IRQ_GPIO2_1 },
  668 + { .irq = -1 },
669 669 };
670 670  
671 671 /* gpio2 slave ports */
672 672  
673 673  
674 674  
... ... @@ -682,26 +682,26 @@
682 682 .name = "gpio3",
683 683 .class = &am33xx_gpio_hwmod_class,
684 684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
685   - .mpu_irqs = am33xx_gpio2_irqs,
686   - .main_clk = "gpio2_fck",
  685 + .mpu_irqs = am33xx_gpio2_irqs,
  686 + .main_clk = "gpio2_ick",
687 687 .clkdm_name = "l4ls_clkdm",
688   - .prcm = {
689   - .omap4 = {
  688 + .prcm = {
  689 + .omap4 = {
690 690 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
691 691 .modulemode = MODULEMODE_SWCTRL,
692 692 },
693 693 },
694   - .opt_clks = gpio2_opt_clks,
695   - .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
696   - .dev_attr = &gpio_dev_attr,
697   - .slaves = am33xx_gpio2_slaves,
698   - .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
  694 + .opt_clks = gpio2_opt_clks,
  695 + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
  696 + .dev_attr = &gpio_dev_attr,
  697 + .slaves = am33xx_gpio2_slaves,
  698 + .slaves_cnt = ARRAY_SIZE(am33xx_gpio2_slaves),
699 699 };
700 700  
701 701 /* gpio3 */
702 702 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
703   - { .irq = 62 },
704   - { .irq = -1 }
  703 + { .irq = AM33XX_IRQ_GPIO3_1 },
  704 + { .irq = -1 },
705 705 };
706 706  
707 707 /* gpio3 slave ports */
708 708  
709 709  
710 710  
... ... @@ -718,26 +718,26 @@
718 718 .name = "gpio4",
719 719 .class = &am33xx_gpio_hwmod_class,
720 720 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
721   - .mpu_irqs = am33xx_gpio3_irqs,
722   - .main_clk = "gpio3_fck",
  721 + .mpu_irqs = am33xx_gpio3_irqs,
  722 + .main_clk = "gpio3_ick",
723 723 .clkdm_name = "l4ls_clkdm",
724   - .prcm = {
725   - .omap4 = {
  724 + .prcm = {
  725 + .omap4 = {
726 726 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
727 727 .modulemode = MODULEMODE_SWCTRL,
728 728 },
729 729 },
730   - .opt_clks = gpio3_opt_clks,
731   - .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
732   - .dev_attr = &gpio_dev_attr,
733   - .slaves = am33xx_gpio3_slaves,
734   - .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
  730 + .opt_clks = gpio3_opt_clks,
  731 + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
  732 + .dev_attr = &gpio_dev_attr,
  733 + .slaves = am33xx_gpio3_slaves,
  734 + .slaves_cnt = ARRAY_SIZE(am33xx_gpio3_slaves),
735 735 };
736 736  
737 737 /* 'gpmc' class */
738 738  
739 739 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
740   - .name = "gpmc",
  740 + .name = "gpmc",
741 741 };
742 742  
743 743 /* gpmc */
... ... @@ -746,8 +746,8 @@
746 746 .class = &am33xx_gpmc_hwmod_class,
747 747 .main_clk = "gpmc_fck",
748 748 .clkdm_name = "l3s_clkdm",
749   - .prcm = {
750   - .omap4 = {
  749 + .prcm = {
  750 + .omap4 = {
751 751 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
752 752 .modulemode = MODULEMODE_SWCTRL,
753 753 },
754 754  
755 755  
756 756  
757 757  
758 758  
759 759  
... ... @@ -756,33 +756,32 @@
756 756  
757 757 /* 'i2c' class */
758 758  
759   -static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
  759 +static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
760 760 .sysc_offs = 0x0010,
761 761 .syss_offs = 0x0090,
762 762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
763   - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
764   - SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  763 + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  764 + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
765 765 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
766   - SIDLE_SMART_WKUP),
  766 + SIDLE_SMART_WKUP),
767 767 .sysc_fields = &omap_hwmod_sysc_type1,
768 768 };
769 769  
  770 +static struct omap_i2c_dev_attr i2c_dev_attr = {
  771 + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
  772 +};
770 773  
771 774 static struct omap_hwmod_class i2c_class = {
772   - .name = "i2c",
773   - .sysc = &omap44xx_i2c_sysc,
774   - .rev = OMAP_I2C_IP_VERSION_2,
775   - .reset = &omap_i2c_reset,
  775 + .name = "i2c",
  776 + .sysc = &am33xx_i2c_sysc,
  777 + .rev = OMAP_I2C_IP_VERSION_2,
  778 + .reset = &omap_i2c_reset,
776 779 };
777 780  
778   -static struct omap_i2c_dev_attr i2c_dev_attr = {
779   - .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
780   -};
781   -
782 781 /* I2C1 */
783 782 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
784   - { .irq = 70 },
785   - { .irq = -1 }
  783 + { .irq = AM33XX_IRQ_MSHSI2COCP0 },
  784 + { .irq = -1 },
786 785 };
787 786  
788 787 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
789 788  
790 789  
791 790  
792 791  
793 792  
794 793  
... ... @@ -795,44 +794,44 @@
795 794 };
796 795  
797 796 static struct omap_hwmod am33xx_i2c1_hwmod = {
798   - .name = "i2c1",
799   - .flags = HWMOD_16BIT_REG,
800   - .mpu_irqs = i2c1_mpu_irqs,
801   - .sdma_reqs = i2c1_edma_reqs,
802   - .main_clk = "i2c1_fck",
  797 + .name = "i2c1",
  798 + .mpu_irqs = i2c1_mpu_irqs,
  799 + .sdma_reqs = i2c1_edma_reqs,
  800 + .main_clk = "i2c1_fck",
803 801 .clkdm_name = "l4_wkup_clkdm",
804   - .prcm = {
805   - .omap4 = {
  802 + .prcm = {
  803 + .omap4 = {
806 804 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
807 805 .modulemode = MODULEMODE_SWCTRL,
808 806 },
809 807 },
810   - .slaves = am33xx_i2c1_slaves,
811   - .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
812   - .class = &i2c_class,
  808 + .flags = HWMOD_16BIT_REG,
813 809 .dev_attr = &i2c_dev_attr,
  810 + .slaves = am33xx_i2c1_slaves,
  811 + .slaves_cnt = ARRAY_SIZE(am33xx_i2c1_slaves),
  812 + .class = &i2c_class,
814 813 };
815 814  
816 815 /* i2c2 */
817 816 /* l4 per -> i2c2 */
818 817 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
819 818 {
820   - .pa_start = 0x4802A000,
821   - .pa_end = 0x4802A000 + SZ_4K - 1,
822   - .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
  819 + .pa_start = AM33XX_I2C1_BASE,
  820 + .pa_end = AM33XX_I2C1_BASE + SZ_4K - 1,
  821 + .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
823 822 },
824 823 };
825 824  
826 825 static struct omap_hwmod_ocp_if am335_l4_per_i2c2 = {
827   - .master = &am33xx_l4per_hwmod,
828   - .slave = &am33xx_i2c2_hwmod,
829   - .addr = am33xx_i2c2_addr_space,
830   - .user = OCP_USER_MPU,
  826 + .master = &am33xx_l4per_hwmod,
  827 + .slave = &am33xx_i2c2_hwmod,
  828 + .addr = am33xx_i2c2_addr_space,
  829 + .user = OCP_USER_MPU,
831 830 };
832 831  
833 832 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
834   - { .irq = 71 },
835   - { .irq = -1 }
  833 + { .irq = AM33XX_IRQ_MSHSI2COCP1 },
  834 + { .irq = -1 },
836 835 };
837 836  
838 837 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
839 838  
840 839  
841 840  
... ... @@ -845,22 +844,22 @@
845 844 };
846 845  
847 846 static struct omap_hwmod am33xx_i2c2_hwmod = {
848   - .name = "i2c2",
849   - .flags = HWMOD_16BIT_REG,
850   - .mpu_irqs = i2c2_mpu_irqs,
851   - .sdma_reqs = i2c2_edma_reqs,
852   - .main_clk = "i2c2_fck",
  847 + .name = "i2c2",
  848 + .mpu_irqs = i2c2_mpu_irqs,
  849 + .sdma_reqs = i2c2_edma_reqs,
  850 + .main_clk = "i2c2_fck",
853 851 .clkdm_name = "l4ls_clkdm",
854   - .prcm = {
  852 + .prcm = {
855 853 .omap4 = {
856 854 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
857 855 .modulemode = MODULEMODE_SWCTRL,
858 856 },
859 857 },
860   - .slaves = am33xx_i2c2_slaves,
861   - .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
862   - .class = &i2c_class,
  858 + .flags = HWMOD_16BIT_REG,
863 859 .dev_attr = &i2c_dev_attr,
  860 + .slaves = am33xx_i2c2_slaves,
  861 + .slaves_cnt = ARRAY_SIZE(am33xx_i2c2_slaves),
  862 + .class = &i2c_class,
864 863 };
865 864  
866 865 /* 'icss' class */
867 866  
... ... @@ -872,10 +871,10 @@
872 871 static struct omap_hwmod am33xx_icss_hwmod = {
873 872 .name = "icss",
874 873 .class = &am33xx_icss_hwmod_class,
875   - .main_clk = "pruss",
  874 + .main_clk = "icss_uart_gclk",
876 875 .clkdm_name = "icss_ocp_clkdm",
877   - .prcm = {
878   - .omap4 = {
  876 + .prcm = {
  877 + .omap4 = {
879 878 .clkctrl_offs = AM33XX_CM_PER_ICSS_CLKCTRL_OFFSET,
880 879 .modulemode = MODULEMODE_SWCTRL,
881 880 },
... ... @@ -884,7 +883,7 @@
884 883  
885 884 /* 'ieee5000' class */
886 885 static struct omap_hwmod_class am33xx_ieee5000_hwmod_class = {
887   - .name = "ieee5000",
  886 + .name = "ieee5000",
888 887 };
889 888  
890 889 /* ieee5000 */
... ... @@ -893,8 +892,8 @@
893 892 .class = &am33xx_ieee5000_hwmod_class,
894 893 .main_clk = "ieee5000_fck",
895 894 .clkdm_name = "l3s_clkdm",
896   - .prcm = {
897   - .omap4 = {
  895 + .prcm = {
  896 + .omap4 = {
898 897 .clkctrl_offs = AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET,
899 898 .modulemode = MODULEMODE_SWCTRL,
900 899 },
... ... @@ -904,7 +903,7 @@
904 903  
905 904 /* 'l3' class */
906 905 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
907   - .name = "l3",
  906 + .name = "l3",
908 907 };
909 908  
910 909 /* l4_hs */
... ... @@ -913,8 +912,8 @@
913 912 .class = &am33xx_l3_hwmod_class,
914 913 .clkdm_name = "l4hs_clkdm",
915 914 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
916   - .prcm = {
917   - .omap4 = {
  915 + .prcm = {
  916 + .omap4 = {
918 917 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
919 918 .modulemode = MODULEMODE_SWCTRL,
920 919 },
... ... @@ -927,8 +926,8 @@
927 926 .class = &am33xx_l3_hwmod_class,
928 927 .clkdm_name = "l3_clkdm",
929 928 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
930   - .prcm = {
931   - .omap4 = {
  929 + .prcm = {
  930 + .omap4 = {
932 931 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
933 932 .modulemode = MODULEMODE_SWCTRL,
934 933 },
... ... @@ -941,8 +940,8 @@
941 940 .class = &am33xx_l3_hwmod_class,
942 941 .clkdm_name = "l3_clkdm",
943 942 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
944   - .prcm = {
945   - .omap4 = {
  943 + .prcm = {
  944 + .omap4 = {
946 945 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
947 946 .modulemode = MODULEMODE_SWCTRL,
948 947 },
... ... @@ -951,7 +950,7 @@
951 950  
952 951 /* 'l4fw' class */
953 952 static struct omap_hwmod_class am33xx_l4fw_hwmod_class = {
954   - .name = "l4fw",
  953 + .name = "l4fw",
955 954 };
956 955  
957 956 /* l4fw */
... ... @@ -960,8 +959,8 @@
960 959 .class = &am33xx_l4fw_hwmod_class,
961 960 .clkdm_name = "l4fw_clkdm",
962 961 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
963   - .prcm = {
964   - .omap4 = {
  962 + .prcm = {
  963 + .omap4 = {
965 964 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
966 965 .modulemode = MODULEMODE_SWCTRL,
967 966 },
968 967  
969 968  
970 969  
971 970  
972 971  
973 972  
974 973  
975 974  
976 975  
977 976  
978 977  
979 978  
... ... @@ -970,70 +969,69 @@
970 969  
971 970 /* 'l4ls' class */
972 971 static struct omap_hwmod_class am33xx_l4ls_hwmod_class = {
973   - .name = "l4ls",
  972 + .name = "l4ls",
974 973 };
975 974  
976 975 /* l4ls */
977 976 static struct omap_hwmod am33xx_l4ls_hwmod = {
978 977 .name = "l4ls",
979 978 .class = &am33xx_l4ls_hwmod_class,
980   - .main_clk = "l4ls_fck",
  979 + .main_clk = "l4ls_gclk",
981 980 .clkdm_name = "l4ls_clkdm",
982 981 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
983   - .prcm = {
984   - .omap4 = {
  982 + .prcm = {
  983 + .omap4 = {
985 984 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
986 985 .modulemode = MODULEMODE_SWCTRL,
987 986 },
988 987 },
989 988 };
990 989  
991   -#if 0
992 990 /* 'lcdc' class */
993 991 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
994   - .name = "lcdc",
  992 + .name = "lcdc",
995 993 };
996 994  
997 995 /* lcdc */
998 996 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
999   - { .irq = 36 },
1000   - { .irq = -1 }
  997 + { .irq = AM33XX_IRQ_LCD },
  998 + { .irq = -1 },
1001 999 };
1002 1000  
1003 1001 static struct omap_hwmod am33xx_lcdc_hwmod = {
1004 1002 .name = "lcdc",
1005 1003 .class = &am33xx_lcdc_hwmod_class,
1006   - .mpu_irqs = am33xx_lcdc_irqs,
  1004 + .mpu_irqs = am33xx_lcdc_irqs,
1007 1005 .main_clk = "lcdc_fck",
1008 1006 .clkdm_name = "lcdc_clkdm",
1009   - .prcm = {
1010   - .omap4 = {
  1007 + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  1008 + .prcm = {
  1009 + .omap4 = {
1011 1010 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1012 1011 .modulemode = MODULEMODE_SWCTRL,
1013 1012 },
1014 1013 },
1015 1014 };
1016   -#endif
1017 1015  
1018 1016 /* 'mcasp' class */
1019 1017 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1020   - .name = "mcasp",
  1018 + .name = "mcasp",
1021 1019 };
1022 1020  
1023 1021 /* mcasp0 */
1024 1022 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1025 1023 { .irq = 80 },
1026   - { .irq = -1 }
  1024 + { .irq = -1 },
1027 1025 };
1028 1026  
1029 1027 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1030 1028 .name = "mcasp0",
1031 1029 .class = &am33xx_mcasp_hwmod_class,
1032   - .mpu_irqs = am33xx_mcasp0_irqs,
  1030 + .mpu_irqs = am33xx_mcasp0_irqs,
1033 1031 .main_clk = "mcasp0_fck",
1034 1032 .clkdm_name = "l3s_clkdm",
1035   - .prcm = {
1036   - .omap4 = {
  1033 + .prcm = {
  1034 + .omap4 = {
1037 1035 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1038 1036 .modulemode = MODULEMODE_SWCTRL,
1039 1037 },
... ... @@ -1041,6 +1039,7 @@
1041 1039 };
1042 1040  
1043 1041 /* 'mmc' class */
  1042 +
1044 1043 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1045 1044 .rev_offs = 0x1fc,
1046 1045 .sysc_offs = 0x10,
1047 1046  
... ... @@ -1053,14 +1052,14 @@
1053 1052 };
1054 1053  
1055 1054 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1056   - .name = "mmc",
1057   - .sysc = &am33xx_mmc_sysc,
  1055 + .name = "mmc",
  1056 + .sysc = &am33xx_mmc_sysc,
1058 1057 };
1059 1058  
1060 1059 /* mmc0 */
1061 1060 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1062 1061 { .irq = AM33XX_IRQ_MMCHS0 },
1063   - { .irq = -1 }
  1062 + { .irq = -1 },
1064 1063 };
1065 1064  
1066 1065 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1067 1066  
1068 1067  
1069 1068  
... ... @@ -1086,22 +1085,22 @@
1086 1085 };
1087 1086  
1088 1087 static struct omap_hwmod_ocp_if *am33xx_mmc0_slaves[] = {
1089   - &am33xx_l4ls__mmc0,
  1088 + &am33xx_l4ls__mmc0,
1090 1089 };
1091 1090  
1092 1091 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1093   - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1092 + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1094 1093 };
1095 1094  
1096 1095 static struct omap_hwmod am33xx_mmc0_hwmod = {
1097 1096 .name = "mmc1",
1098 1097 .class = &am33xx_mmc_hwmod_class,
1099   - .mpu_irqs = am33xx_mmc0_irqs,
  1098 + .mpu_irqs = am33xx_mmc0_irqs,
1100 1099 .sdma_reqs = am33xx_mmc0_edma_reqs,
1101 1100 .main_clk = "mmc0_fck",
1102 1101 .clkdm_name = "l4ls_clkdm",
1103   - .prcm = {
1104   - .omap4 = {
  1102 + .prcm = {
  1103 + .omap4 = {
1105 1104 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1106 1105 .modulemode = MODULEMODE_SWCTRL,
1107 1106 },
... ... @@ -1114,7 +1113,7 @@
1114 1113 /* mmc1 */
1115 1114 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1116 1115 { .irq = AM33XX_IRQ_MMCHS1 },
1117   - { .irq = -1 }
  1116 + { .irq = -1 },
1118 1117 };
1119 1118  
1120 1119 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1121 1120  
1122 1121  
... ... @@ -1144,18 +1143,18 @@
1144 1143 };
1145 1144  
1146 1145 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1147   - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1146 + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1148 1147 };
1149 1148  
1150 1149 static struct omap_hwmod am33xx_mmc1_hwmod = {
1151 1150 .name = "mmc2",
1152 1151 .class = &am33xx_mmc_hwmod_class,
1153   - .mpu_irqs = am33xx_mmc1_irqs,
  1152 + .mpu_irqs = am33xx_mmc1_irqs,
1154 1153 .sdma_reqs = am33xx_mmc1_edma_reqs,
1155 1154 .main_clk = "mmc1_fck",
1156 1155 .clkdm_name = "l4ls_clkdm",
1157   - .prcm = {
1158   - .omap4 = {
  1156 + .prcm = {
  1157 + .omap4 = {
1159 1158 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1160 1159 .modulemode = MODULEMODE_SWCTRL,
1161 1160 },
... ... @@ -1168,7 +1167,7 @@
1168 1167 /* mmc2 */
1169 1168 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1170 1169 { .irq = AM33XX_IRQ_MMCHS2 },
1171   - { .irq = -1 }
  1170 + { .irq = -1 },
1172 1171 };
1173 1172  
1174 1173 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1175 1174  
1176 1175  
1177 1176  
1178 1177  
... ... @@ -1194,22 +1193,21 @@
1194 1193 };
1195 1194  
1196 1195 static struct omap_hwmod_ocp_if *am33xx_mmc2_slaves[] = {
1197   - &am33xx_l3_main__mmc2,
  1196 + &am33xx_l3_main__mmc2,
1198 1197 };
1199 1198  
1200 1199 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1201   - .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
  1200 + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1202 1201 };
1203   -
1204 1202 static struct omap_hwmod am33xx_mmc2_hwmod = {
1205 1203 .name = "mmc3",
1206 1204 .class = &am33xx_mmc_hwmod_class,
1207   - .mpu_irqs = am33xx_mmc2_irqs,
  1205 + .mpu_irqs = am33xx_mmc2_irqs,
1208 1206 .sdma_reqs = am33xx_mmc2_edma_reqs,
1209 1207 .main_clk = "mmc2_fck",
1210 1208 .clkdm_name = "l3s_clkdm",
1211   - .prcm = {
1212   - .omap4 = {
  1209 + .prcm = {
  1210 + .omap4 = {
1213 1211 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1214 1212 .modulemode = MODULEMODE_SWCTRL,
1215 1213 },
1216 1214  
... ... @@ -1227,14 +1225,14 @@
1227 1225 /* mpu */
1228 1226 static struct omap_hwmod am33xx_mpu_hwmod = {
1229 1227 .name = "mpu",
1230   - .class = &mpu_hwmod_class,
1231   - .masters = am33xx_l3_mpu_masters,
1232   - .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
  1228 + .class = &mpu_hwmod_class,
  1229 + .masters = am33xx_l3_mpu_masters,
  1230 + .masters_cnt = ARRAY_SIZE(am33xx_l3_mpu_masters),
1233 1231 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1234 1232 .main_clk = "mpu_fck",
1235   - .clkdm_name = "mpu_clkdm",
1236   - .prcm = {
1237   - .omap4 = {
  1233 + .clkdm_name = "mpu_clkdm",
  1234 + .prcm = {
  1235 + .omap4 = {
1238 1236 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1239 1237 .modulemode = MODULEMODE_SWCTRL,
1240 1238 },
1241 1239  
... ... @@ -1250,10 +1248,10 @@
1250 1248 static struct omap_hwmod am33xx_ocmcram_hwmod = {
1251 1249 .name = "ocmcram",
1252 1250 .class = &am33xx_ocmcram_hwmod_class,
1253   - .main_clk = "ocmcram_fck",
  1251 + .main_clk = "ocmcram_ick",
1254 1252 .clkdm_name = "l3_clkdm",
1255   - .prcm = {
1256   - .omap4 = {
  1253 + .prcm = {
  1254 + .omap4 = {
1257 1255 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
1258 1256 .modulemode = MODULEMODE_SWCTRL,
1259 1257 },
... ... @@ -1262,7 +1260,7 @@
1262 1260  
1263 1261 /* 'ocpwp' class */
1264 1262 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
1265   - .name = "ocpwp",
  1263 + .name = "ocpwp",
1266 1264 };
1267 1265  
1268 1266 /* ocpwp */
... ... @@ -1271,8 +1269,8 @@
1271 1269 .class = &am33xx_ocpwp_hwmod_class,
1272 1270 .main_clk = "ocpwp_fck",
1273 1271 .clkdm_name = "l4ls_clkdm",
1274   - .prcm = {
1275   - .omap4 = {
  1272 + .prcm = {
  1273 + .omap4 = {
1276 1274 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
1277 1275 .modulemode = MODULEMODE_SWCTRL,
1278 1276 },
1279 1277  
1280 1278  
1281 1279  
... ... @@ -1281,24 +1279,24 @@
1281 1279  
1282 1280 /* 'rtc' class */
1283 1281 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1284   - .name = "rtc",
  1282 + .name = "rtc",
1285 1283 };
1286 1284  
1287 1285 /* rtc */
1288 1286 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1289   - { .irq = 75 },
1290   - { .irq = -1 }
  1287 + { .irq = AM33XX_IRQ_RTC_TIMER },
  1288 + { .irq = -1 },
1291 1289 };
1292 1290  
1293 1291 static struct omap_hwmod am33xx_rtc_hwmod = {
1294 1292 .name = "rtc",
1295 1293 .class = &am33xx_rtc_hwmod_class,
1296   - .mpu_irqs = am33xx_rtc_irqs,
  1294 + .mpu_irqs = am33xx_rtc_irqs,
1297 1295 .main_clk = "rtc_fck",
1298 1296 .clkdm_name = "l4_rtc_clkdm",
1299   - .flags = HWMOD_INIT_NO_IDLE,
1300   - .prcm = {
1301   - .omap4 = {
  1297 + .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  1298 + .prcm = {
  1299 + .omap4 = {
1302 1300 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1303 1301 .modulemode = MODULEMODE_SWCTRL,
1304 1302 },
1305 1303  
1306 1304  
1307 1305  
... ... @@ -1307,23 +1305,23 @@
1307 1305  
1308 1306 /* 'sha0' class */
1309 1307 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
1310   - .name = "sha0",
  1308 + .name = "sha0",
1311 1309 };
1312 1310  
1313 1311 /* sha0 */
1314 1312 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
1315   - { .irq = 108 },
1316   - { .irq = -1 }
  1313 + { .irq = AM33XX_IRQ_SHAEIP57t0_S },
  1314 + { .irq = -1 },
1317 1315 };
1318 1316  
1319 1317 static struct omap_hwmod am33xx_sha0_hwmod = {
1320 1318 .name = "sha0",
1321 1319 .class = &am33xx_sha0_hwmod_class,
1322   - .mpu_irqs = am33xx_sha0_irqs,
  1320 + .mpu_irqs = am33xx_sha0_irqs,
1323 1321 .main_clk = "sha0_fck",
1324 1322 .clkdm_name = "l3_clkdm",
1325   - .prcm = {
1326   - .omap4 = {
  1323 + .prcm = {
  1324 + .omap4 = {
1327 1325 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
1328 1326 .modulemode = MODULEMODE_SWCTRL,
1329 1327 },
1330 1328  
1331 1329  
1332 1330  
... ... @@ -1332,23 +1330,23 @@
1332 1330  
1333 1331 /* 'smartreflex' class */
1334 1332 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
1335   - .name = "smartreflex",
  1333 + .name = "smartreflex",
1336 1334 };
1337 1335  
1338 1336 /* smartreflex0 */
1339 1337 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
1340   - { .irq = 120 },
1341   - { .irq = -1 }
  1338 + { .irq = AM33XX_IRQ_SMARTREFLEX0 },
  1339 + { .irq = -1 },
1342 1340 };
1343 1341  
1344 1342 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
1345 1343 .name = "smartreflex0",
1346 1344 .class = &am33xx_smartreflex_hwmod_class,
1347   - .mpu_irqs = am33xx_smartreflex0_irqs,
  1345 + .mpu_irqs = am33xx_smartreflex0_irqs,
1348 1346 .main_clk = "smartreflex0_fck",
1349 1347 .clkdm_name = "l4_wkup_clkdm",
1350   - .prcm = {
1351   - .omap4 = {
  1348 + .prcm = {
  1349 + .omap4 = {
1352 1350 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
1353 1351 .modulemode = MODULEMODE_SWCTRL,
1354 1352 },
1355 1353  
1356 1354  
1357 1355  
1358 1356  
1359 1357  
1360 1358  
1361 1359  
... ... @@ -1357,46 +1355,47 @@
1357 1355  
1358 1356 /* smartreflex1 */
1359 1357 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
1360   - { .irq = 121 },
1361   - { .irq = -1 }
  1358 + { .irq = AM33XX_IRQ_SMARTREFLEX1 },
  1359 + { .irq = -1 },
1362 1360 };
1363 1361  
1364 1362 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
1365 1363 .name = "smartreflex1",
1366 1364 .class = &am33xx_smartreflex_hwmod_class,
1367   - .mpu_irqs = am33xx_smartreflex1_irqs,
  1365 + .mpu_irqs = am33xx_smartreflex1_irqs,
1368 1366 .main_clk = "smartreflex1_fck",
1369 1367 .clkdm_name = "l4_wkup_clkdm",
1370   - .prcm = {
1371   - .omap4 = {
  1368 + .prcm = {
  1369 + .omap4 = {
1372 1370 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
1373 1371 .modulemode = MODULEMODE_SWCTRL,
1374 1372 },
1375 1373 },
1376 1374 };
1377 1375  
  1376 +/* 'spi' class */
  1377 +
1378 1378 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1379 1379 .rev_offs = 0x0000,
1380 1380 .sysc_offs = 0x0110,
1381 1381 .syss_offs = 0x0114,
1382 1382 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1383   - SYSC_HAS_SOFTRESET |
1384   - SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  1383 + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  1384 + SYSS_HAS_RESET_STATUS),
1385 1385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1386 1386 .sysc_fields = &omap_hwmod_sysc_type1,
1387 1387 };
1388 1388  
1389   -/* 'spi' class */
1390 1389 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1391   - .name = "mcspi",
1392   - .sysc = &am33xx_mcspi_sysc,
1393   - .rev = OMAP4_MCSPI_REV,
  1390 + .name = "mcspi",
  1391 + .sysc = &am33xx_mcspi_sysc,
  1392 + .rev = OMAP4_MCSPI_REV,
1394 1393 };
1395 1394  
1396 1395 /* spi0 */
1397 1396 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1398 1397 { .irq = AM33XX_IRQ_MCSPIOCP0 },
1399   - { .irq = -1 }
  1398 + { .irq = -1 },
1400 1399 };
1401 1400  
1402 1401 struct omap_hwmod_dma_info am33xx_mcspi0_sdma_reqs[] = {
... ... @@ -1413,7 +1412,7 @@
1413 1412 .pa_end = AM33XX_SPI0_BASE + SZ_1K - 1,
1414 1413 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1415 1414 },
1416   - { }
  1415 + { },
1417 1416 };
1418 1417  
1419 1418 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi0 = {
1420 1419  
1421 1420  
1422 1421  
1423 1422  
1424 1423  
... ... @@ -1429,31 +1428,30 @@
1429 1428 };
1430 1429  
1431 1430 struct omap2_mcspi_dev_attr mcspi_attrib = {
1432   - .num_chipselect = 2,
  1431 + .num_chipselect = 2,
1433 1432 };
1434   -
1435 1433 static struct omap_hwmod am33xx_spi0_hwmod = {
1436 1434 .name = "spi0",
1437 1435 .class = &am33xx_spi_hwmod_class,
1438   - .mpu_irqs = am33xx_spi0_irqs,
  1436 + .mpu_irqs = am33xx_spi0_irqs,
1439 1437 .sdma_reqs = am33xx_mcspi0_sdma_reqs,
1440 1438 .main_clk = "spi0_fck",
1441 1439 .clkdm_name = "l4ls_clkdm",
1442   - .dev_attr = &mcspi_attrib,
1443   - .slaves = am33xx_mcspi0_slaves,
1444   - .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1445   - .prcm = {
1446   - .omap4 = {
  1440 + .prcm = {
  1441 + .omap4 = {
1447 1442 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1448 1443 .modulemode = MODULEMODE_SWCTRL,
1449 1444 },
1450 1445 },
  1446 + .dev_attr = &mcspi_attrib,
  1447 + .slaves = am33xx_mcspi0_slaves,
  1448 + .slaves_cnt = ARRAY_SIZE(am33xx_mcspi0_slaves),
1451 1449 };
1452 1450  
1453 1451 /* spi1 */
1454 1452 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1455 1453 { .irq = AM33XX_IRQ_SPI1 },
1456   - { .irq = -1 }
  1454 + { .irq = -1 },
1457 1455 };
1458 1456  
1459 1457 struct omap_hwmod_dma_info am33xx_mcspi1_sdma_reqs[] = {
... ... @@ -1470,7 +1468,7 @@
1470 1468 .pa_end = AM33XX_SPI1_BASE + SZ_1K - 1,
1471 1469 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
1472 1470 },
1473   - { }
  1471 + { },
1474 1472 };
1475 1473  
1476 1474 struct omap_hwmod_ocp_if am33xx_l4_core__mcspi1 = {
1477 1475  
1478 1476  
1479 1477  
1480 1478  
... ... @@ -1484,28 +1482,27 @@
1484 1482 static struct omap_hwmod_ocp_if *am33xx_mcspi1_slaves[] = {
1485 1483 &am33xx_l4_core__mcspi1,
1486 1484 };
1487   -
1488 1485 static struct omap_hwmod am33xx_spi1_hwmod = {
1489   - .name = "spi1",
1490   - .class = &am33xx_spi_hwmod_class,
1491   - .mpu_irqs = am33xx_spi1_irqs,
  1486 + .name = "spi1",
  1487 + .class = &am33xx_spi_hwmod_class,
  1488 + .mpu_irqs = am33xx_spi1_irqs,
1492 1489 .sdma_reqs = am33xx_mcspi1_sdma_reqs,
1493 1490 .main_clk = "spi1_fck",
1494 1491 .clkdm_name = "l4ls_clkdm",
1495   - .dev_attr = &mcspi_attrib,
1496   - .slaves = am33xx_mcspi1_slaves,
1497   - .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1498   - .prcm = {
1499   - .omap4 = {
  1492 + .prcm = {
  1493 + .omap4 = {
1500 1494 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1501 1495 .modulemode = MODULEMODE_SWCTRL,
1502 1496 },
1503 1497 },
  1498 + .dev_attr = &mcspi_attrib,
  1499 + .slaves = am33xx_mcspi1_slaves,
  1500 + .slaves_cnt = ARRAY_SIZE(am33xx_mcspi1_slaves),
1504 1501 };
1505 1502  
1506 1503 /* 'spinlock' class */
1507 1504 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1508   - .name = "spinlock",
  1505 + .name = "spinlock",
1509 1506 };
1510 1507  
1511 1508 /* spinlock */
1512 1509  
1513 1510  
1514 1511  
1515 1512  
1516 1513  
1517 1514  
1518 1515  
1519 1516  
1520 1517  
1521 1518  
1522 1519  
1523 1520  
... ... @@ -1514,68 +1511,66 @@
1514 1511 .class = &am33xx_spinlock_hwmod_class,
1515 1512 .main_clk = "spinlock_fck",
1516 1513 .clkdm_name = "l4ls_clkdm",
1517   - .prcm = {
1518   - .omap4 = {
  1514 + .prcm = {
  1515 + .omap4 = {
1519 1516 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1520 1517 .modulemode = MODULEMODE_SWCTRL,
1521 1518 },
1522 1519 },
1523 1520 };
1524 1521  
1525   -
1526 1522 /* 'timer 0 & 2-7' class */
1527 1523 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1528   - .rev_offs = 0x0000,
1529   - .sysc_offs = 0x0010,
1530   - .syss_offs = 0x0014,
1531   - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1532   - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  1524 + .rev_offs = 0x0000,
  1525 + .sysc_offs = 0x0010,
  1526 + .syss_offs = 0x0014,
  1527 + .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
  1528 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1533 1529 SIDLE_SMART_WKUP),
1534   - .sysc_fields = &omap_hwmod_sysc_type2,
  1530 + .sysc_fields = &omap_hwmod_sysc_type2,
1535 1531 };
1536 1532  
1537   -/* 'timer 0 & 2-7' class */
1538 1533 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1539   - .name = "timer",
1540   - .sysc = &am33xx_timer_sysc,
  1534 + .name = "timer",
  1535 + .sysc = &am33xx_timer_sysc,
1541 1536 };
1542 1537  
1543 1538 /* timer0 */
1544 1539 /* l4 wkup -> timer0 interface */
1545 1540 static struct omap_hwmod_addr_space am33xx_timer0_addr_space[] = {
1546 1541 {
1547   - .pa_start = 0x44E05000,
1548   - .pa_end = 0x44E05000 + SZ_1K - 1,
  1542 + .pa_start = AM33XX_TIMER0_BASE,
  1543 + .pa_end = AM33XX_TIMER0_BASE + SZ_1K - 1,
1549 1544 .flags = ADDR_TYPE_RT
1550 1545 },
1551   - { }
  1546 + { },
1552 1547 };
1553 1548  
1554 1549 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer0 = {
1555   - .master = &am33xx_l4wkup_hwmod,
1556   - .slave = &am33xx_timer0_hwmod,
1557   - .clk = "timer0_ick",
1558   - .addr = am33xx_timer0_addr_space,
1559   - .user = OCP_USER_MPU,
  1550 + .master = &am33xx_l4wkup_hwmod,
  1551 + .slave = &am33xx_timer0_hwmod,
  1552 + .clk = "timer0_ick",
  1553 + .addr = am33xx_timer0_addr_space,
  1554 + .user = OCP_USER_MPU,
1560 1555 };
1561 1556  
1562 1557 static struct omap_hwmod_ocp_if *am33xx_timer0_slaves[] = {
1563   - &am33xx_l4wkup__timer0,
  1558 + &am33xx_l4wkup__timer0,
1564 1559 };
1565 1560  
1566 1561 static struct omap_hwmod_irq_info am33xx_timer0_irqs[] = {
1567   - { .irq = 66 },
1568   - { .irq = -1 }
  1562 + { .irq = AM33XX_IRQ_DMTIMER0 },
  1563 + { .irq = -1 },
1569 1564 };
1570 1565  
1571 1566 static struct omap_hwmod am33xx_timer0_hwmod = {
1572 1567 .name = "timer0",
1573 1568 .class = &am33xx_timer_hwmod_class,
1574   - .mpu_irqs = am33xx_timer0_irqs,
  1569 + .mpu_irqs = am33xx_timer0_irqs,
1575 1570 .main_clk = "timer0_fck",
1576 1571 .clkdm_name = "l4_wkup_clkdm",
1577   - .prcm = {
1578   - .omap4 = {
  1572 + .prcm = {
  1573 + .omap4 = {
1579 1574 .clkctrl_offs = AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET,
1580 1575 .modulemode = MODULEMODE_SWCTRL,
1581 1576 },
1582 1577  
1583 1578  
1584 1579  
1585 1580  
1586 1581  
1587 1582  
1588 1583  
1589 1584  
1590 1585  
... ... @@ -1584,58 +1579,58 @@
1584 1579 .slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
1585 1580 };
1586 1581  
1587   -/* timer 1ms */
  1582 +/* timer1 1ms */
1588 1583 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1589   - .rev_offs = 0x0000,
1590   - .sysc_offs = 0x0010,
1591   - .syss_offs = 0x0014,
1592   - .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE
1593   - | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE
1594   - | SYSS_HAS_RESET_STATUS),
1595   - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1596   - .sysc_fields = &omap_hwmod_sysc_type1,
  1584 + .rev_offs = 0x0000,
  1585 + .sysc_offs = 0x0010,
  1586 + .syss_offs = 0x0014,
  1587 + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
  1588 + SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  1589 + SYSS_HAS_RESET_STATUS),
  1590 + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  1591 + .sysc_fields = &omap_hwmod_sysc_type1,
1597 1592 };
1598 1593  
1599 1594 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1600   - .name = "timer",
1601   - .sysc = &am33xx_timer1ms_sysc,
  1595 + .name = "timer",
  1596 + .sysc = &am33xx_timer1ms_sysc,
1602 1597 };
1603 1598  
1604 1599 /* l4 wkup -> timer1 interface */
1605 1600 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
1606 1601 {
1607   - .pa_start = 0x44E31000,
1608   - .pa_end = 0x44E31000 + SZ_1K - 1,
  1602 + .pa_start = AM33XX_TIMER1_BASE,
  1603 + .pa_end = AM33XX_TIMER1_BASE + SZ_1K - 1,
1609 1604 .flags = ADDR_TYPE_RT
1610 1605 },
1611   - { }
  1606 + { },
1612 1607 };
1613 1608  
1614 1609 static struct omap_hwmod_ocp_if am33xx_l4wkup__timer1 = {
1615   - .master = &am33xx_l4wkup_hwmod,
1616   - .slave = &am33xx_timer1_hwmod,
1617   - .clk = "timer1_ick",
1618   - .addr = am33xx_timer1_addr_space,
1619   - .user = OCP_USER_MPU,
  1610 + .master = &am33xx_l4wkup_hwmod,
  1611 + .slave = &am33xx_timer1_hwmod,
  1612 + .clk = "timer1_ick",
  1613 + .addr = am33xx_timer1_addr_space,
  1614 + .user = OCP_USER_MPU,
1620 1615 };
1621 1616  
1622 1617 static struct omap_hwmod_ocp_if *am33xx_timer1_slaves[] = {
1623   - &am33xx_l4wkup__timer1,
  1618 + &am33xx_l4wkup__timer1,
1624 1619 };
1625 1620  
1626 1621 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1627   - { .irq = 67 },
1628   - { .irq = -1 }
  1622 + { .irq = AM33XX_IRQ_DMTIMER1 },
  1623 + { .irq = -1 },
1629 1624 };
1630 1625  
1631 1626 static struct omap_hwmod am33xx_timer1_hwmod = {
1632 1627 .name = "timer1",
1633 1628 .class = &am33xx_timer1ms_hwmod_class,
1634   - .mpu_irqs = am33xx_timer1_irqs,
  1629 + .mpu_irqs = am33xx_timer1_irqs,
1635 1630 .main_clk = "timer1_fck",
1636 1631 .clkdm_name = "l4_wkup_clkdm",
1637   - .prcm = {
1638   - .omap4 = {
  1632 + .prcm = {
  1633 + .omap4 = {
1639 1634 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1640 1635 .modulemode = MODULEMODE_SWCTRL,
1641 1636 },
1642 1637  
1643 1638  
1644 1639  
1645 1640  
1646 1641  
1647 1642  
... ... @@ -1648,37 +1643,37 @@
1648 1643 /* l4 per -> timer2 interface */
1649 1644 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
1650 1645 {
1651   - .pa_start = 0x48040000,
1652   - .pa_end = 0x48040000 + SZ_1K - 1,
  1646 + .pa_start = AM33XX_TIMER2_BASE,
  1647 + .pa_end = AM33XX_TIMER2_BASE + SZ_1K - 1,
1653 1648 .flags = ADDR_TYPE_RT
1654 1649 },
1655   - { }
  1650 + { },
1656 1651 };
1657 1652  
1658 1653 static struct omap_hwmod_ocp_if am33xx_l4per__timer2 = {
1659   - .master = &am33xx_l4per_hwmod,
1660   - .slave = &am33xx_timer2_hwmod,
1661   - .clk = "timer2_ick",
1662   - .addr = am33xx_timer2_addr_space,
1663   - .user = OCP_USER_MPU,
  1654 + .master = &am33xx_l4per_hwmod,
  1655 + .slave = &am33xx_timer2_hwmod,
  1656 + .clk = "timer2_ick",
  1657 + .addr = am33xx_timer2_addr_space,
  1658 + .user = OCP_USER_MPU,
1664 1659 };
1665 1660  
1666 1661 static struct omap_hwmod_ocp_if *am33xx_timer2_slaves[] = {
1667   - &am33xx_l4per__timer2,
  1662 + &am33xx_l4per__timer2,
1668 1663 };
1669 1664  
1670 1665 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1671   - { .irq = 68 },
1672   - { .irq = -1 }
  1666 + { .irq = AM33XX_IRQ_DMTIMER2 },
  1667 + { .irq = -1 },
1673 1668 };
1674 1669  
1675 1670 static struct omap_hwmod am33xx_timer2_hwmod = {
1676 1671 .name = "timer2",
1677 1672 .class = &am33xx_timer_hwmod_class,
1678   - .mpu_irqs = am33xx_timer2_irqs,
  1673 + .mpu_irqs = am33xx_timer2_irqs,
1679 1674 .main_clk = "timer2_fck",
1680   - .prcm = {
1681   - .omap4 = {
  1675 + .prcm = {
  1676 + .omap4 = {
1682 1677 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1683 1678 .modulemode = MODULEMODE_SWCTRL,
1684 1679 },
1685 1680  
1686 1681  
1687 1682  
1688 1683  
1689 1684  
1690 1685  
... ... @@ -1692,38 +1687,38 @@
1692 1687 /* l4 per -> timer3 interface */
1693 1688 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
1694 1689 {
1695   - .pa_start = 0x48042000,
1696   - .pa_end = 0x48042000 + SZ_1K - 1,
  1690 + .pa_start = AM33XX_TIMER3_BASE,
  1691 + .pa_end = AM33XX_TIMER3_BASE + SZ_1K - 1,
1697 1692 .flags = ADDR_TYPE_RT
1698 1693 },
1699   - { }
  1694 + { },
1700 1695 };
1701 1696  
1702 1697 static struct omap_hwmod_ocp_if am33xx_l4per__timer3 = {
1703   - .master = &am33xx_l4per_hwmod,
1704   - .slave = &am33xx_timer3_hwmod,
1705   - .clk = "timer3_ick",
1706   - .addr = am33xx_timer3_addr_space,
1707   - .user = OCP_USER_MPU,
  1698 + .master = &am33xx_l4per_hwmod,
  1699 + .slave = &am33xx_timer3_hwmod,
  1700 + .clk = "timer3_ick",
  1701 + .addr = am33xx_timer3_addr_space,
  1702 + .user = OCP_USER_MPU,
1708 1703 };
1709 1704  
1710 1705 static struct omap_hwmod_ocp_if *am33xx_timer3_slaves[] = {
1711   - &am33xx_l4per__timer3,
  1706 + &am33xx_l4per__timer3,
1712 1707 };
1713 1708  
1714 1709 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1715   - { .irq = 69 },
1716   - { .irq = -1 }
  1710 + { .irq = AM33XX_IRQ_DMTIMER3 },
  1711 + { .irq = -1 },
1717 1712 };
1718 1713  
1719 1714 static struct omap_hwmod am33xx_timer3_hwmod = {
1720 1715 .name = "timer3",
1721 1716 .class = &am33xx_timer_hwmod_class,
1722   - .mpu_irqs = am33xx_timer3_irqs,
  1717 + .mpu_irqs = am33xx_timer3_irqs,
1723 1718 .main_clk = "timer3_fck",
1724 1719 .clkdm_name = "l4ls_clkdm",
1725   - .prcm = {
1726   - .omap4 = {
  1720 + .prcm = {
  1721 + .omap4 = {
1727 1722 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1728 1723 .modulemode = MODULEMODE_SWCTRL,
1729 1724 },
1730 1725  
1731 1726  
1732 1727  
1733 1728  
1734 1729  
1735 1730  
... ... @@ -1736,37 +1731,37 @@
1736 1731 /* l4 per -> timer4 interface */
1737 1732 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
1738 1733 {
1739   - .pa_start = 0x48044000,
1740   - .pa_end = 0x48044000 + SZ_1K - 1,
  1734 + .pa_start = AM33XX_TIMER4_BASE,
  1735 + .pa_end = AM33XX_TIMER4_BASE + SZ_1K - 1,
1741 1736 .flags = ADDR_TYPE_RT
1742 1737 },
1743   - { }
  1738 + { },
1744 1739 };
1745 1740  
1746 1741 static struct omap_hwmod_ocp_if am33xx_l4per__timer4 = {
1747   - .master = &am33xx_l4per_hwmod,
1748   - .slave = &am33xx_timer4_hwmod,
1749   - .clk = "timer4_ick",
1750   - .addr = am33xx_timer4_addr_space,
1751   - .user = OCP_USER_MPU,
  1742 + .master = &am33xx_l4per_hwmod,
  1743 + .slave = &am33xx_timer4_hwmod,
  1744 + .clk = "timer4_ick",
  1745 + .addr = am33xx_timer4_addr_space,
  1746 + .user = OCP_USER_MPU,
1752 1747 };
1753 1748  
1754 1749 static struct omap_hwmod_ocp_if *am33xx_timer4_slaves[] = {
1755   - &am33xx_l4per__timer4,
  1750 + &am33xx_l4per__timer4,
1756 1751 };
1757 1752  
1758 1753 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1759   - { .irq = 92 },
1760   - { .irq = -1 }
  1754 + { .irq = AM33XX_IRQ_DMTIMER4 },
  1755 + { .irq = -1 },
1761 1756 };
1762 1757  
1763 1758 static struct omap_hwmod am33xx_timer4_hwmod = {
1764 1759 .name = "timer4",
1765 1760 .class = &am33xx_timer_hwmod_class,
1766   - .mpu_irqs = am33xx_timer4_irqs,
  1761 + .mpu_irqs = am33xx_timer4_irqs,
1767 1762 .main_clk = "timer4_fck",
1768   - .prcm = {
1769   - .omap4 = {
  1763 + .prcm = {
  1764 + .omap4 = {
1770 1765 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1771 1766 .modulemode = MODULEMODE_SWCTRL,
1772 1767 },
1773 1768  
1774 1769  
1775 1770  
1776 1771  
1777 1772  
1778 1773  
... ... @@ -1781,37 +1776,37 @@
1781 1776 /* l4 per -> timer5 interface */
1782 1777 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
1783 1778 {
1784   - .pa_start = 0x48046000,
1785   - .pa_end = 0x48046000 + SZ_1K - 1,
  1779 + .pa_start = AM33XX_TIMER5_BASE,
  1780 + .pa_end = AM33XX_TIMER5_BASE + SZ_1K - 1,
1786 1781 .flags = ADDR_TYPE_RT
1787 1782 },
1788   - { }
  1783 + { },
1789 1784 };
1790 1785  
1791 1786 static struct omap_hwmod_ocp_if am33xx_l4per__timer5 = {
1792   - .master = &am33xx_l4per_hwmod,
1793   - .slave = &am33xx_timer5_hwmod,
1794   - .clk = "timer5_ick",
1795   - .addr = am33xx_timer5_addr_space,
1796   - .user = OCP_USER_MPU,
  1787 + .master = &am33xx_l4per_hwmod,
  1788 + .slave = &am33xx_timer5_hwmod,
  1789 + .clk = "timer5_ick",
  1790 + .addr = am33xx_timer5_addr_space,
  1791 + .user = OCP_USER_MPU,
1797 1792 };
1798 1793  
1799 1794 static struct omap_hwmod_ocp_if *am33xx_timer5_slaves[] = {
1800   - &am33xx_l4per__timer5,
  1795 + &am33xx_l4per__timer5,
1801 1796 };
1802 1797  
1803 1798 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1804   - { .irq = 93 },
1805   - { .irq = -1 }
  1799 + { .irq = AM33XX_IRQ_DMTIMER5 },
  1800 + { .irq = -1 },
1806 1801 };
1807 1802  
1808 1803 static struct omap_hwmod am33xx_timer5_hwmod = {
1809 1804 .name = "timer5",
1810 1805 .class = &am33xx_timer_hwmod_class,
1811   - .mpu_irqs = am33xx_timer5_irqs,
  1806 + .mpu_irqs = am33xx_timer5_irqs,
1812 1807 .main_clk = "timer5_fck",
1813   - .prcm = {
1814   - .omap4 = {
  1808 + .prcm = {
  1809 + .omap4 = {
1815 1810 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1816 1811 .modulemode = MODULEMODE_SWCTRL,
1817 1812 },
1818 1813  
1819 1814  
1820 1815  
1821 1816  
1822 1817  
1823 1818  
... ... @@ -1825,37 +1820,37 @@
1825 1820 /* l4 per -> timer6 interface */
1826 1821 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
1827 1822 {
1828   - .pa_start = 0x48048000,
1829   - .pa_end = 0x48048000 + SZ_1K - 1,
  1823 + .pa_start = AM33XX_TIMER6_BASE,
  1824 + .pa_end = AM33XX_TIMER6_BASE + SZ_1K - 1,
1830 1825 .flags = ADDR_TYPE_RT
1831 1826 },
1832   - { }
  1827 + { },
1833 1828 };
1834 1829  
1835 1830 static struct omap_hwmod_ocp_if am33xx_l4per__timer6 = {
1836   - .master = &am33xx_l4per_hwmod,
1837   - .slave = &am33xx_timer6_hwmod,
1838   - .clk = "timer6_ick",
1839   - .addr = am33xx_timer6_addr_space,
1840   - .user = OCP_USER_MPU,
  1831 + .master = &am33xx_l4per_hwmod,
  1832 + .slave = &am33xx_timer6_hwmod,
  1833 + .clk = "timer6_ick",
  1834 + .addr = am33xx_timer6_addr_space,
  1835 + .user = OCP_USER_MPU,
1841 1836 };
1842 1837  
1843 1838 static struct omap_hwmod_ocp_if *am33xx_timer6_slaves[] = {
1844   - &am33xx_l4per__timer6,
  1839 + &am33xx_l4per__timer6,
1845 1840 };
1846 1841  
1847 1842 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1848   - { .irq = 94 },
1849   - { .irq = -1 }
  1843 + { .irq = AM33XX_IRQ_DMTIMER6 },
  1844 + { .irq = -1 },
1850 1845 };
1851 1846  
1852 1847 static struct omap_hwmod am33xx_timer6_hwmod = {
1853 1848 .name = "timer6",
1854 1849 .class = &am33xx_timer_hwmod_class,
1855   - .mpu_irqs = am33xx_timer6_irqs,
  1850 + .mpu_irqs = am33xx_timer6_irqs,
1856 1851 .main_clk = "timer6_fck",
1857   - .prcm = {
1858   - .omap4 = {
  1852 + .prcm = {
  1853 + .omap4 = {
1859 1854 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1860 1855 .modulemode = MODULEMODE_SWCTRL,
1861 1856 },
1862 1857  
1863 1858  
1864 1859  
1865 1860  
1866 1861  
1867 1862  
1868 1863  
... ... @@ -1865,42 +1860,41 @@
1865 1860 .clkdm_name = "l4ls_clkdm",
1866 1861 };
1867 1862  
1868   -
1869 1863 /* timer7 */
1870 1864 /* l4 per -> timer7 interface */
1871 1865 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
1872 1866 {
1873   - .pa_start = 0x4804a000,
1874   - .pa_end = 0x4804a000 + SZ_1K - 1,
  1867 + .pa_start = AM33XX_TIMER7_BASE,
  1868 + .pa_end = AM33XX_TIMER7_BASE + SZ_1K - 1,
1875 1869 .flags = ADDR_TYPE_RT
1876 1870 },
1877   - { }
  1871 + { },
1878 1872 };
1879 1873  
1880 1874 static struct omap_hwmod_ocp_if am33xx_l4per__timer7 = {
1881   - .master = &am33xx_l4per_hwmod,
1882   - .slave = &am33xx_timer7_hwmod,
1883   - .clk = "timer7_ick",
1884   - .addr = am33xx_timer7_addr_space,
1885   - .user = OCP_USER_MPU,
  1875 + .master = &am33xx_l4per_hwmod,
  1876 + .slave = &am33xx_timer7_hwmod,
  1877 + .clk = "timer7_ick",
  1878 + .addr = am33xx_timer7_addr_space,
  1879 + .user = OCP_USER_MPU,
1886 1880 };
1887 1881  
1888 1882 static struct omap_hwmod_ocp_if *am33xx_timer7_slaves[] = {
1889   - &am33xx_l4per__timer7,
  1883 + &am33xx_l4per__timer7,
1890 1884 };
1891 1885  
1892 1886 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1893   - { .irq = 69 },
1894   - { .irq = -1 }
  1887 + { .irq = AM33XX_IRQ_DMTIMER7 },
  1888 + { .irq = -1 },
1895 1889 };
1896 1890  
1897 1891 static struct omap_hwmod am33xx_timer7_hwmod = {
1898 1892 .name = "timer7",
1899 1893 .class = &am33xx_timer_hwmod_class,
1900   - .mpu_irqs = am33xx_timer7_irqs,
  1894 + .mpu_irqs = am33xx_timer7_irqs,
1901 1895 .main_clk = "timer7_fck",
1902   - .prcm = {
1903   - .omap4 = {
  1896 + .prcm = {
  1897 + .omap4 = {
1904 1898 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1905 1899 .modulemode = MODULEMODE_SWCTRL,
1906 1900 },
1907 1901  
1908 1902  
1909 1903  
... ... @@ -1912,23 +1906,23 @@
1912 1906  
1913 1907 /* 'tpcc' class */
1914 1908 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1915   - .name = "tpcc",
  1909 + .name = "tpcc",
1916 1910 };
1917 1911  
1918 1912 /* tpcc */
1919 1913 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1920   - { .irq = 12 },
1921   - { .irq = -1 }
  1914 + { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
  1915 + { .irq = -1 },
1922 1916 };
1923 1917  
1924 1918 static struct omap_hwmod am33xx_tpcc_hwmod = {
1925 1919 .name = "tpcc",
1926 1920 .class = &am33xx_tpcc_hwmod_class,
1927   - .mpu_irqs = am33xx_tpcc_irqs,
  1921 + .mpu_irqs = am33xx_tpcc_irqs,
1928 1922 .main_clk = "tpcc_ick",
1929 1923 .clkdm_name = "l3_clkdm",
1930   - .prcm = {
1931   - .omap4 = {
  1924 + .prcm = {
  1925 + .omap4 = {
1932 1926 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1933 1927 .modulemode = MODULEMODE_SWCTRL,
1934 1928 },
1935 1929  
1936 1930  
1937 1931  
... ... @@ -1937,23 +1931,23 @@
1937 1931  
1938 1932 /* 'tptc' class */
1939 1933 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1940   - .name = "tptc",
  1934 + .name = "tptc",
1941 1935 };
1942 1936  
1943 1937 /* tptc0 */
1944 1938 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1945   - { .irq = 112 },
1946   - { .irq = -1 }
  1939 + { .irq = AM33XX_IRQ_TPTC0 },
  1940 + { .irq = -1 },
1947 1941 };
1948 1942  
1949 1943 static struct omap_hwmod am33xx_tptc0_hwmod = {
1950 1944 .name = "tptc0",
1951 1945 .class = &am33xx_tptc_hwmod_class,
1952   - .mpu_irqs = am33xx_tptc0_irqs,
  1946 + .mpu_irqs = am33xx_tptc0_irqs,
1953 1947 .main_clk = "tptc0_ick",
1954 1948 .clkdm_name = "l3_clkdm",
1955   - .prcm = {
1956   - .omap4 = {
  1949 + .prcm = {
  1950 + .omap4 = {
1957 1951 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1958 1952 .modulemode = MODULEMODE_SWCTRL,
1959 1953 },
1960 1954  
1961 1955  
... ... @@ -1962,18 +1956,18 @@
1962 1956  
1963 1957 /* tptc1 */
1964 1958 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1965   - { .irq = 113 },
1966   - { .irq = -1 }
  1959 + { .irq = AM33XX_IRQ_TPTC1 },
  1960 + { .irq = -1 },
1967 1961 };
1968 1962  
1969 1963 static struct omap_hwmod am33xx_tptc1_hwmod = {
1970 1964 .name = "tptc1",
1971 1965 .class = &am33xx_tptc_hwmod_class,
1972   - .mpu_irqs = am33xx_tptc1_irqs,
  1966 + .mpu_irqs = am33xx_tptc1_irqs,
1973 1967 .main_clk = "tptc1_ick",
1974 1968 .clkdm_name = "l3_clkdm",
1975   - .prcm = {
1976   - .omap4 = {
  1969 + .prcm = {
  1970 + .omap4 = {
1977 1971 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1978 1972 .modulemode = MODULEMODE_SWCTRL,
1979 1973 },
1980 1974  
1981 1975  
... ... @@ -1982,18 +1976,18 @@
1982 1976  
1983 1977 /* tptc2 */
1984 1978 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1985   - { .irq = 114 },
1986   - { .irq = -1 }
  1979 + { .irq = AM33XX_IRQ_TPTC2 },
  1980 + { .irq = -1 },
1987 1981 };
1988 1982  
1989 1983 static struct omap_hwmod am33xx_tptc2_hwmod = {
1990 1984 .name = "tptc2",
1991 1985 .class = &am33xx_tptc_hwmod_class,
1992   - .mpu_irqs = am33xx_tptc2_irqs,
  1986 + .mpu_irqs = am33xx_tptc2_irqs,
1993 1987 .main_clk = "tptc2_ick",
1994 1988 .clkdm_name = "l3_clkdm",
1995   - .prcm = {
1996   - .omap4 = {
  1989 + .prcm = {
  1990 + .omap4 = {
1997 1991 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1998 1992 .modulemode = MODULEMODE_SWCTRL,
1999 1993 },
2000 1994  
2001 1995  
... ... @@ -2006,15 +2000,15 @@
2006 2000 .sysc_offs = 0x54,
2007 2001 .syss_offs = 0x58,
2008 2002 .sysc_flags = (SYSC_HAS_SIDLEMODE |
2009   - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2010   - SYSC_HAS_AUTOIDLE),
  2003 + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  2004 + SYSC_HAS_AUTOIDLE),
2011 2005 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2012   - .sysc_fields = &omap_hwmod_sysc_type1,
  2006 + .sysc_fields = &omap_hwmod_sysc_type1,
2013 2007 };
2014 2008  
2015 2009 static struct omap_hwmod_class uart_class = {
2016   - .name = "uart",
2017   - .sysc = &uart_sysc,
  2010 + .name = "uart",
  2011 + .sysc = &uart_sysc,
2018 2012 };
2019 2013  
2020 2014 /* uart1 */
... ... @@ -2041,7 +2035,7 @@
2041 2035 };
2042 2036  
2043 2037 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
2044   - { .irq = 72 },
  2038 + { .irq = AM33XX_IRQ_UART0 },
2045 2039 { .irq = -1 }
2046 2040 };
2047 2041  
2048 2042  
... ... @@ -2052,12 +2046,12 @@
2052 2046 static struct omap_hwmod am33xx_uart1_hwmod = {
2053 2047 .name = "uart1",
2054 2048 .class = &uart_class,
2055   - .mpu_irqs = am33xx_uart1_irqs,
  2049 + .mpu_irqs = am33xx_uart1_irqs,
2056 2050 .sdma_reqs = uart1_edma_reqs,
2057 2051 .main_clk = "uart1_fck",
2058 2052 .clkdm_name = "l4_wkup_clkdm",
2059   - .prcm = {
2060   - .omap4 = {
  2053 + .prcm = {
  2054 + .omap4 = {
2061 2055 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2062 2056 .modulemode = MODULEMODE_SWCTRL,
2063 2057 },
... ... @@ -2083,8 +2077,8 @@
2083 2077 };
2084 2078  
2085 2079 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2086   - { .irq = 73 },
2087   - { .irq = -1 }
  2080 + { .irq = AM33XX_IRQ_UART1 },
  2081 + { .irq = -1 },
2088 2082 };
2089 2083  
2090 2084 static struct omap_hwmod_ocp_if *am33xx_uart2_slaves[] = {
2091 2085  
... ... @@ -2094,12 +2088,12 @@
2094 2088 static struct omap_hwmod am33xx_uart2_hwmod = {
2095 2089 .name = "uart2",
2096 2090 .class = &uart_class,
2097   - .mpu_irqs = am33xx_uart2_irqs,
  2091 + .mpu_irqs = am33xx_uart2_irqs,
2098 2092 .main_clk = "uart2_fck",
2099 2093 .clkdm_name = "l4ls_clkdm",
2100 2094 .sdma_reqs = uart1_edma_reqs,
2101   - .prcm = {
2102   - .omap4 = {
  2095 + .prcm = {
  2096 + .omap4 = {
2103 2097 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2104 2098 .modulemode = MODULEMODE_SWCTRL,
2105 2099 },
... ... @@ -2125,8 +2119,8 @@
2125 2119 };
2126 2120  
2127 2121 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2128   - { .irq = 74 },
2129   - { .irq = -1 }
  2122 + { .irq = AM33XX_IRQ_UART2 },
  2123 + { .irq = -1 },
2130 2124 };
2131 2125  
2132 2126 static struct omap_hwmod_ocp_if *am33xx_uart3_slaves[] = {
2133 2127  
... ... @@ -2136,12 +2130,12 @@
2136 2130 static struct omap_hwmod am33xx_uart3_hwmod = {
2137 2131 .name = "uart3",
2138 2132 .class = &uart_class,
2139   - .mpu_irqs = am33xx_uart3_irqs,
  2133 + .mpu_irqs = am33xx_uart3_irqs,
2140 2134 .main_clk = "uart3_fck",
2141 2135 .clkdm_name = "l4ls_clkdm",
2142 2136 .sdma_reqs = uart1_edma_reqs,
2143   - .prcm = {
2144   - .omap4 = {
  2137 + .prcm = {
  2138 + .omap4 = {
2145 2139 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2146 2140 .modulemode = MODULEMODE_SWCTRL,
2147 2141 },
... ... @@ -2167,8 +2161,8 @@
2167 2161 };
2168 2162  
2169 2163 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2170   - { .irq = 44 },
2171   - { .irq = -1 }
  2164 + { .irq = AM33XX_IRQ_UART3 },
  2165 + { .irq = -1 },
2172 2166 };
2173 2167  
2174 2168 static struct omap_hwmod_ocp_if *am33xx_uart4_slaves[] = {
2175 2169  
... ... @@ -2178,12 +2172,12 @@
2178 2172 static struct omap_hwmod am33xx_uart4_hwmod = {
2179 2173 .name = "uart4",
2180 2174 .class = &uart_class,
2181   - .mpu_irqs = am33xx_uart4_irqs,
  2175 + .mpu_irqs = am33xx_uart4_irqs,
2182 2176 .main_clk = "uart4_fck",
2183 2177 .clkdm_name = "l4ls_clkdm",
2184 2178 .sdma_reqs = uart1_edma_reqs,
2185   - .prcm = {
2186   - .omap4 = {
  2179 + .prcm = {
  2180 + .omap4 = {
2187 2181 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2188 2182 .modulemode = MODULEMODE_SWCTRL,
2189 2183 },
... ... @@ -2209,8 +2203,8 @@
2209 2203 };
2210 2204  
2211 2205 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2212   - { .irq = 45 },
2213   - { .irq = -1 }
  2206 + { .irq = AM33XX_IRQ_UART4 },
  2207 + { .irq = -1 },
2214 2208 };
2215 2209  
2216 2210 static struct omap_hwmod_ocp_if *am33xx_uart5_slaves[] = {
2217 2211  
... ... @@ -2220,12 +2214,12 @@
2220 2214 static struct omap_hwmod am33xx_uart5_hwmod = {
2221 2215 .name = "uart5",
2222 2216 .class = &uart_class,
2223   - .mpu_irqs = am33xx_uart5_irqs,
  2217 + .mpu_irqs = am33xx_uart5_irqs,
2224 2218 .main_clk = "uart5_fck",
2225 2219 .clkdm_name = "l4ls_clkdm",
2226 2220 .sdma_reqs = uart1_edma_reqs,
2227   - .prcm = {
2228   - .omap4 = {
  2221 + .prcm = {
  2222 + .omap4 = {
2229 2223 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2230 2224 .modulemode = MODULEMODE_SWCTRL,
2231 2225 },
... ... @@ -2251,8 +2245,8 @@
2251 2245 };
2252 2246  
2253 2247 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2254   - { .irq = 46 },
2255   - { .irq = -1 }
  2248 + { .irq = AM33XX_IRQ_UART5 },
  2249 + { .irq = -1 },
2256 2250 };
2257 2251  
2258 2252 static struct omap_hwmod_ocp_if *am33xx_uart6_slaves[] = {
2259 2253  
... ... @@ -2262,12 +2256,12 @@
2262 2256 static struct omap_hwmod am33xx_uart6_hwmod = {
2263 2257 .name = "uart6",
2264 2258 .class = &uart_class,
2265   - .mpu_irqs = am33xx_uart6_irqs,
  2259 + .mpu_irqs = am33xx_uart6_irqs,
2266 2260 .main_clk = "uart6_fck",
2267 2261 .clkdm_name = "l4ls_clkdm",
2268 2262 .sdma_reqs = uart1_edma_reqs,
2269   - .prcm = {
2270   - .omap4 = {
  2263 + .prcm = {
  2264 + .omap4 = {
2271 2265 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2272 2266 .modulemode = MODULEMODE_SWCTRL,
2273 2267 },
2274 2268  
... ... @@ -2283,11 +2277,11 @@
2283 2277  
2284 2278 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
2285 2279 {
2286   - .pa_start = 0x44E35000,
2287   - .pa_end = 0x44E35000 + SZ_4K - 1,
  2280 + .pa_start = AM33XX_WDT1_BASE,
  2281 + .pa_end = AM33XX_WDT1_BASE + SZ_4K - 1,
2288 2282 .flags = ADDR_TYPE_RT
2289 2283 },
2290   - { }
  2284 + { },
2291 2285 };
2292 2286  
2293 2287 /* l4_wkup -> wd_timer1 */
2294 2288  
... ... @@ -2312,10 +2306,10 @@
2312 2306 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2313 2307 .name = "wd_timer2",
2314 2308 .class = &am33xx_wd_timer_hwmod_class,
2315   - .main_clk = "wd_timer1_fck",
  2309 + .main_clk = "wdt1_fck",
2316 2310 .clkdm_name = "l4_wkup_clkdm",
2317   - .prcm = {
2318   - .omap4 = {
  2311 + .prcm = {
  2312 + .omap4 = {
2319 2313 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2320 2314 .modulemode = MODULEMODE_SWCTRL,
2321 2315 },
2322 2316  
... ... @@ -2324,29 +2318,9 @@
2324 2318 .slaves_cnt = ARRAY_SIZE(am33xx_wd_timer1_slaves),
2325 2319 };
2326 2320  
2327   -/* wdt0 */
2328   -static struct omap_hwmod_irq_info am33xx_wdt0_irqs[] = {
2329   - { .irq = 15 },
2330   - { .irq = -1 }
2331   -};
2332   -
2333   -static struct omap_hwmod am33xx_wdt0_hwmod = {
2334   - .name = "wdt0",
2335   - .class = &am33xx_wd_timer_hwmod_class,
2336   - .mpu_irqs = am33xx_wdt0_irqs,
2337   - .main_clk = "wdt0_fck",
2338   - .clkdm_name = "l4_wkup_clkdm",
2339   - .prcm = {
2340   - .omap4 = {
2341   - .clkctrl_offs = AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET,
2342   - .modulemode = MODULEMODE_SWCTRL,
2343   - },
2344   - },
2345   -};
2346   -
2347 2321 /* 'wkup_m3' class */
2348 2322 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
2349   - .name = "wkup_m3",
  2323 + .name = "wkup_m3",
2350 2324 };
2351 2325  
2352 2326 /* wkup_m3 */
... ... @@ -2355,8 +2329,8 @@
2355 2329 .class = &am33xx_wkup_m3_hwmod_class,
2356 2330 .clkdm_name = "l4_wkup_aon_clkdm",
2357 2331 .main_clk = "wkup_m3_fck",
2358   - .prcm = {
2359   - .omap4 = {
  2332 + .prcm = {
  2333 + .omap4 = {
2360 2334 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
2361 2335 .modulemode = MODULEMODE_SWCTRL,
2362 2336 },
2363 2337  
2364 2338  
... ... @@ -2367,20 +2341,20 @@
2367 2341 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
2368 2342 {
2369 2343 .name = "usbss",
2370   - .pa_start = 0x47400000,
2371   - .pa_end = 0x47400000 + SZ_4K - 1,
  2344 + .pa_start = AM33XX_USBSS_BASE,
  2345 + .pa_end = AM33XX_USBSS_BASE + SZ_4K - 1,
2372 2346 .flags = ADDR_TYPE_RT
2373 2347 },
2374 2348 {
2375 2349 .name = "musb0",
2376   - .pa_start = 0x47401000,
2377   - .pa_end = 0x47401000 + SZ_2K - 1,
  2350 + .pa_start = AM33XX_USB0_BASE,
  2351 + .pa_end = AM33XX_USB0_BASE + SZ_2K - 1,
2378 2352 .flags = ADDR_TYPE_RT
2379 2353 },
2380 2354 {
2381 2355 .name = "musb1",
2382   - .pa_start = 0x47401800,
2383   - .pa_end = 0x47401800 + SZ_2K - 1,
  2356 + .pa_start = AM33XX_USB1_BASE,
  2357 + .pa_end = AM33XX_USB1_BASE + SZ_2K - 1,
2384 2358 .flags = ADDR_TYPE_RT
2385 2359 },
2386 2360 {
2387 2361  
... ... @@ -2396,14 +2370,14 @@
2396 2370 };
2397 2371  
2398 2372 static struct omap_hwmod_class am33xx_usbotg_class = {
2399   - .name = "usbotg",
2400   - .sysc = &am33xx_usbhsotg_sysc,
  2373 + .name = "usbotg",
  2374 + .sysc = &am33xx_usbhsotg_sysc,
2401 2375 };
2402 2376  
2403 2377 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2404   - { .name = "usbss-irq", .irq = 17, },
2405   - { .name = "musb0-irq", .irq = 18, },
2406   - { .name = "musb1-irq", .irq = 19, },
  2378 + { .name = "usbss-irq", .irq = AM33XX_IRQ_USBSS, },
  2379 + { .name = "musb0-irq", .irq = AM33XX_IRQ_USB0, },
  2380 + { .name = "musb1-irq", .irq = AM33XX_IRQ_USB1, },
2407 2381 { .irq = -1, },
2408 2382 };
2409 2383  
... ... @@ -2422,6 +2396,7 @@
2422 2396 static struct omap_hwmod_opt_clk usbss_opt_clks[] = {
2423 2397 { .role = "clkdcoldo", .clk = "usbotg_fck" },
2424 2398 };
  2399 +
2425 2400 static struct omap_hwmod am33xx_usbss_hwmod = {
2426 2401 .name = "usb_otg_hs",
2427 2402 .mpu_irqs = am33xx_usbss_mpu_irqs,
... ... @@ -2429,7 +2404,7 @@
2429 2404 .clkdm_name = "l4ls_clkdm",
2430 2405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2431 2406 .prcm = {
2432   - .omap4 = {
  2407 + .omap4 = {
2433 2408 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2434 2409 .modulemode = MODULEMODE_SWCTRL,
2435 2410 },
... ... @@ -2441,6 +2416,42 @@
2441 2416 .class = &am33xx_usbotg_class,
2442 2417 };
2443 2418  
  2419 +/* sgx/gfx */
  2420 +/* Pseudo hwmod for reset control purpose only */
  2421 +static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
  2422 + .name = "gfx",
  2423 +};
  2424 +
  2425 +static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
  2426 + { .name = "gfx", .rst_shift = 0, .st_shift = 0 },
  2427 +};
  2428 +
  2429 +static struct omap_hwmod am33xx_gfx_hwmod = {
  2430 + .name = "gfx",
  2431 + .class = &am33xx_gfx_hwmod_class,
  2432 + .clkdm_name = "gfx_l3_clkdm",
  2433 + .rst_lines = am33xx_gfx_resets,
  2434 + .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
  2435 +};
  2436 +
  2437 +/* PRUSS/ICSS */
  2438 +/* Pseudo hwmod for reset control purpose only */
  2439 +static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
  2440 + .name = "pruss",
  2441 +};
  2442 +
  2443 +static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
  2444 + { .name = "pruss", .rst_shift = 1, .st_shift = 1 },
  2445 +};
  2446 +
  2447 +static struct omap_hwmod am33xx_pruss_hwmod = {
  2448 + .name = "pruss",
  2449 + .class = &am33xx_pruss_hwmod_class,
  2450 + .clkdm_name = "icss_ocp_clkdm",
  2451 + .rst_lines = am33xx_pruss_resets,
  2452 + .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
  2453 +};
  2454 +
2444 2455 static __initdata struct omap_hwmod *am33xx_hwmods[] = {
2445 2456 /* l3 class */
2446 2457 &am33xx_l3_instr_hwmod,
2447 2458  
... ... @@ -2541,13 +2552,20 @@
2541 2552 &am33xx_usbss_hwmod,
2542 2553 /* cpgmac0 class */
2543 2554 &am33xx_cpgmac0_hwmod,
2544   - &am33xx_wdt0_hwmod, /* Secure WDT */
2545 2555 /* tptc class */
2546 2556 &am33xx_tptc0_hwmod,
2547 2557 &am33xx_tptc1_hwmod,
2548 2558 &am33xx_tptc2_hwmod,
2549 2559 /* tpcc class */
2550 2560 &am33xx_tpcc_hwmod,
  2561 + /* LCDC class */
  2562 + &am33xx_lcdc_hwmod,
  2563 + /* gfx/sgx */
  2564 + &am33xx_gfx_hwmod,
  2565 + /* pruss/icss */
  2566 + &am33xx_pruss_hwmod,
  2567 + /* rtc */
  2568 + &am33xx_rtc_hwmod,
2551 2569 NULL,
2552 2570 };
2553 2571  
arch/arm/plat-omap/include/plat/am33xx.h
Diff comments   View file @ 7a4a31c
... ... @@ -27,6 +27,17 @@
27 27 #define AM33XX_GPIO2_BASE 0x481AC000
28 28 #define AM33XX_GPIO3_BASE 0x481AE000
29 29  
  30 +#define AM33XX_TIMER0_BASE 0x44E05000
  31 +#define AM33XX_TIMER1_BASE 0x44E31000
  32 +#define AM33XX_TIMER2_BASE 0x48040000
  33 +#define AM33XX_TIMER3_BASE 0x48042000
  34 +#define AM33XX_TIMER4_BASE 0x48044000
  35 +#define AM33XX_TIMER5_BASE 0x48046000
  36 +#define AM33XX_TIMER6_BASE 0x48048000
  37 +#define AM33XX_TIMER7_BASE 0x4804A000
  38 +
  39 +#define AM33XX_WDT1_BASE 0x44E35000
  40 +
30 41 #define AM33XX_TSC_BASE 0x44E0D000
31 42 #define AM33XX_RTC_BASE 0x44E3E000
32 43  
33 44  
... ... @@ -40,8 +51,26 @@
40 51 #define AM33XX_MMC1_BASE 0x481D8100
41 52 #define AM33XX_MMC2_BASE 0x47810100
42 53  
  54 +#define AM33XX_I2C0_BASE 0x44E0B000
  55 +#define AM33XX_I2C1_BASE 0x4802A000
  56 +#define AM33XX_I2C2_BASE 0x4819C000
  57 +
43 58 #define AM33XX_SPI0_BASE 0x48030000
44 59 #define AM33XX_SPI1_BASE 0x481A0000
  60 +
  61 +#define AM33XX_DCAN0_BASE 0x481CC000
  62 +#define AM33XX_DCAN1_BASE 0x481D0000
  63 +
  64 +#define AM33XX_USBSS_BASE 0x47400000
  65 +#define AM33XX_USB0_BASE 0x47401000
  66 +#define AM33XX_USB1_BASE 0x47401800
  67 +
  68 +#define AM33XX_ASP0_BASE 0x48038000
  69 +#define AM33XX_ASP1_BASE 0x4803C000
  70 +
  71 +#define AM33XX_MMC0_BASE 0x48060100
  72 +#define AM33XX_MMC1_BASE 0x481D8100
  73 +#define AM33XX_MMC2_BASE 0x47810100
45 74  
46 75 #define AM33XX_CPSW_BASE 0x4A100000
47 76 #define AM33XX_CPSW_MDIO_BASE 0x4A101000
arch/arm/plat-omap/include/plat/irqs-am33xx.h
Diff comments   View file @ 7a4a31c
... ... @@ -28,9 +28,9 @@
28 28 #define AM33XX_IRQ_TPCC0_ERRINT_PO 14
29 29 #define AM33XX_IRQ_WDT0 15
30 30 #define AM33XX_IRQ_ADC_GEN 16
31   -#define AM33XX_IRQ_USB_SS 17
32   -#define AM33XX_IRQ_USB_0 18
33   -#define AM33XX_IRQ_USB_1 19
  31 +#define AM33XX_IRQ_USBSS 17
  32 +#define AM33XX_IRQ_USB0 18
  33 +#define AM33XX_IRQ_USB1 19
34 34 #define AM33XX_IRQ_ICSS0_0 20
35 35 #define AM33XX_IRQ_ICSS0_1 21
36 36 #define AM33XX_IRQ_ICSS0_2 22
... ... @@ -59,10 +59,10 @@
59 59 #define AM33XX_IRQ_UART4 45
60 60 #define AM33XX_IRQ_UART5 46
61 61 #define AM33XX_IRQ_PWMSS1_ECAP 47
62   -#define AM33XX_IRQ_PCI_0 48
63   -#define AM33XX_IRQ_PCI_1 49
64   -#define AM33XX_IRQ_PCI_2 50
65   -#define AM33XX_IRQ_PCI_3 51
  62 +#define AM33XX_IRQ_PCI0 48
  63 +#define AM33XX_IRQ_PCI1 49
  64 +#define AM33XX_IRQ_PCI2 50
  65 +#define AM33XX_IRQ_PCI3 51
66 66 #define AM33XX_IRQ_DCAN0_0 52
67 67 #define AM33XX_IRQ_DCAN0_1 53
68 68 #define AM33XX_IRQ_DCAN0_UERR 54
... ... @@ -77,10 +77,10 @@
77 77 #define AM33XX_IRQ_GPIO3_2 63
78 78 #define AM33XX_IRQ_MMCHS0 64
79 79 #define AM33XX_IRQ_MCSPIOCP0 65
80   -#define AM33XX_IRQ_DMTIMER 66
81   -#define AM33XX_IRQ_DMTIMER_1 67
82   -#define AM33XX_IRQ_DMTIMER_2 68
83   -#define AM33XX_IRQ_DMTIMER_3 69
  80 +#define AM33XX_IRQ_DMTIMER0 66
  81 +#define AM33XX_IRQ_DMTIMER1 67
  82 +#define AM33XX_IRQ_DMTIMER2 68
  83 +#define AM33XX_IRQ_DMTIMER3 69
84 84 #define AM33XX_IRQ_MSHSI2COCP0 70
85 85 #define AM33XX_IRQ_MSHSI2COCP1 71
86 86 #define AM33XX_IRQ_UART0 72
... ... @@ -103,10 +103,10 @@
103 103 #define AM33XX_IRQ_PWMSS2_EQEP 89
104 104 #define AM33XX_IRQ_DMA 90
105 105 #define AM33XX_IRQ_WDT1 91
106   -#define AM33XX_IRQ_DMTIMER_4 92
107   -#define AM33XX_IRQ_DMTIMER_5 93
108   -#define AM33XX_IRQ_DMTIMER_6 94
109   -#define AM33XX_IRQ_DMTIMER_7 95
  106 +#define AM33XX_IRQ_DMTIMER4 92
  107 +#define AM33XX_IRQ_DMTIMER5 93
  108 +#define AM33XX_IRQ_DMTIMER6 94
  109 +#define AM33XX_IRQ_DMTIMER7 95
110 110 #define AM33XX_IRQ_GPIO0_1 96
111 111 #define AM33XX_IRQ_GPIO0_2 97
112 112 #define AM33XX_IRQ_GPIO1_1 98
... ... @@ -126,10 +126,11 @@
126 126 #define AM33XX_IRQ_TPTC0 112
127 127 #define AM33XX_IRQ_TPTC1 113
128 128 #define AM33XX_IRQ_TPTC2 114
129   -#define AM33XX_IRQ_SDMA_0 116
130   -#define AM33XX_IRQ_SDMA_1 117
131   -#define AM33XX_IRQ_SDMA_2 118
132   -#define AM33XX_IRQ_SDMA_3 119
  129 +#define AM33XX_IRQ_TSC 115
  130 +#define AM33XX_IRQ_SDMA0 116
  131 +#define AM33XX_IRQ_SDMA1 117
  132 +#define AM33XX_IRQ_SDMA2 118
  133 +#define AM33XX_IRQ_SDMA3 119
133 134 #define AM33XX_IRQ_SMARTREFLEX0 120
134 135 #define AM33XX_IRQ_SMARTREFLEX1 121
135 136 #define AM33XX_IRQ_NETRA_MMU 122