Commit 7ce1a9f88aea036034e5e7dc65480694e7e0913d

Authored by Russ Dill
Committed by Vaibhav Hiremath
1 parent 931e7f0032

IIO: ti_adc: Handle set to clear IRQENABLE register properly.

The driver is currently mishandling the IRQENABLE register. The driver
should write a 1 for bits it wishes to set, and a zero for bits it does not
wish to change. The read of the current register contents is not
necessary.

Write 0 = No action.
Read 0 = Interrupt disabled (masked).
Read 1 = Interrupt enabled.
Write 1 = Enable interrupt.

The current read/update/write method is currently not causing any
problems, but could cause confusion in the future.

Signed-off-by: Russ Dill <Russ.Dill@ti.com>

Showing 1 changed file with 4 additions and 6 deletions Side-by-side Diff

drivers/staging/iio/adc/ti_adc.c
... ... @@ -192,7 +192,7 @@
192 192 container_of(work_s, struct adc_device, poll_work);
193 193 struct iio_dev *idev = iio_priv_to_dev(adc_dev);
194 194 struct iio_buffer *buffer = idev->buffer;
195   - unsigned int fifo1count, readx1, status;
  195 + unsigned int fifo1count, readx1;
196 196 int i;
197 197 u32 *iBuf;
198 198  
199 199  
... ... @@ -216,9 +216,8 @@
216 216 }
217 217  
218 218 buffer->access->store_to(buffer, (u8 *) iBuf, iio_get_time_ns());
219   - status = adc_readl(adc_dev, TSCADC_REG_IRQENABLE);
220 219 adc_writel(adc_dev, TSCADC_REG_IRQENABLE,
221   - (status | TSCADC_IRQENB_FIFO1THRES));
  220 + TSCADC_IRQENB_FIFO1THRES);
222 221  
223 222 kfree(iBuf);
224 223 }
... ... @@ -235,7 +234,7 @@
235 234 {
236 235 struct adc_device *adc_dev = iio_priv(idev);
237 236 struct iio_buffer *buffer = idev->buffer;
238   - unsigned int enb, status, fifo1count;
  237 + unsigned int enb, fifo1count;
239 238 int stepnum, i;
240 239 u8 bit;
241 240  
242 241  
... ... @@ -243,9 +242,8 @@
243 242 pr_info("Data cannot be read continuously in one shot mode\n");
244 243 return -EINVAL;
245 244 } else {
246   - status = adc_readl(adc_dev, TSCADC_REG_IRQENABLE);
247 245 adc_writel(adc_dev, TSCADC_REG_IRQENABLE,
248   - (status | TSCADC_IRQENB_FIFO1THRES |
  246 + (TSCADC_IRQENB_FIFO1THRES |
249 247 TSCADC_IRQENB_FIFO1OVRRUN |
250 248 TSCADC_IRQENB_FIFO1UNDRFLW));
251 249