Eric Lee / linux-smarc-t335x-v3.2

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Commit 824877111cd7f2b4fd2fe6947c5c5cbbb3ac5bd8

Authored by Jaswinder Singh Rajput
Committed by Ingo Molnar
1 parent c854c91979
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

x86, pci: move arch/x86/pci/pci.h to arch/x86/include/asm/pci_x86.h 

Impact: cleanup

Now that arch/x86/pci/pci.h is used in a number of other places as well,
move the lowlevel x86 pci definitions into the architecture include files.
(not to be confused with the existing arch/x86/include/asm/pci.h file,
which provides public details about x86 PCI)

Tested on: X86_32_UP, X86_32_SMP and X86_64_SMP

Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

Showing 24 changed files with 188 additions and 194 deletions Side-by-side Diff

arch/x86/include/asm/pci_x86.h
Diff comments   View file @ 8248771
  1 +/*
  2 + * Low-Level PCI Access for i386 machines.
  3 + *
  4 + * (c) 1999 Martin Mares <mj@ucw.cz>
  5 + */
  6 +
  7 +#undef DEBUG
  8 +
  9 +#ifdef DEBUG
  10 +#define DBG(x...) printk(x)
  11 +#else
  12 +#define DBG(x...)
  13 +#endif
  14 +
  15 +#define PCI_PROBE_BIOS 0x0001
  16 +#define PCI_PROBE_CONF1 0x0002
  17 +#define PCI_PROBE_CONF2 0x0004
  18 +#define PCI_PROBE_MMCONF 0x0008
  19 +#define PCI_PROBE_MASK 0x000f
  20 +#define PCI_PROBE_NOEARLY 0x0010
  21 +
  22 +#define PCI_NO_CHECKS 0x0400
  23 +#define PCI_USE_PIRQ_MASK 0x0800
  24 +#define PCI_ASSIGN_ROMS 0x1000
  25 +#define PCI_BIOS_IRQ_SCAN 0x2000
  26 +#define PCI_ASSIGN_ALL_BUSSES 0x4000
  27 +#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
  28 +#define PCI_USE__CRS 0x10000
  29 +#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
  30 +#define PCI_HAS_IO_ECS 0x40000
  31 +#define PCI_NOASSIGN_ROMS 0x80000
  32 +
  33 +extern unsigned int pci_probe;
  34 +extern unsigned long pirq_table_addr;
  35 +
  36 +enum pci_bf_sort_state {
  37 + pci_bf_sort_default,
  38 + pci_force_nobf,
  39 + pci_force_bf,
  40 + pci_dmi_bf,
  41 +};
  42 +
  43 +/* pci-i386.c */
  44 +
  45 +extern unsigned int pcibios_max_latency;
  46 +
  47 +void pcibios_resource_survey(void);
  48 +
  49 +/* pci-pc.c */
  50 +
  51 +extern int pcibios_last_bus;
  52 +extern struct pci_bus *pci_root_bus;
  53 +extern struct pci_ops pci_root_ops;
  54 +
  55 +/* pci-irq.c */
  56 +
  57 +struct irq_info {
  58 + u8 bus, devfn; /* Bus, device and function */
  59 + struct {
  60 + u8 link; /* IRQ line ID, chipset dependent,
  61 + 0 = not routed */
  62 + u16 bitmap; /* Available IRQs */
  63 + } __attribute__((packed)) irq[4];
  64 + u8 slot; /* Slot number, 0=onboard */
  65 + u8 rfu;
  66 +} __attribute__((packed));
  67 +
  68 +struct irq_routing_table {
  69 + u32 signature; /* PIRQ_SIGNATURE should be here */
  70 + u16 version; /* PIRQ_VERSION */
  71 + u16 size; /* Table size in bytes */
  72 + u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
  73 + u16 exclusive_irqs; /* IRQs devoted exclusively to
  74 + PCI usage */
  75 + u16 rtr_vendor, rtr_device; /* Vendor and device ID of
  76 + interrupt router */
  77 + u32 miniport_data; /* Crap */
  78 + u8 rfu[11];
  79 + u8 checksum; /* Modulo 256 checksum must give 0 */
  80 + struct irq_info slots[0];
  81 +} __attribute__((packed));
  82 +
  83 +extern unsigned int pcibios_irq_mask;
  84 +
  85 +extern int pcibios_scanned;
  86 +extern spinlock_t pci_config_lock;
  87 +
  88 +extern int (*pcibios_enable_irq)(struct pci_dev *dev);
  89 +extern void (*pcibios_disable_irq)(struct pci_dev *dev);
  90 +
  91 +struct pci_raw_ops {
  92 + int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
  93 + int reg, int len, u32 *val);
  94 + int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
  95 + int reg, int len, u32 val);
  96 +};
  97 +
  98 +extern struct pci_raw_ops *raw_pci_ops;
  99 +extern struct pci_raw_ops *raw_pci_ext_ops;
  100 +
  101 +extern struct pci_raw_ops pci_direct_conf1;
  102 +extern bool port_cf9_safe;
  103 +
  104 +/* arch_initcall level */
  105 +extern int pci_direct_probe(void);
  106 +extern void pci_direct_init(int type);
  107 +extern void pci_pcbios_init(void);
  108 +extern int pci_olpc_init(void);
  109 +extern void __init dmi_check_pciprobe(void);
  110 +extern void __init dmi_check_skip_isa_align(void);
  111 +
  112 +/* some common used subsys_initcalls */
  113 +extern int __init pci_acpi_init(void);
  114 +extern int __init pcibios_irq_init(void);
  115 +extern int __init pci_visws_init(void);
  116 +extern int __init pci_numaq_init(void);
  117 +extern int __init pcibios_init(void);
  118 +
  119 +/* pci-mmconfig.c */
  120 +
  121 +extern int __init pci_mmcfg_arch_init(void);
  122 +extern void __init pci_mmcfg_arch_free(void);
  123 +
  124 +/*
  125 + * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
  126 + * on their northbrige except through the * %eax register. As such, you MUST
  127 + * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
  128 + * accessor functions.
  129 + * In fact just use pci_config_*, nothing else please.
  130 + */
  131 +static inline unsigned char mmio_config_readb(void __iomem *pos)
  132 +{
  133 + u8 val;
  134 + asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
  135 + return val;
  136 +}
  137 +
  138 +static inline unsigned short mmio_config_readw(void __iomem *pos)
  139 +{
  140 + u16 val;
  141 + asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
  142 + return val;
  143 +}
  144 +
  145 +static inline unsigned int mmio_config_readl(void __iomem *pos)
  146 +{
  147 + u32 val;
  148 + asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
  149 + return val;
  150 +}
  151 +
  152 +static inline void mmio_config_writeb(void __iomem *pos, u8 val)
  153 +{
  154 + asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
  155 +}
  156 +
  157 +static inline void mmio_config_writew(void __iomem *pos, u16 val)
  158 +{
  159 + asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
  160 +}
  161 +
  162 +static inline void mmio_config_writel(void __iomem *pos, u32 val)
  163 +{
  164 + asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
  165 +}
arch/x86/kernel/mmconf-fam10h_64.c
Diff comments   View file @ 8248771
... ... @@ -13,8 +13,7 @@
13 13 #include <asm/msr.h>
14 14 #include <asm/acpi.h>
15 15 #include <asm/mmconfig.h>
16   -
17   -#include "../pci/pci.h"
  16 +#include <asm/pci_x86.h>
18 17  
19 18 struct pci_hostbridge_probe {
20 19 u32 bus;
arch/x86/kernel/reboot.c
Diff comments   View file @ 8248771
... ... @@ -12,6 +12,7 @@
12 12 #include <asm/proto.h>
13 13 #include <asm/reboot_fixups.h>
14 14 #include <asm/reboot.h>
  15 +#include <asm/pci_x86.h>
15 16  
16 17 #ifdef CONFIG_X86_32
17 18 # include <linux/dmi.h>
... ... @@ -22,8 +23,6 @@
22 23 #endif
23 24  
24 25 #include <mach_ipi.h>
25   -#include "../pci/pci.h"
26   -
27 26  
28 27 /*
29 28 * Power off function, if any
... ... @@ -4,7 +4,7 @@
4 4 #include <linux/irq.h>
5 5 #include <linux/dmi.h>
6 6 #include <asm/numa.h>
7   -#include "pci.h"
  7 +#include <asm/pci_x86.h>
8 8  
9 9 struct pci_root_info {
10 10 char *name;
arch/x86/pci/amd_bus.c
Diff comments   View file @ 8248771
... ... @@ -2,7 +2,7 @@
2 2 #include <linux/pci.h>
3 3 #include <linux/topology.h>
4 4 #include <linux/cpu.h>
5   -#include "pci.h"
  5 +#include <asm/pci_x86.h>
6 6  
7 7 #ifdef CONFIG_X86_64
8 8 #include <asm/pci-direct.h>
arch/x86/pci/common.c
Diff comments   View file @ 8248771
... ... @@ -14,8 +14,7 @@
14 14 #include <asm/segment.h>
15 15 #include <asm/io.h>
16 16 #include <asm/smp.h>
17   -
18   -#include "pci.h"
  17 +#include <asm/pci_x86.h>
19 18  
20 19 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
21 20 PCI_PROBE_MMCONF;
arch/x86/pci/direct.c
Diff comments   View file @ 8248771
... ... @@ -5,7 +5,7 @@
5 5 #include <linux/pci.h>
6 6 #include <linux/init.h>
7 7 #include <linux/dmi.h>
8   -#include "pci.h"
  8 +#include <asm/pci_x86.h>
9 9  
10 10 /*
11 11 * Functions for accessing PCI base (first 256 bytes) and extended
arch/x86/pci/early.c
Diff comments   View file @ 8248771
... ... @@ -2,7 +2,7 @@
2 2 #include <linux/pci.h>
3 3 #include <asm/pci-direct.h>
4 4 #include <asm/io.h>
5   -#include "pci.h"
  5 +#include <asm/pci_x86.h>
6 6  
7 7 /* Direct PCI access. This is used for PCI accesses in early boot before
8 8 the PCI subsystem works. */
arch/x86/pci/fixup.c
Diff comments   View file @ 8248771
... ... @@ -6,8 +6,7 @@
6 6 #include <linux/dmi.h>
7 7 #include <linux/pci.h>
8 8 #include <linux/init.h>
9   -#include "pci.h"
10   -
  9 +#include <asm/pci_x86.h>
11 10  
12 11 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
13 12 {
... ... @@ -34,8 +34,8 @@
34 34  
35 35 #include <asm/pat.h>
36 36 #include <asm/e820.h>
  37 +#include <asm/pci_x86.h>
37 38  
38   -#include "pci.h"
39 39  
40 40 static int
41 41 skip_isa_ioresource_align(struct pci_dev *dev) {
1 1 #include <linux/pci.h>
2 2 #include <linux/init.h>
3   -#include "pci.h"
  3 +#include <asm/pci_x86.h>
4 4  
5 5 /* arch_initcall has too random ordering, so call the initializers
6 6 in the right sequence from here. */
... ... @@ -16,8 +16,7 @@
16 16 #include <asm/io_apic.h>
17 17 #include <linux/irq.h>
18 18 #include <linux/acpi.h>
19   -
20   -#include "pci.h"
  19 +#include <asm/pci_x86.h>
21 20  
22 21 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
23 22 #define PIRQ_VERSION 0x0100
arch/x86/pci/legacy.c
Diff comments   View file @ 8248771
... ... @@ -3,7 +3,7 @@
3 3 */
4 4 #include <linux/init.h>
5 5 #include <linux/pci.h>
6   -#include "pci.h"
  6 +#include <asm/pci_x86.h>
7 7  
8 8 /*
9 9 * Discover remaining PCI buses in case there are peer host bridges.
arch/x86/pci/mmconfig-shared.c
Diff comments   View file @ 8248771
... ... @@ -15,8 +15,7 @@
15 15 #include <linux/acpi.h>
16 16 #include <linux/bitmap.h>
17 17 #include <asm/e820.h>
18   -
19   -#include "pci.h"
  18 +#include <asm/pci_x86.h>
20 19  
21 20 /* aperture is up to 256MB but BIOS may reserve less */
22 21 #define MMCONFIG_APER_MIN (2 * 1024*1024)
arch/x86/pci/mmconfig_32.c
Diff comments   View file @ 8248771
... ... @@ -13,7 +13,7 @@
13 13 #include <linux/init.h>
14 14 #include <linux/acpi.h>
15 15 #include <asm/e820.h>
16   -#include "pci.h"
  16 +#include <asm/pci_x86.h>
17 17  
18 18 /* Assume systems with more busses have correct MCFG */
19 19 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
arch/x86/pci/mmconfig_64.c
Diff comments   View file @ 8248771
... ... @@ -10,8 +10,7 @@
10 10 #include <linux/acpi.h>
11 11 #include <linux/bitmap.h>
12 12 #include <asm/e820.h>
13   -
14   -#include "pci.h"
  13 +#include <asm/pci_x86.h>
15 14  
16 15 /* Static virtual mapping of the MMCONFIG aperture */
17 16 struct mmcfg_virt {
arch/x86/pci/numaq_32.c
Diff comments   View file @ 8248771
... ... @@ -7,7 +7,7 @@
7 7 #include <linux/nodemask.h>
8 8 #include <mach_apic.h>
9 9 #include <asm/mpspec.h>
10   -#include "pci.h"
  10 +#include <asm/pci_x86.h>
11 11  
12 12 #define XQUAD_PORTIO_BASE 0xfe400000
13 13 #define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
... ... @@ -29,7 +29,7 @@
29 29 #include <linux/init.h>
30 30 #include <asm/olpc.h>
31 31 #include <asm/geode.h>
32   -#include "pci.h"
  32 +#include <asm/pci_x86.h>
33 33  
34 34 /*
35 35 * In the tables below, the first two line (8 longwords) are the
arch/x86/pci/pcbios.c
Diff comments   View file @ 8248771
... ... @@ -6,9 +6,8 @@
6 6 #include <linux/init.h>
7 7 #include <linux/module.h>
8 8 #include <linux/uaccess.h>
9   -#include "pci.h"
10   -#include "pci-functions.h"
11   -
  9 +#include <asm/pci_x86.h>
  10 +#include <asm/mach-default/pci-functions.h>
12 11  
13 12 /* BIOS32 signature: "_32_" */
14 13 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
arch/x86/pci/pci.h
View file @ 8248771
1   -/*
2   - * Low-Level PCI Access for i386 machines.
3   - *
4   - * (c) 1999 Martin Mares <mj@ucw.cz>
5   - */
6   -
7   -#undef DEBUG
8   -
9   -#ifdef DEBUG
10   -#define DBG(x...) printk(x)
11   -#else
12   -#define DBG(x...)
13   -#endif
14   -
15   -#define PCI_PROBE_BIOS 0x0001
16   -#define PCI_PROBE_CONF1 0x0002
17   -#define PCI_PROBE_CONF2 0x0004
18   -#define PCI_PROBE_MMCONF 0x0008
19   -#define PCI_PROBE_MASK 0x000f
20   -#define PCI_PROBE_NOEARLY 0x0010
21   -
22   -#define PCI_NO_CHECKS 0x0400
23   -#define PCI_USE_PIRQ_MASK 0x0800
24   -#define PCI_ASSIGN_ROMS 0x1000
25   -#define PCI_BIOS_IRQ_SCAN 0x2000
26   -#define PCI_ASSIGN_ALL_BUSSES 0x4000
27   -#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
28   -#define PCI_USE__CRS 0x10000
29   -#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
30   -#define PCI_HAS_IO_ECS 0x40000
31   -#define PCI_NOASSIGN_ROMS 0x80000
32   -
33   -extern unsigned int pci_probe;
34   -extern unsigned long pirq_table_addr;
35   -
36   -enum pci_bf_sort_state {
37   - pci_bf_sort_default,
38   - pci_force_nobf,
39   - pci_force_bf,
40   - pci_dmi_bf,
41   -};
42   -
43   -/* pci-i386.c */
44   -
45   -extern unsigned int pcibios_max_latency;
46   -
47   -void pcibios_resource_survey(void);
48   -
49   -/* pci-pc.c */
50   -
51   -extern int pcibios_last_bus;
52   -extern struct pci_bus *pci_root_bus;
53   -extern struct pci_ops pci_root_ops;
54   -
55   -/* pci-irq.c */
56   -
57   -struct irq_info {
58   - u8 bus, devfn; /* Bus, device and function */
59   - struct {
60   - u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
61   - u16 bitmap; /* Available IRQs */
62   - } __attribute__((packed)) irq[4];
63   - u8 slot; /* Slot number, 0=onboard */
64   - u8 rfu;
65   -} __attribute__((packed));
66   -
67   -struct irq_routing_table {
68   - u32 signature; /* PIRQ_SIGNATURE should be here */
69   - u16 version; /* PIRQ_VERSION */
70   - u16 size; /* Table size in bytes */
71   - u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
72   - u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
73   - u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
74   - u32 miniport_data; /* Crap */
75   - u8 rfu[11];
76   - u8 checksum; /* Modulo 256 checksum must give zero */
77   - struct irq_info slots[0];
78   -} __attribute__((packed));
79   -
80   -extern unsigned int pcibios_irq_mask;
81   -
82   -extern int pcibios_scanned;
83   -extern spinlock_t pci_config_lock;
84   -
85   -extern int (*pcibios_enable_irq)(struct pci_dev *dev);
86   -extern void (*pcibios_disable_irq)(struct pci_dev *dev);
87   -
88   -struct pci_raw_ops {
89   - int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
90   - int reg, int len, u32 *val);
91   - int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
92   - int reg, int len, u32 val);
93   -};
94   -
95   -extern struct pci_raw_ops *raw_pci_ops;
96   -extern struct pci_raw_ops *raw_pci_ext_ops;
97   -
98   -extern struct pci_raw_ops pci_direct_conf1;
99   -extern bool port_cf9_safe;
100   -
101   -/* arch_initcall level */
102   -extern int pci_direct_probe(void);
103   -extern void pci_direct_init(int type);
104   -extern void pci_pcbios_init(void);
105   -extern int pci_olpc_init(void);
106   -extern void __init dmi_check_pciprobe(void);
107   -extern void __init dmi_check_skip_isa_align(void);
108   -
109   -/* some common used subsys_initcalls */
110   -extern int __init pci_acpi_init(void);
111   -extern int __init pcibios_irq_init(void);
112   -extern int __init pci_visws_init(void);
113   -extern int __init pci_numaq_init(void);
114   -extern int __init pcibios_init(void);
115   -
116   -/* pci-mmconfig.c */
117   -
118   -extern int __init pci_mmcfg_arch_init(void);
119   -extern void __init pci_mmcfg_arch_free(void);
120   -
121   -/*
122   - * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
123   - * on their northbrige except through the * %eax register. As such, you MUST
124   - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
125   - * accessor functions.
126   - * In fact just use pci_config_*, nothing else please.
127   - */
128   -static inline unsigned char mmio_config_readb(void __iomem *pos)
129   -{
130   - u8 val;
131   - asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
132   - return val;
133   -}
134   -
135   -static inline unsigned short mmio_config_readw(void __iomem *pos)
136   -{
137   - u16 val;
138   - asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
139   - return val;
140   -}
141   -
142   -static inline unsigned int mmio_config_readl(void __iomem *pos)
143   -{
144   - u32 val;
145   - asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
146   - return val;
147   -}
148   -
149   -static inline void mmio_config_writeb(void __iomem *pos, u8 val)
150   -{
151   - asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
152   -}
153   -
154   -static inline void mmio_config_writew(void __iomem *pos, u16 val)
155   -{
156   - asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
157   -}
158   -
159   -static inline void mmio_config_writel(void __iomem *pos, u32 val)
160   -{
161   - asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
162   -}
arch/x86/pci/visws.c
Diff comments   View file @ 8248771
... ... @@ -9,10 +9,9 @@
9 9 #include <linux/init.h>
10 10  
11 11 #include <asm/setup.h>
  12 +#include <asm/pci_x86.h>
12 13 #include <asm/visws/cobalt.h>
13 14 #include <asm/visws/lithium.h>
14   -
15   -#include "pci.h"
16 15  
17 16 static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
18 17 static void pci_visws_disable_irq(struct pci_dev *dev) { }
drivers/pci/hotplug/cpqphp_core.c
Diff comments   View file @ 8248771
... ... @@ -45,7 +45,7 @@
45 45  
46 46 #include "cpqphp.h"
47 47 #include "cpqphp_nvram.h"
48   -#include "../../../arch/x86/pci/pci.h" /* horrible hack showing how processor dependent we are... */
  48 +#include <asm/pci_x86.h>
49 49  
50 50  
51 51 /* Global variables */
drivers/pci/hotplug/cpqphp_pci.c
Diff comments   View file @ 8248771
... ... @@ -37,7 +37,7 @@
37 37 #include "../pci.h"
38 38 #include "cpqphp.h"
39 39 #include "cpqphp_nvram.h"
40   -#include "../../../arch/x86/pci/pci.h" /* horrible hack showing how processor dependent we are... */
  40 +#include <asm/pci_x86.h>
41 41  
42 42  
43 43 u8 cpqhp_nic_irq;
drivers/pci/hotplug/ibmphp_core.c
Diff comments   View file @ 8248771
... ... @@ -35,7 +35,7 @@
35 35 #include <linux/delay.h>
36 36 #include <linux/wait.h>
37 37 #include "../pci.h"
38   -#include "../../../arch/x86/pci/pci.h" /* for struct irq_routing_table */
  38 +#include <asm/pci_x86.h> /* for struct irq_routing_table */
39 39 #include "ibmphp.h"
40 40  
41 41 #define attn_on(sl) ibmphp_hpc_writeslot (sl, HPC_SLOT_ATTNON)