Eric Lee / linux-smarc-t335x-v3.2

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Commit 83ea7e0fe1471508ab8e8d7b317e743fe7a05a5f

Authored by Dmitry Kasatkin
Committed by Herbert Xu
1 parent 67a730ce44
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

crypto: omap-aes - initialize aes module once per request 

AES module was initialized for every DMA transaction.
That is redundant.
Now it is initialized once per request.

Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Showing 1 changed file with 28 additions and 26 deletions Side-by-side Diff

drivers/crypto/omap-aes.c
Diff comments   View file @ 83ea7e0
... ... @@ -176,6 +176,11 @@
176 176  
177 177 static int omap_aes_hw_init(struct omap_aes_dev *dd)
178 178 {
  179 + /*
  180 + * clocks are enabled when request starts and disabled when finished.
  181 + * It may be long delays between requests.
  182 + * Device might go to off mode to save power.
  183 + */
179 184 clk_enable(dd->iclk);
180 185  
181 186 if (!(dd->flags & FLAGS_INIT)) {
182 187  
... ... @@ -190,10 +195,9 @@
190 195 __asm__ __volatile__("nop");
191 196  
192 197 if (omap_aes_wait(dd, AES_REG_SYSSTATUS,
193   - AES_REG_SYSSTATUS_RESETDONE)) {
194   - clk_disable(dd->iclk);
  198 + AES_REG_SYSSTATUS_RESETDONE))
195 199 return -ETIMEDOUT;
196   - }
  200 +
197 201 dd->flags |= FLAGS_INIT;
198 202 dd->err = 0;
199 203 }
200 204  
... ... @@ -243,10 +247,20 @@
243 247  
244 248 omap_aes_write_mask(dd, AES_REG_CTRL, val, mask);
245 249  
246   - /* start DMA or disable idle mode */
247   - omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START,
248   - AES_REG_MASK_START);
  250 + /* IN */
  251 + omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
  252 + dd->phys_base + AES_REG_DATA, 0, 4);
249 253  
  254 + omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
  255 + omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
  256 +
  257 + /* OUT */
  258 + omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
  259 + dd->phys_base + AES_REG_DATA, 0, 4);
  260 +
  261 + omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
  262 + omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
  263 +
250 264 return 0;
251 265 }
252 266  
... ... @@ -419,7 +433,6 @@
419 433 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
420 434 struct omap_aes_dev *dd = ctx->dd;
421 435 int len32;
422   - int err;
423 436  
424 437 pr_debug("len: %d\n", length);
425 438  
... ... @@ -432,12 +445,6 @@
432 445 len32 = DIV_ROUND_UP(length, sizeof(u32));
433 446  
434 447 /* IN */
435   - omap_set_dma_dest_params(dd->dma_lch_in, 0, OMAP_DMA_AMODE_CONSTANT,
436   - dd->phys_base + AES_REG_DATA, 0, 4);
437   -
438   - omap_set_dma_dest_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
439   - omap_set_dma_src_burst_mode(dd->dma_lch_in, OMAP_DMA_DATA_BURST_4);
440   -
441 448 omap_set_dma_transfer_params(dd->dma_lch_in, OMAP_DMA_DATA_TYPE_S32,
442 449 len32, 1, OMAP_DMA_SYNC_PACKET, dd->dma_in,
443 450 OMAP_DMA_DST_SYNC);
... ... @@ -446,12 +453,6 @@
446 453 dma_addr_in, 0, 0);
447 454  
448 455 /* OUT */
449   - omap_set_dma_src_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_CONSTANT,
450   - dd->phys_base + AES_REG_DATA, 0, 4);
451   -
452   - omap_set_dma_src_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
453   - omap_set_dma_dest_burst_mode(dd->dma_lch_out, OMAP_DMA_DATA_BURST_4);
454   -
455 456 omap_set_dma_transfer_params(dd->dma_lch_out, OMAP_DMA_DATA_TYPE_S32,
456 457 len32, 1, OMAP_DMA_SYNC_PACKET,
457 458 dd->dma_out, OMAP_DMA_SRC_SYNC);
458 459  
... ... @@ -459,13 +460,13 @@
459 460 omap_set_dma_dest_params(dd->dma_lch_out, 0, OMAP_DMA_AMODE_POST_INC,
460 461 dma_addr_out, 0, 0);
461 462  
462   - err = omap_aes_write_ctrl(dd);
463   - if (err)
464   - return err;
465   -
466 463 omap_start_dma(dd->dma_lch_in);
467 464 omap_start_dma(dd->dma_lch_out);
468 465  
  466 + /* start DMA or disable idle mode */
  467 + omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START,
  468 + AES_REG_MASK_START);
  469 +
469 470 return 0;
470 471 }
471 472  
... ... @@ -545,6 +546,7 @@
545 546  
546 547 pr_debug("err: %d\n", err);
547 548  
  549 + clk_disable(dd->iclk);
548 550 dd->flags &= ~FLAGS_BUSY;
549 551  
550 552 req->base.complete(&req->base, err);
... ... @@ -562,8 +564,6 @@
562 564 omap_stop_dma(dd->dma_lch_in);
563 565 omap_stop_dma(dd->dma_lch_out);
564 566  
565   - clk_disable(dd->iclk);
566   -
567 567 if (dd->flags & FLAGS_FAST) {
568 568 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
569 569 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
... ... @@ -629,7 +629,9 @@
629 629 dd->ctx = ctx;
630 630 ctx->dd = dd;
631 631  
632   - err = omap_aes_crypt_dma_start(dd);
  632 + err = omap_aes_write_ctrl(dd);
  633 + if (!err)
  634 + err = omap_aes_crypt_dma_start(dd);
633 635 if (err) {
634 636 /* aes_task will not finish it, so do it here */
635 637 omap_aes_finish_req(dd, err);