Eric Lee / linux-smarc-t335x-v3.2

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Commit 8530935d384bef1467ba76e1f4382f0f8b3c899d

Authored by Anton Blanchard
Committed by Paul Mackerras
1 parent fd5b4377ea
Exists in master and in 4 other branches v3.2_AM335xPSP_04.06.00.11, v3.2_NEWT335xPSP_04.06.00.11, v3.2_SBC_SMARTMEN, v3.2_SMARCT335xPSP_04.06.00.11

[PATCH] ppc64: remove CPU_FTR_PMC8 

Remove the CPU_FTR_PMC8 feature now we encode the number of PMCs
directly.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

Showing 2 changed files with 12 additions and 14 deletions Side-by-side Diff

arch/ppc64/kernel/cputable.c
Diff comments   View file @ 8530935
... ... @@ -54,8 +54,7 @@
54 54 .pvr_value = 0x00400000,
55 55 .cpu_name = "POWER3 (630)",
56 56 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
57   - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
58   - CPU_FTR_PMC8,
  57 + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
59 58 .cpu_user_features = COMMON_USER_PPC64,
60 59 .icache_bsize = 128,
61 60 .dcache_bsize = 128,
... ... @@ -67,8 +66,7 @@
67 66 .pvr_value = 0x00410000,
68 67 .cpu_name = "POWER3 (630+)",
69 68 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
70   - CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
71   - CPU_FTR_PMC8,
  69 + CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
72 70 .cpu_user_features = COMMON_USER_PPC64,
73 71 .icache_bsize = 128,
74 72 .dcache_bsize = 128,
... ... @@ -81,7 +79,7 @@
81 79 .cpu_name = "RS64-II (northstar)",
82 80 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
83 81 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
84   - CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  82 + CPU_FTR_MMCRA | CPU_FTR_CTRL,
85 83 .cpu_user_features = COMMON_USER_PPC64,
86 84 .icache_bsize = 128,
87 85 .dcache_bsize = 128,
... ... @@ -94,7 +92,7 @@
94 92 .cpu_name = "RS64-III (pulsar)",
95 93 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
96 94 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
97   - CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  95 + CPU_FTR_MMCRA | CPU_FTR_CTRL,
98 96 .cpu_user_features = COMMON_USER_PPC64,
99 97 .icache_bsize = 128,
100 98 .dcache_bsize = 128,
... ... @@ -107,7 +105,7 @@
107 105 .cpu_name = "RS64-III (icestar)",
108 106 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
109 107 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
110   - CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  108 + CPU_FTR_MMCRA | CPU_FTR_CTRL,
111 109 .cpu_user_features = COMMON_USER_PPC64,
112 110 .icache_bsize = 128,
113 111 .dcache_bsize = 128,
... ... @@ -120,7 +118,7 @@
120 118 .cpu_name = "RS64-IV (sstar)",
121 119 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
122 120 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
123   - CPU_FTR_PMC8 | CPU_FTR_MMCRA | CPU_FTR_CTRL,
  121 + CPU_FTR_MMCRA | CPU_FTR_CTRL,
124 122 .cpu_user_features = COMMON_USER_PPC64,
125 123 .icache_bsize = 128,
126 124 .dcache_bsize = 128,
... ... @@ -133,7 +131,7 @@
133 131 .cpu_name = "POWER4 (gp)",
134 132 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
135 133 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
136   - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  134 + CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
137 135 .cpu_user_features = COMMON_USER_PPC64,
138 136 .icache_bsize = 128,
139 137 .dcache_bsize = 128,
... ... @@ -146,7 +144,7 @@
146 144 .cpu_name = "POWER4+ (gq)",
147 145 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
148 146 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
149   - CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  147 + CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
150 148 .cpu_user_features = COMMON_USER_PPC64,
151 149 .icache_bsize = 128,
152 150 .dcache_bsize = 128,
... ... @@ -160,7 +158,7 @@
160 158 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
161 159 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
162 160 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
163   - CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  161 + CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
164 162 .cpu_user_features = COMMON_USER_PPC64 |
165 163 PPC_FEATURE_HAS_ALTIVEC_COMP,
166 164 .icache_bsize = 128,
... ... @@ -175,7 +173,7 @@
175 173 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
176 174 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
177 175 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
178   - CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  176 + CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
179 177 .cpu_user_features = COMMON_USER_PPC64 |
180 178 PPC_FEATURE_HAS_ALTIVEC_COMP,
181 179 .icache_bsize = 128,
... ... @@ -190,7 +188,7 @@
190 188 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
191 189 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
192 190 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
193   - CPU_FTR_CAN_NAP | CPU_FTR_PMC8 | CPU_FTR_MMCRA,
  191 + CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
194 192 .cpu_user_features = COMMON_USER_PPC64 |
195 193 PPC_FEATURE_HAS_ALTIVEC_COMP,
196 194 .icache_bsize = 128,
include/asm-ppc64/cputable.h
Diff comments   View file @ 8530935
... ... @@ -98,7 +98,7 @@
98 98 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
99 99 #define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
100 100 #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
101   -#define CPU_FTR_PMC8 ASM_CONST(0x0000008000000000)
  101 +/* unused ASM_CONST(0x0000008000000000) */
102 102 #define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
103 103 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
104 104 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)