ARM:omap:am33xx: move edma.h to common place

edma.h is placed in <mach/..> folder on other platforms (ex Davinci). Move edma.h in OMAP also to same folder. This will save #if or cpu_is usage in places where code is shared between omap & other platforms Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>

ARM:omap:am33xx: move edma.h to common place
edma.h is placed in <mach/..> folder on other platforms (ex Davinci). Move edma.h in OMAP also to same folder. This will save #if or cpu_is usage in places where code is shared between omap & other platforms Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Hebbar, Gururaja · Afzal Mohammed
1 parent 5961d04460
Showing 5 changed files with 236 additions and 236 deletions Side-by-side Diff
arch/arm/common/edma.c
arch/arm/include/asm/hardware/edma.h
arch/arm/mach-omap2/devices.c
arch/arm/mach-omap2/include/mach/edma.h
arch/arm/plat-omap/sdma2edma.c
@@ -20,7 +20,7 @@
 #include <linux/slab.h>
 #include <linux/io.h>
  
-#include <asm/hardware/edma.h>
+#include <mach/edma.h>
  
 /* Offsets matching "struct edmacc_param" */
 #define PARM_OPT		0x00
-/*
- * TI EDMA3 definitions
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * This EDMA3 programming framework exposes two basic kinds of resource:
- *
- *  Channel	Triggers transfers, usually from a hardware event but
- *		also manually or by "chaining" from DMA completions.
- *		Each channel is coupled to a Parameter RAM (PaRAM) slot.
- *
- *  Slot	Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- *		"set"), source and destination addresses, a link to a
- *		next PaRAM slot (if any), options for the transfer, and
- *		instructions for updating those addresses.  There are
- *		more than twice as many slots as event channels.
- *
- * Each PaRAM set describes a sequence of transfers, either for one large
- * buffer or for several discontiguous smaller buffers.  An EDMA transfer
- * is driven only from a channel, which performs the transfers specified
- * in its PaRAM slot until there are no more transfers.  When that last
- * transfer completes, the "link" field may be used to reload the channel's
- * PaRAM slot with a new transfer descriptor.
- *
- * The EDMA Channel Controller (CC) maps requests from channels into physical
- * Transfer Controller (TC) requests when the channel triggers (by hardware
- * or software events, or by chaining).  The two physical DMA channels provided
- * by the TCs are thus shared by many logical channels.
- *
- * EDMA hardware also has a "QDMA" mechanism which is not currently
- * supported through this interface.  (DSP firmware uses it though.)
- */
-
-#ifndef EDMA_H_
-#define EDMA_H_
-
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
-	unsigned int opt;
-	unsigned int src;
-	unsigned int a_b_cnt;
-	unsigned int dst;
-	unsigned int src_dst_bidx;
-	unsigned int link_bcntrld;
-	unsigned int src_dst_cidx;
-	unsigned int ccnt;
-};
-
-/* fields in edmacc_param.opt */
-#define SAM		BIT(0)
-#define DAM		BIT(1)
-#define SYNCDIM		BIT(2)
-#define STATIC		BIT(3)
-#define EDMA_FWID	(0x07 << 8)
-#define TCCMODE		BIT(11)
-#define EDMA_TCC(t)	((t) << 12)
-#define TCINTEN		BIT(20)
-#define ITCINTEN	BIT(21)
-#define TCCHEN		BIT(22)
-#define ITCCHEN		BIT(23)
-
-#define TRWORD (0x7<<2)
-#define PAENTRY (0x1ff<<5)
-
-/*ch_status paramater of callback function possible values*/
-#define DMA_COMPLETE 1
-#define DMA_CC_ERROR 2
-#define DMA_TC0_ERROR 3
-#define DMA_TC1_ERROR 4
-#define DMA_TC2_ERROR 5
-#define DMA_TC3_ERROR 6
-
-enum address_mode {
-	INCR = 0,
-	FIFO = 1
-};
-
-enum fifo_width {
-	W8BIT = 0,
-	W16BIT = 1,
-	W32BIT = 2,
-	W64BIT = 3,
-	W128BIT = 4,
-	W256BIT = 5
-};
-
-enum dma_event_q {
-	EVENTQ_0 = 0,
-	EVENTQ_1 = 1,
-	EVENTQ_2 = 2,
-	EVENTQ_3 = 3,
-	EVENTQ_DEFAULT = -1
-};
-
-enum sync_dimension {
-	ASYNC = 0,
-	ABSYNC = 1
-};
-
-#define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
-#define EDMA_CTLR(i)			((i) >> 16)
-#define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
-
-#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY		 1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-
-#define EDMA_MAX_DMACH           64
-#define EDMA_MAX_PARAMENTRY     512
-#define EDMA_MAX_CC               2
-
-
-/* Mapping of crossbar event numbers to actual DMA channels*/
-struct event_to_channel_map {
-	unsigned        xbar_event_no;
-	int		channel_no;
-};
-
-/* actual number of DMA channels and slots on this silicon */
-struct edma {
-	/* how many dma resources of each type */
-	unsigned	num_channels;
-	unsigned	num_region;
-	unsigned	num_slots;
-	unsigned	num_tc;
-	unsigned	num_cc;
-	enum dma_event_q	default_queue;
-
-	/* list of channels with no even trigger; terminated by "-1" */
-	const s8	*noevent;
-
-	/* The edma_inuse bit for each PaRAM slot is clear unless the
-	 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
-	 */
-	DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-
-	/* The edma_unused bit for each channel is clear unless
-	 * it is not being used on this platform. It uses a bit
-	 * of SOC-specific initialization code.
-	 */
-	DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
-
-	unsigned	irq_res_start;
-	unsigned	irq_res_end;
-
-	struct dma_interrupt_data {
-		void (*callback)(unsigned channel, unsigned short ch_status,
-				void *data);
-		void *data;
-	} intr_data[EDMA_MAX_DMACH];
-
-	unsigned	is_xbar;
-	unsigned	num_events;
-	struct event_to_channel_map	*xbar_event_mapping;
-};
-
-extern struct edma *edma_info[EDMA_MAX_CC];
-
-/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
-	void (*callback)(unsigned channel, u16 ch_status, void *data),
-	void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
-
-/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
-
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
-/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
-				enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
-				 enum address_mode mode, enum fifo_width);
-void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
-		u16 bcnt_rld, enum sync_dimension sync_mode);
-void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
-
-/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
-
-/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
-
-/* platform_data for EDMA driver */
-struct edma_soc_info {
-
-	/* how many dma resources of each type */
-	unsigned	n_channel;
-	unsigned	n_region;
-	unsigned	n_slot;
-	unsigned	n_tc;
-	unsigned	n_cc;
-	enum dma_event_q	default_queue;
-
-	const s16	(*rsv_chans)[2];
-	const s16	(*rsv_slots)[2];
-	const s8	(*queue_tc_mapping)[2];
-	const s8	(*queue_priority_mapping)[2];
-	unsigned	is_xbar;
-	unsigned	n_events;
-	struct event_to_channel_map    *xbar_event_mapping;
-	int		(*map_xbar_channel)(unsigned event, unsigned *channel,
-				struct event_to_channel_map *xbar_event_map);
-};
-
-#endif
@@ -29,7 +29,7 @@
 #include <asm/pmu.h>
  
 #ifdef	CONFIG_OMAP3_EDMA
-#include <asm/hardware/edma.h>
+#include <mach/edma.h>
 #endif
  
 #include <plat/tc.h>
+/*
+ * TI EDMA3 definitions
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This EDMA3 programming framework exposes two basic kinds of resource:
+ *
+ *  Channel	Triggers transfers, usually from a hardware event but
+ *		also manually or by "chaining" from DMA completions.
+ *		Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *
+ *  Slot	Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ *		"set"), source and destination addresses, a link to a
+ *		next PaRAM slot (if any), options for the transfer, and
+ *		instructions for updating those addresses.  There are
+ *		more than twice as many slots as event channels.
+ *
+ * Each PaRAM set describes a sequence of transfers, either for one large
+ * buffer or for several discontiguous smaller buffers.  An EDMA transfer
+ * is driven only from a channel, which performs the transfers specified
+ * in its PaRAM slot until there are no more transfers.  When that last
+ * transfer completes, the "link" field may be used to reload the channel's
+ * PaRAM slot with a new transfer descriptor.
+ *
+ * The EDMA Channel Controller (CC) maps requests from channels into physical
+ * Transfer Controller (TC) requests when the channel triggers (by hardware
+ * or software events, or by chaining).  The two physical DMA channels provided
+ * by the TCs are thus shared by many logical channels.
+ *
+ * EDMA hardware also has a "QDMA" mechanism which is not currently
+ * supported through this interface.  (DSP firmware uses it though.)
+ */
+
+#ifndef EDMA_H_
+#define EDMA_H_
+
+/* PaRAM slots are laid out like this */
+struct edmacc_param {
+	unsigned int opt;
+	unsigned int src;
+	unsigned int a_b_cnt;
+	unsigned int dst;
+	unsigned int src_dst_bidx;
+	unsigned int link_bcntrld;
+	unsigned int src_dst_cidx;
+	unsigned int ccnt;
+};
+
+/* fields in edmacc_param.opt */
+#define SAM		BIT(0)
+#define DAM		BIT(1)
+#define SYNCDIM		BIT(2)
+#define STATIC		BIT(3)
+#define EDMA_FWID	(0x07 << 8)
+#define TCCMODE		BIT(11)
+#define EDMA_TCC(t)	((t) << 12)
+#define TCINTEN		BIT(20)
+#define ITCINTEN	BIT(21)
+#define TCCHEN		BIT(22)
+#define ITCCHEN		BIT(23)
+
+#define TRWORD (0x7<<2)
+#define PAENTRY (0x1ff<<5)
+
+/*ch_status paramater of callback function possible values*/
+#define DMA_COMPLETE 1
+#define DMA_CC_ERROR 2
+#define DMA_TC0_ERROR 3
+#define DMA_TC1_ERROR 4
+#define DMA_TC2_ERROR 5
+#define DMA_TC3_ERROR 6
+
+enum address_mode {
+	INCR = 0,
+	FIFO = 1
+};
+
+enum fifo_width {
+	W8BIT = 0,
+	W16BIT = 1,
+	W32BIT = 2,
+	W64BIT = 3,
+	W128BIT = 4,
+	W256BIT = 5
+};
+
+enum dma_event_q {
+	EVENTQ_0 = 0,
+	EVENTQ_1 = 1,
+	EVENTQ_2 = 2,
+	EVENTQ_3 = 3,
+	EVENTQ_DEFAULT = -1
+};
+
+enum sync_dimension {
+	ASYNC = 0,
+	ABSYNC = 1
+};
+
+#define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i)			((i) >> 16)
+#define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
+
+#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY		 1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
+
+#define EDMA_MAX_DMACH           64
+#define EDMA_MAX_PARAMENTRY     512
+#define EDMA_MAX_CC               2
+
+
+/* Mapping of crossbar event numbers to actual DMA channels*/
+struct event_to_channel_map {
+	unsigned        xbar_event_no;
+	int		channel_no;
+};
+
+/* actual number of DMA channels and slots on this silicon */
+struct edma {
+	/* how many dma resources of each type */
+	unsigned	num_channels;
+	unsigned	num_region;
+	unsigned	num_slots;
+	unsigned	num_tc;
+	unsigned	num_cc;
+	enum dma_event_q	default_queue;
+
+	/* list of channels with no even trigger; terminated by "-1" */
+	const s8	*noevent;
+
+	/* The edma_inuse bit for each PaRAM slot is clear unless the
+	 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+	 */
+	DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+
+	/* The edma_unused bit for each channel is clear unless
+	 * it is not being used on this platform. It uses a bit
+	 * of SOC-specific initialization code.
+	 */
+	DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
+
+	unsigned	irq_res_start;
+	unsigned	irq_res_end;
+
+	struct dma_interrupt_data {
+		void (*callback)(unsigned channel, unsigned short ch_status,
+				void *data);
+		void *data;
+	} intr_data[EDMA_MAX_DMACH];
+
+	unsigned	is_xbar;
+	unsigned	num_events;
+	struct event_to_channel_map	*xbar_event_mapping;
+};
+
+extern struct edma *edma_info[EDMA_MAX_CC];
+
+/* alloc/free DMA channels and their dedicated parameter RAM slots */
+int edma_alloc_channel(int channel,
+	void (*callback)(unsigned channel, u16 ch_status, void *data),
+	void *data, enum dma_event_q);
+void edma_free_channel(unsigned channel);
+
+/* alloc/free parameter RAM slots */
+int edma_alloc_slot(unsigned ctlr, int slot);
+void edma_free_slot(unsigned slot);
+
+/* alloc/free a set of contiguous parameter RAM slots */
+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
+int edma_free_cont_slots(unsigned slot, int count);
+
+/* calls that operate on part of a parameter RAM slot */
+void edma_set_src(unsigned slot, dma_addr_t src_port,
+				enum address_mode mode, enum fifo_width);
+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
+				 enum address_mode mode, enum fifo_width);
+void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
+		u16 bcnt_rld, enum sync_dimension sync_mode);
+void edma_link(unsigned from, unsigned to);
+void edma_unlink(unsigned from);
+
+/* calls that operate on an entire parameter RAM slot */
+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
+void edma_read_slot(unsigned slot, struct edmacc_param *params);
+
+/* channel control operations */
+int edma_start(unsigned channel);
+void edma_stop(unsigned channel);
+void edma_clean_channel(unsigned channel);
+void edma_clear_event(unsigned channel);
+void edma_pause(unsigned channel);
+void edma_resume(unsigned channel);
+
+/* platform_data for EDMA driver */
+struct edma_soc_info {
+
+	/* how many dma resources of each type */
+	unsigned	n_channel;
+	unsigned	n_region;
+	unsigned	n_slot;
+	unsigned	n_tc;
+	unsigned	n_cc;
+	enum dma_event_q	default_queue;
+
+	const s16	(*rsv_chans)[2];
+	const s16	(*rsv_slots)[2];
+	const s8	(*queue_tc_mapping)[2];
+	const s8	(*queue_priority_mapping)[2];
+	unsigned	is_xbar;
+	unsigned	n_events;
+	struct event_to_channel_map    *xbar_event_mapping;
+	int		(*map_xbar_channel)(unsigned event, unsigned *channel,
+				struct event_to_channel_map *xbar_event_map);
+};
+
+#endif
@@ -39,7 +39,7 @@
 #include <plat/tc.h>
  
 /* some edma specific hacks which might change */
-#include <asm/hardware/edma.h>
+#include <mach/edma.h>
  
 /**
  * omap_request_dma - allocate DMA channel and paired parameter RAM
...	...	@@ -20,7 +20,7 @@
20	20	#include <linux/slab.h>
21	21	#include <linux/io.h>
22	22
23		-#include <asm/hardware/edma.h>
	23	+#include <mach/edma.h>
24	24
25	25	/* Offsets matching "struct edmacc_param" */
26	26	#define PARM_OPT 0x00
1		-/*
2		- * TI EDMA3 definitions
3		- *
4		- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5		- *
6		- * This program is free software; you can redistribute it and/or
7		- * modify it under the terms of the GNU General Public License as
8		- * published by the Free Software Foundation version 2.
9		- *
10		- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11		- * kind, whether express or implied; without even the implied warranty
12		- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13		- * GNU General Public License for more details.
14		- */
15		-
16		-/*
17		- * This EDMA3 programming framework exposes two basic kinds of resource:
18		- *
19		- * Channel Triggers transfers, usually from a hardware event but
20		- * also manually or by "chaining" from DMA completions.
21		- * Each channel is coupled to a Parameter RAM (PaRAM) slot.
22		- *
23		- * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
24		- * "set"), source and destination addresses, a link to a
25		- * next PaRAM slot (if any), options for the transfer, and
26		- * instructions for updating those addresses. There are
27		- * more than twice as many slots as event channels.
28		- *
29		- * Each PaRAM set describes a sequence of transfers, either for one large
30		- * buffer or for several discontiguous smaller buffers. An EDMA transfer
31		- * is driven only from a channel, which performs the transfers specified
32		- * in its PaRAM slot until there are no more transfers. When that last
33		- * transfer completes, the "link" field may be used to reload the channel's
34		- * PaRAM slot with a new transfer descriptor.
35		- *
36		- * The EDMA Channel Controller (CC) maps requests from channels into physical
37		- * Transfer Controller (TC) requests when the channel triggers (by hardware
38		- * or software events, or by chaining). The two physical DMA channels provided
39		- * by the TCs are thus shared by many logical channels.
40		- *
41		- * EDMA hardware also has a "QDMA" mechanism which is not currently
42		- * supported through this interface. (DSP firmware uses it though.)
43		- */
44		-
45		-#ifndef EDMA_H_
46		-#define EDMA_H_
47		-
48		-/* PaRAM slots are laid out like this */
49		-struct edmacc_param {
50		- unsigned int opt;
51		- unsigned int src;
52		- unsigned int a_b_cnt;
53		- unsigned int dst;
54		- unsigned int src_dst_bidx;
55		- unsigned int link_bcntrld;
56		- unsigned int src_dst_cidx;
57		- unsigned int ccnt;
58		-};
59		-
60		-/* fields in edmacc_param.opt */
61		-#define SAM BIT(0)
62		-#define DAM BIT(1)
63		-#define SYNCDIM BIT(2)
64		-#define STATIC BIT(3)
65		-#define EDMA_FWID (0x07 << 8)
66		-#define TCCMODE BIT(11)
67		-#define EDMA_TCC(t) ((t) << 12)
68		-#define TCINTEN BIT(20)
69		-#define ITCINTEN BIT(21)
70		-#define TCCHEN BIT(22)
71		-#define ITCCHEN BIT(23)
72		-
73		-#define TRWORD (0x7<<2)
74		-#define PAENTRY (0x1ff<<5)
75		-
76		-/ch_status paramater of callback function possible values/
77		-#define DMA_COMPLETE 1
78		-#define DMA_CC_ERROR 2
79		-#define DMA_TC0_ERROR 3
80		-#define DMA_TC1_ERROR 4
81		-#define DMA_TC2_ERROR 5
82		-#define DMA_TC3_ERROR 6
83		-
84		-enum address_mode {
85		- INCR = 0,
86		- FIFO = 1
87		-};
88		-
89		-enum fifo_width {
90		- W8BIT = 0,
91		- W16BIT = 1,
92		- W32BIT = 2,
93		- W64BIT = 3,
94		- W128BIT = 4,
95		- W256BIT = 5
96		-};
97		-
98		-enum dma_event_q {
99		- EVENTQ_0 = 0,
100		- EVENTQ_1 = 1,
101		- EVENTQ_2 = 2,
102		- EVENTQ_3 = 3,
103		- EVENTQ_DEFAULT = -1
104		-};
105		-
106		-enum sync_dimension {
107		- ASYNC = 0,
108		- ABSYNC = 1
109		-};
110		-
111		-#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) \| (chan))
112		-#define EDMA_CTLR(i) ((i) >> 16)
113		-#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
114		-
115		-#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
116		-#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
117		-#define EDMA_CONT_PARAMS_ANY 1001
118		-#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
119		-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
120		-
121		-#define EDMA_MAX_DMACH 64
122		-#define EDMA_MAX_PARAMENTRY 512
123		-#define EDMA_MAX_CC 2
124		-
125		-
126		-/* Mapping of crossbar event numbers to actual DMA channels*/
127		-struct event_to_channel_map {
128		- unsigned xbar_event_no;
129		- int channel_no;
130		-};
131		-
132		-/* actual number of DMA channels and slots on this silicon */
133		-struct edma {
134		- /* how many dma resources of each type */
135		- unsigned num_channels;
136		- unsigned num_region;
137		- unsigned num_slots;
138		- unsigned num_tc;
139		- unsigned num_cc;
140		- enum dma_event_q default_queue;
141		-
142		- /* list of channels with no even trigger; terminated by "-1" */
143		- const s8 *noevent;
144		-
145		- /* The edma_inuse bit for each PaRAM slot is clear unless the
146		- * channel is in use ... by ARM or DSP, for QDMA, or whatever.
147		- */
148		- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
149		-
150		- /* The edma_unused bit for each channel is clear unless
151		- * it is not being used on this platform. It uses a bit
152		- * of SOC-specific initialization code.
153		- */
154		- DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
155		-
156		- unsigned irq_res_start;
157		- unsigned irq_res_end;
158		-
159		- struct dma_interrupt_data {
160		- void (*callback)(unsigned channel, unsigned short ch_status,
161		- void *data);
162		- void *data;
163		- } intr_data[EDMA_MAX_DMACH];
164		-
165		- unsigned is_xbar;
166		- unsigned num_events;
167		- struct event_to_channel_map *xbar_event_mapping;
168		-};
169		-
170		-extern struct edma *edma_info[EDMA_MAX_CC];
171		-
172		-/* alloc/free DMA channels and their dedicated parameter RAM slots */
173		-int edma_alloc_channel(int channel,
174		- void (callback)(unsigned channel, u16 ch_status, void data),
175		- void *data, enum dma_event_q);
176		-void edma_free_channel(unsigned channel);
177		-
178		-/* alloc/free parameter RAM slots */
179		-int edma_alloc_slot(unsigned ctlr, int slot);
180		-void edma_free_slot(unsigned slot);
181		-
182		-/* alloc/free a set of contiguous parameter RAM slots */
183		-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
184		-int edma_free_cont_slots(unsigned slot, int count);
185		-
186		-/* calls that operate on part of a parameter RAM slot */
187		-void edma_set_src(unsigned slot, dma_addr_t src_port,
188		- enum address_mode mode, enum fifo_width);
189		-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
190		- enum address_mode mode, enum fifo_width);
191		-void edma_get_position(unsigned slot, dma_addr_t src, dma_addr_t dst);
192		-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
193		-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
194		-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
195		- u16 bcnt_rld, enum sync_dimension sync_mode);
196		-void edma_link(unsigned from, unsigned to);
197		-void edma_unlink(unsigned from);
198		-
199		-/* calls that operate on an entire parameter RAM slot */
200		-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
201		-void edma_read_slot(unsigned slot, struct edmacc_param *params);
202		-
203		-/* channel control operations */
204		-int edma_start(unsigned channel);
205		-void edma_stop(unsigned channel);
206		-void edma_clean_channel(unsigned channel);
207		-void edma_clear_event(unsigned channel);
208		-void edma_pause(unsigned channel);
209		-void edma_resume(unsigned channel);
210		-
211		-/* platform_data for EDMA driver */
212		-struct edma_soc_info {
213		-
214		- /* how many dma resources of each type */
215		- unsigned n_channel;
216		- unsigned n_region;
217		- unsigned n_slot;
218		- unsigned n_tc;
219		- unsigned n_cc;
220		- enum dma_event_q default_queue;
221		-
222		- const s16 (*rsv_chans)[2];
223		- const s16 (*rsv_slots)[2];
224		- const s8 (*queue_tc_mapping)[2];
225		- const s8 (*queue_priority_mapping)[2];
226		- unsigned is_xbar;
227		- unsigned n_events;
228		- struct event_to_channel_map *xbar_event_mapping;
229		- int (map_xbar_channel)(unsigned event, unsigned channel,
230		- struct event_to_channel_map *xbar_event_map);
231		-};
232		-
233		-#endif
...	...	@@ -29,7 +29,7 @@
29	29	#include <asm/pmu.h>
30	30
31	31	#ifdef CONFIG_OMAP3_EDMA
32		-#include <asm/hardware/edma.h>
	32	+#include <mach/edma.h>
33	33	#endif
34	34
35	35	#include <plat/tc.h>
	1	+/*
	2	+ * TI EDMA3 definitions
	3	+ *
	4	+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or
	7	+ * modify it under the terms of the GNU General Public License as
	8	+ * published by the Free Software Foundation version 2.
	9	+ *
	10	+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	+ * kind, whether express or implied; without even the implied warranty
	12	+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+ * GNU General Public License for more details.
	14	+ */
	15	+
	16	+/*
	17	+ * This EDMA3 programming framework exposes two basic kinds of resource:
	18	+ *
	19	+ * Channel Triggers transfers, usually from a hardware event but
	20	+ * also manually or by "chaining" from DMA completions.
	21	+ * Each channel is coupled to a Parameter RAM (PaRAM) slot.
	22	+ *
	23	+ * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
	24	+ * "set"), source and destination addresses, a link to a
	25	+ * next PaRAM slot (if any), options for the transfer, and
	26	+ * instructions for updating those addresses. There are
	27	+ * more than twice as many slots as event channels.
	28	+ *
	29	+ * Each PaRAM set describes a sequence of transfers, either for one large
	30	+ * buffer or for several discontiguous smaller buffers. An EDMA transfer
	31	+ * is driven only from a channel, which performs the transfers specified
	32	+ * in its PaRAM slot until there are no more transfers. When that last
	33	+ * transfer completes, the "link" field may be used to reload the channel's
	34	+ * PaRAM slot with a new transfer descriptor.
	35	+ *
	36	+ * The EDMA Channel Controller (CC) maps requests from channels into physical
	37	+ * Transfer Controller (TC) requests when the channel triggers (by hardware
	38	+ * or software events, or by chaining). The two physical DMA channels provided
	39	+ * by the TCs are thus shared by many logical channels.
	40	+ *
	41	+ * EDMA hardware also has a "QDMA" mechanism which is not currently
	42	+ * supported through this interface. (DSP firmware uses it though.)
	43	+ */
	44	+
	45	+#ifndef EDMA_H_
	46	+#define EDMA_H_
	47	+
	48	+/* PaRAM slots are laid out like this */
	49	+struct edmacc_param {
	50	+ unsigned int opt;
	51	+ unsigned int src;
	52	+ unsigned int a_b_cnt;
	53	+ unsigned int dst;
	54	+ unsigned int src_dst_bidx;
	55	+ unsigned int link_bcntrld;
	56	+ unsigned int src_dst_cidx;
	57	+ unsigned int ccnt;
	58	+};
	59	+
	60	+/* fields in edmacc_param.opt */
	61	+#define SAM BIT(0)
	62	+#define DAM BIT(1)
	63	+#define SYNCDIM BIT(2)
	64	+#define STATIC BIT(3)
	65	+#define EDMA_FWID (0x07 << 8)
	66	+#define TCCMODE BIT(11)
	67	+#define EDMA_TCC(t) ((t) << 12)
	68	+#define TCINTEN BIT(20)
	69	+#define ITCINTEN BIT(21)
	70	+#define TCCHEN BIT(22)
	71	+#define ITCCHEN BIT(23)
	72	+
	73	+#define TRWORD (0x7<<2)
	74	+#define PAENTRY (0x1ff<<5)
	75	+
	76	+/ch_status paramater of callback function possible values/
	77	+#define DMA_COMPLETE 1
	78	+#define DMA_CC_ERROR 2
	79	+#define DMA_TC0_ERROR 3
	80	+#define DMA_TC1_ERROR 4
	81	+#define DMA_TC2_ERROR 5
	82	+#define DMA_TC3_ERROR 6
	83	+
	84	+enum address_mode {
	85	+ INCR = 0,
	86	+ FIFO = 1
	87	+};
	88	+
	89	+enum fifo_width {
	90	+ W8BIT = 0,
	91	+ W16BIT = 1,
	92	+ W32BIT = 2,
	93	+ W64BIT = 3,
	94	+ W128BIT = 4,
	95	+ W256BIT = 5
	96	+};
	97	+
	98	+enum dma_event_q {
	99	+ EVENTQ_0 = 0,
	100	+ EVENTQ_1 = 1,
	101	+ EVENTQ_2 = 2,
	102	+ EVENTQ_3 = 3,
	103	+ EVENTQ_DEFAULT = -1
	104	+};
	105	+
	106	+enum sync_dimension {
	107	+ ASYNC = 0,
	108	+ ABSYNC = 1
	109	+};
	110	+
	111	+#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) \| (chan))
	112	+#define EDMA_CTLR(i) ((i) >> 16)
	113	+#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
	114	+
	115	+#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
	116	+#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
	117	+#define EDMA_CONT_PARAMS_ANY 1001
	118	+#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
	119	+#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
	120	+
	121	+#define EDMA_MAX_DMACH 64
	122	+#define EDMA_MAX_PARAMENTRY 512
	123	+#define EDMA_MAX_CC 2
	124	+
	125	+
	126	+/* Mapping of crossbar event numbers to actual DMA channels*/
	127	+struct event_to_channel_map {
	128	+ unsigned xbar_event_no;
	129	+ int channel_no;
	130	+};
	131	+
	132	+/* actual number of DMA channels and slots on this silicon */
	133	+struct edma {
	134	+ /* how many dma resources of each type */
	135	+ unsigned num_channels;
	136	+ unsigned num_region;
	137	+ unsigned num_slots;
	138	+ unsigned num_tc;
	139	+ unsigned num_cc;
	140	+ enum dma_event_q default_queue;
	141	+
	142	+ /* list of channels with no even trigger; terminated by "-1" */
	143	+ const s8 *noevent;
	144	+
	145	+ /* The edma_inuse bit for each PaRAM slot is clear unless the
	146	+ * channel is in use ... by ARM or DSP, for QDMA, or whatever.
	147	+ */
	148	+ DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
	149	+
	150	+ /* The edma_unused bit for each channel is clear unless
	151	+ * it is not being used on this platform. It uses a bit
	152	+ * of SOC-specific initialization code.
	153	+ */
	154	+ DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
	155	+
	156	+ unsigned irq_res_start;
	157	+ unsigned irq_res_end;
	158	+
	159	+ struct dma_interrupt_data {
	160	+ void (*callback)(unsigned channel, unsigned short ch_status,
	161	+ void *data);
	162	+ void *data;
	163	+ } intr_data[EDMA_MAX_DMACH];
	164	+
	165	+ unsigned is_xbar;
	166	+ unsigned num_events;
	167	+ struct event_to_channel_map *xbar_event_mapping;
	168	+};
	169	+
	170	+extern struct edma *edma_info[EDMA_MAX_CC];
	171	+
	172	+/* alloc/free DMA channels and their dedicated parameter RAM slots */
	173	+int edma_alloc_channel(int channel,
	174	+ void (callback)(unsigned channel, u16 ch_status, void data),
	175	+ void *data, enum dma_event_q);
	176	+void edma_free_channel(unsigned channel);
	177	+
	178	+/* alloc/free parameter RAM slots */
	179	+int edma_alloc_slot(unsigned ctlr, int slot);
	180	+void edma_free_slot(unsigned slot);
	181	+
	182	+/* alloc/free a set of contiguous parameter RAM slots */
	183	+int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
	184	+int edma_free_cont_slots(unsigned slot, int count);
	185	+
	186	+/* calls that operate on part of a parameter RAM slot */
	187	+void edma_set_src(unsigned slot, dma_addr_t src_port,
	188	+ enum address_mode mode, enum fifo_width);
	189	+void edma_set_dest(unsigned slot, dma_addr_t dest_port,
	190	+ enum address_mode mode, enum fifo_width);
	191	+void edma_get_position(unsigned slot, dma_addr_t src, dma_addr_t dst);
	192	+void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
	193	+void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
	194	+void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
	195	+ u16 bcnt_rld, enum sync_dimension sync_mode);
	196	+void edma_link(unsigned from, unsigned to);
	197	+void edma_unlink(unsigned from);
	198	+
	199	+/* calls that operate on an entire parameter RAM slot */
	200	+void edma_write_slot(unsigned slot, const struct edmacc_param *params);
	201	+void edma_read_slot(unsigned slot, struct edmacc_param *params);
	202	+
	203	+/* channel control operations */
	204	+int edma_start(unsigned channel);
	205	+void edma_stop(unsigned channel);
	206	+void edma_clean_channel(unsigned channel);
	207	+void edma_clear_event(unsigned channel);
	208	+void edma_pause(unsigned channel);
	209	+void edma_resume(unsigned channel);
	210	+
	211	+/* platform_data for EDMA driver */
	212	+struct edma_soc_info {
	213	+
	214	+ /* how many dma resources of each type */
	215	+ unsigned n_channel;
	216	+ unsigned n_region;
	217	+ unsigned n_slot;
	218	+ unsigned n_tc;
	219	+ unsigned n_cc;
	220	+ enum dma_event_q default_queue;
	221	+
	222	+ const s16 (*rsv_chans)[2];
	223	+ const s16 (*rsv_slots)[2];
	224	+ const s8 (*queue_tc_mapping)[2];
	225	+ const s8 (*queue_priority_mapping)[2];
	226	+ unsigned is_xbar;
	227	+ unsigned n_events;
	228	+ struct event_to_channel_map *xbar_event_mapping;
	229	+ int (map_xbar_channel)(unsigned event, unsigned channel,
	230	+ struct event_to_channel_map *xbar_event_map);
	231	+};
	232	+
	233	+#endif
...	...	@@ -39,7 +39,7 @@
39	39	#include <plat/tc.h>
40	40
41	41	/* some edma specific hacks which might change */
42		-#include <asm/hardware/edma.h>
	42	+#include <mach/edma.h>
43	43
44	44	/**
45	45	* omap_request_dma - allocate DMA channel and paired parameter RAM